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| author | Gabor Juhos <juhosg@openwrt.org> | 2008-11-26 17:17:13 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2008-11-26 17:17:13 +0000 |
| commit | a0db668dea0071a5a8931fbecbf33b577fc732d7 (patch) | |
| tree | eb5e5d3e8abfab3842bf851fed8df7ea3707af20 /target/linux/ar71xx/files/include | |
| parent | 8d9ff98b67cdd0d551acefa4310ffbcc0374809e (diff) | |
| download | upstream-a0db668dea0071a5a8931fbecbf33b577fc732d7.tar.gz upstream-a0db668dea0071a5a8931fbecbf33b577fc732d7.tar.bz2 upstream-a0db668dea0071a5a8931fbecbf33b577fc732d7.zip | |
[ar71xx] rename DDR registers
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13363 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/include')
| -rw-r--r-- | target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h index 8dbe021614..322f3c2ec7 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h @@ -207,18 +207,18 @@ extern void ar71xx_gpio_function_disable(u32 mask); /* * DDR_CTRL block */ -#define DDR_REG_PCI_WIN0 0x7c -#define DDR_REG_PCI_WIN1 0x80 -#define DDR_REG_PCI_WIN2 0x84 -#define DDR_REG_PCI_WIN3 0x88 -#define DDR_REG_PCI_WIN4 0x8c -#define DDR_REG_PCI_WIN5 0x90 -#define DDR_REG_PCI_WIN6 0x94 -#define DDR_REG_PCI_WIN7 0x98 -#define DDR_REG_FLUSH_GE0 0x9c -#define DDR_REG_FLUSH_GE1 0xa0 -#define DDR_REG_FLUSH_USB 0xa4 -#define DDR_REG_FLUSH_PCI 0xa8 +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 #define PCI_WIN0_OFFS 0x10000000 #define PCI_WIN1_OFFS 0x11000000 |