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authorDavid Bauer <mail@david-bauer.net>2018-08-06 16:15:04 +0200
committerJohn Crispin <john@phrozen.org>2018-08-08 15:48:57 +0200
commitf4f99ec9737c653815268f2efad0210caaa32e2d (patch)
treeb0aa4b6488ecfbd36f6f11b1cd7da75cc3fb9d0f /target/linux/ar71xx/files/drivers
parentfbe17867daddf76ec26be7dbf6b9af3cfad4a54f (diff)
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ar71xx: fix QCA955X SGMII link loss
The QCA955X is affected by a hardware bug which causes link-loss of the SGMII link between SoC and PHY. This happens on change of link-state or speed. It is not really known what causes this bug. It definitely occurs when using a AR8033 Gigabit Ethernet PHY. Qualcomm solves this Bug in a similar fashion. We need to apply the fix on a per-device base via platform-data as performing the fixup work will break connectivity in case the SGMII interface is connected to a Switch. This bug was first proposed to be fixed by Sven Eckelmann in 2016. https://patchwork.ozlabs.org/patch/604782/ Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux/ar71xx/files/drivers')
-rw-r--r--target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h2
-rw-r--r--target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c79
2 files changed, 81 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
index 77ee5b36ec..2d9a865043 100644
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
@@ -66,6 +66,8 @@
#define AG71XX_TX_RING_SIZE_MAX 128
#define AG71XX_RX_RING_SIZE_MAX 256
+#define QCA955X_SGMII_LINK_WAR_MAX_TRY 10
+
#ifdef CONFIG_AG71XX_DEBUG
#define DBG(fmt, args...) pr_debug(fmt, ## args)
#else
diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 54ec8e67b3..109335ef0f 100644
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -31,6 +31,7 @@ MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
#define ETH_SWITCH_HEADER_LEN 2
static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
+static void ag71xx_qca955x_sgmii_init(void);
static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
{
@@ -610,6 +611,9 @@ __ag71xx_link_adjust(struct ag71xx *ag, bool update)
if (update && pdata->set_speed)
pdata->set_speed(ag->speed);
+ if (update && pdata->enable_sgmii_fixup)
+ ag71xx_qca955x_sgmii_init();
+
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
@@ -913,6 +917,81 @@ static void ag71xx_tx_timeout(struct net_device *dev)
schedule_delayed_work(&ag->restart_work, 1);
}
+static void ag71xx_bit_set(void __iomem *reg, u32 bit)
+{
+ u32 val = __raw_readl(reg) | bit;
+ __raw_writel(val, reg);
+ __raw_readl(reg);
+}
+
+static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
+{
+ u32 val = __raw_readl(reg) & ~bit;
+ __raw_writel(val, reg);
+ __raw_readl(reg);
+}
+
+static void ag71xx_qca955x_sgmii_init()
+{
+ void __iomem *gmac_base;
+ u32 mr_an_status, sgmii_status;
+ u8 tries = 0;
+
+ gmac_base = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ if (!gmac_base)
+ goto sgmii_out;
+
+ mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
+ if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
+ goto sgmii_out;
+
+ __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET ,
+ gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
+ __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
+ udelay(10);
+
+ /* Init sequence */
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_HW_RX_125M_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_RX_125M_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_TX_125M_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_RX_CLK_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_TX_CLK_N);
+ udelay(10);
+
+ do {
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
+ QCA955X_MR_AN_CONTROL_PHY_RESET |
+ QCA955X_MR_AN_CONTROL_AN_ENABLE);
+ udelay(100);
+ ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
+ QCA955X_MR_AN_CONTROL_PHY_RESET);
+ mdelay(10);
+ sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) & 0xF;
+
+ if (tries++ >= QCA955X_SGMII_LINK_WAR_MAX_TRY) {
+ pr_warn("ag71xx: max retries for SGMII fixup exceeded!\n");
+ break;
+ }
+ } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
+
+sgmii_out:
+ iounmap(gmac_base);
+}
+
static void ag71xx_restart_work_func(struct work_struct *work)
{
struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);