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authorGabor Juhos <juhosg@openwrt.org>2008-11-27 18:54:58 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-11-27 18:54:58 +0000
commitd841d5cfc70b38f85660f82d41ad803087db5272 (patch)
treed9673fac7d3d393f3370a9071f25cc974928514e /target/linux/ar71xx/files/drivers/net/ag71xx
parent74932eb40a19478fdeab8500afd487f3300bc919 (diff)
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ag71xx driver: use SoC specific PLL values
SVN-Revision: 13377
Diffstat (limited to 'target/linux/ar71xx/files/drivers/net/ag71xx')
-rw-r--r--target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c28
1 files changed, 15 insertions, 13 deletions
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
index cedbfe616b..aa9a74f34a 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c
@@ -27,15 +27,13 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
return "?";
}
-#if 1
-#define PLL_VAL_1000 0x00110000
-#define PLL_VAL_100 0x00001099
-#define PLL_VAL_10 0x00991099
-#else
-#define PLL_VAL_1000 0x01111000
-#define PLL_VAL_100 0x09991000
-#define PLL_VAL_10 0x09991999
-#endif
+#define AR71XX_PLL_VAL_1000 0x00110000
+#define AR71XX_PLL_VAL_100 0x00001099
+#define AR71XX_PLL_VAL_10 0x00991099
+
+#define AR91XX_PLL_VAL_1000 0x1a000000
+#define AR91XX_PLL_VAL_100 0x13000a44
+#define AR91XX_PLL_VAL_10 0x00441099
static void ag71xx_phy_link_update(struct ag71xx *ag)
{
@@ -67,26 +65,30 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
case SPEED_1000:
mii_speed = MII_CTRL_SPEED_1000;
cfg2 |= MAC_CFG2_IF_1000;
- pll = PLL_VAL_1000;
+ pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
+ : AR71XX_PLL_VAL_1000;
fifo5 |= FIFO_CFG5_BM;
break;
case SPEED_100:
mii_speed = MII_CTRL_SPEED_100;
cfg2 |= MAC_CFG2_IF_10_100;
ifctl |= MAC_IFCTL_SPEED;
- pll = PLL_VAL_100;
+ pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
+ : AR71XX_PLL_VAL_100;
break;
case SPEED_10:
mii_speed = MII_CTRL_SPEED_10;
cfg2 |= MAC_CFG2_IF_10_100;
- pll = PLL_VAL_10;
+ pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
+ : AR71XX_PLL_VAL_10;
break;
default:
BUG();
return;
}
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
+ pdata->is_ar91xx ? 0x780fff : 0x008001ff);
pdata->set_pll(pll);
ag71xx_mii_ctrl_set_speed(ag, mii_speed);