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authorJohn Crispin <john@openwrt.org>2015-09-16 08:33:14 +0000
committerJohn Crispin <john@openwrt.org>2015-09-16 08:33:14 +0000
commitac75fc8d98ae8fd7a6a24ac2d41e49783741d778 (patch)
treea20ba05c13e6a6169254f386a0025437a547c779 /target/linux/ar71xx/files/arch
parentf6607a4bec6dfa60d9badd37046cb61f2748f00f (diff)
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ar71xx: add support for ap152 reference board
Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> SVN-Revision: 46972
Diffstat (limited to 'target/linux/ar71xx/files/arch')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c141
1 files changed, 141 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c
new file mode 100644
index 0000000000..a1eb06b984
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c
@@ -0,0 +1,141 @@
+
+/*
+ * Qualcomm Atheros AP152 reference board support
+ *
+ * Copyright (c) 2015 Qualcomm Atheros
+ * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/ath9k_platform.h>
+#include <linux/ar8216_platform.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+#include "pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-spi.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+
+#define AP152_GPIO_LED_USB0 7
+#define AP152_GPIO_LED_USB1 8
+
+#define AP152_GPIO_BTN_RESET 2
+#define AP152_GPIO_BTN_WPS 1
+#define AP152_KEYS_POLL_INTERVAL 20 /* msecs */
+#define AP152_KEYS_DEBOUNCE_INTERVAL (3 * AP152_KEYS_POLL_INTERVAL)
+
+#define AP152_MAC0_OFFSET 0
+#define AP152_WMAC_CALDATA_OFFSET 0x1000
+
+static struct gpio_led ap152_leds_gpio[] __initdata = {
+ {
+ .name = "ap152:green:usb0",
+ .gpio = AP152_GPIO_LED_USB0,
+ .active_low = 1,
+ },
+ {
+ .name = "ap152:green:usb1",
+ .gpio = AP152_GPIO_LED_USB1,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_keys_button ap152_gpio_keys[] __initdata = {
+ {
+ .desc = "WPS button",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AP152_GPIO_BTN_WPS,
+ .active_low = 1,
+ },
+ {
+ .desc = "Reset button",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AP152_GPIO_BTN_RESET,
+ .active_low = 1,
+ },
+};
+
+static struct ar8327_pad_cfg ap152_ar8337_pad0_cfg = {
+ .mode = AR8327_PAD_MAC_SGMII,
+ .sgmii_delay_en = true,
+};
+
+static struct ar8327_platform_data ap152_ar8337_data = {
+ .pad0_cfg = &ap152_ar8337_pad0_cfg,
+ .port0_cfg = {
+ .force_link = 1,
+ .speed = AR8327_PORT_SPEED_1000,
+ .duplex = 1,
+ .txpause = 1,
+ .rxpause = 1,
+ },
+};
+
+static struct mdio_board_info ap152_mdio0_info[] = {
+ {
+ .bus_id = "ag71xx-mdio.0",
+ .phy_addr = 0,
+ .platform_data = &ap152_ar8337_data,
+ },
+};
+
+static void __init ap152_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+ ath79_register_m25p80(NULL);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap152_leds_gpio),
+ ap152_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, AP152_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ap152_gpio_keys),
+ ap152_gpio_keys);
+
+ ath79_register_usb();
+
+ platform_device_register(&ath79_mdio0_device);
+
+ mdiobus_register_board_info(ap152_mdio0_info,
+ ARRAY_SIZE(ap152_mdio0_info));
+
+ ath79_register_wmac(art + AP152_WMAC_CALDATA_OFFSET, NULL);
+ ath79_register_pci();
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP152_MAC0_OFFSET, 0);
+
+ /* GMAC0 is connected to an AR8337 switch */
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.phy_mask = BIT(0);
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
+ ath79_eth0_pll_data.pll_1000 = 0x06000000;
+
+ ath79_register_eth(0);
+}
+
+MIPS_MACHINE(ATH79_MACH_AP152, "AP152", "Qualcomm Atheros AP152 reference board",
+ ap152_setup);