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| author | John Crispin <blogic@openwrt.org> | 2016-03-01 08:14:55 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2016-03-01 08:14:55 +0000 |
| commit | d5b9846f545bb5d55157d3aa33675bdfef69b74d (patch) | |
| tree | 214d222f248f60f7552c6f661b9108c95cb1bf85 /target/linux/ar71xx/files/arch | |
| parent | da2592c20e4ac478ab875fceb588eeaf1648066b (diff) | |
| download | upstream-d5b9846f545bb5d55157d3aa33675bdfef69b74d.tar.gz upstream-d5b9846f545bb5d55157d3aa33675bdfef69b74d.tar.bz2 upstream-d5b9846f545bb5d55157d3aa33675bdfef69b74d.zip | |
ar71xx: rework patch for qca953x/956x
Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e
Changelist,
- add more register defines
- add EHCI support
- fix GPIO pin count to 18
- fix chained irq disabled
- fix GMAC0/GMAC1 initial
- fix WMAC irq number to 47
- merge the changes of dev-eth.c from the patch to file.
Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Backport of r46207
git-svn-id: svn://svn.openwrt.org/openwrt/branches/chaos_calmer@48854 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/arch')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index ae3db4c3ef..ff94e2ec37 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: mdio_dev = &ath79_mdio1_device; mdio_data = &ath79_mdio1_data; break; @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) break; case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: mdio_data->builtin_switch = 1; break; @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int id) case ATH79_SOC_QCA9533: case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pll_10 = AR934X_PLL_VAL_10; pll_100 = AR934X_PLL_VAL_100; pll_1000 = AR934X_PLL_VAL_1000; @@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; break; @@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: - case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; break; @@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: switch (pdata->phy_if_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: if (id == 0) { pdata->reset_bit = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO; @@ -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id) pdata->fifo_cfg3 = 0x01f00140; break; - case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: if (id == 0) { pdata->reset_bit = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO; @@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pdata->mii_bus_dev = &ath79_mdio1_device.dev; break; |