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authorGabor Juhos <juhosg@openwrt.org>2011-11-12 10:54:08 +0000
committerGabor Juhos <juhosg@openwrt.org>2011-11-12 10:54:08 +0000
commit43e993e5f535ad0c9edf327f64f1e808e02971e2 (patch)
treef0e67b4aeb925588b502b6b2ad87c37216bd8fe9 /target/linux/ar71xx/files/arch/mips/include
parent0939419e24fe8834b6237601573dee6a28b72b8a (diff)
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ar71xx: fix AR934X clock frequency calculation
SVN-Revision: 28973
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include')
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 97ac835dc0..87a352cc43 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -212,6 +212,7 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
#define AR934X_PLL_REG_CPU_CONFIG 0x00
+#define AR934X_PLL_REG_DDR_CONFIG 0x04
#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
@@ -372,6 +373,13 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
extern void __iomem *ar71xx_pll_base;
static inline void ar71xx_pll_wr(unsigned reg, u32 val)