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| author | Sven Eckelmann <sven@narfation.org> | 2018-01-19 14:02:09 +0100 |
|---|---|---|
| committer | Piotr Dymacz <pepe2k@gmail.com> | 2018-02-22 18:53:22 +0100 |
| commit | b1d57dadb2da0e010e157fd2383523578c9dcc2e (patch) | |
| tree | faabe75d5b6a9d5fbad77f0eb252eef998257a2b /target/linux/ar71xx/files/arch/mips/ath79/machtypes.h | |
| parent | c6bd0b48940cfbabe3fd7f9e46d125316119a7e4 (diff) | |
| download | upstream-b1d57dadb2da0e010e157fd2383523578c9dcc2e.tar.gz upstream-b1d57dadb2da0e010e157fd2383523578c9dcc2e.tar.bz2 upstream-b1d57dadb2da0e010e157fd2383523578c9dcc2e.zip | |
ar71xx: disable 40Mhz refclk for QCA953x
The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms"
datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a
40 Mhz reference clock. The register description for "Bootstrap Options"
(page 31) defines following states for the bit 4 (REF_CLK):
* 0 - CLK25 (default)
* 1 - (reserved)
Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25
Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and
then break the bootup of the system due to this incorrect interpretation.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
[refreshed patches]
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/ath79/machtypes.h')
0 files changed, 0 insertions, 0 deletions