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| author | David Bauer <mail@david-bauer.net> | 2018-08-06 16:15:04 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-08-08 15:48:57 +0200 |
| commit | f4f99ec9737c653815268f2efad0210caaa32e2d (patch) | |
| tree | b0aa4b6488ecfbd36f6f11b1cd7da75cc3fb9d0f /target/linux/ar71xx/files/arch/mips/ath79/mach-fritz450e.c | |
| parent | fbe17867daddf76ec26be7dbf6b9af3cfad4a54f (diff) | |
| download | upstream-f4f99ec9737c653815268f2efad0210caaa32e2d.tar.gz upstream-f4f99ec9737c653815268f2efad0210caaa32e2d.tar.bz2 upstream-f4f99ec9737c653815268f2efad0210caaa32e2d.zip | |
ar71xx: fix QCA955X SGMII link loss
The QCA955X is affected by a hardware bug which causes link-loss of the
SGMII link between SoC and PHY. This happens on change of link-state or
speed.
It is not really known what causes this bug. It definitely occurs when
using a AR8033 Gigabit Ethernet PHY.
Qualcomm solves this Bug in a similar fashion. We need to apply the fix
on a per-device base via platform-data as performing the fixup work will
break connectivity in case the SGMII interface is connected to a Switch.
This bug was first proposed to be fixed by Sven Eckelmann in 2016.
https://patchwork.ozlabs.org/patch/604782/
Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/ath79/mach-fritz450e.c')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-fritz450e.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-fritz450e.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-fritz450e.c index ee0a185304..e48ddd65e7 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-fritz450e.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-fritz450e.c @@ -155,6 +155,7 @@ static void __init fritz450E_setup(void) { ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth0_data.phy_mask = BIT(FRITZ450E_PHY_ADDRESS); + ath79_eth0_data.enable_sgmii_fixup = 1; ath79_eth0_pll_data.pll_1000 = 0x03000000; ath79_eth0_pll_data.pll_100 = 0x00000101; ath79_eth0_pll_data.pll_10 = 0x00001313; |