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| author | Felix Fietkau <nbd@openwrt.org> | 2015-04-20 15:00:41 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-04-20 15:00:41 +0000 |
| commit | c75a0e86b13ec1cd35b0fa56cd5c222172a1407d (patch) | |
| tree | 06877df41e2c97d1141520094b4464dfaf8383b1 /target/linux/ar71xx/base-files | |
| parent | 5c6925a23b84430782ab84eac75ade065c6adbb3 (diff) | |
| download | upstream-c75a0e86b13ec1cd35b0fa56cd5c222172a1407d.tar.gz upstream-c75a0e86b13ec1cd35b0fa56cd5c222172a1407d.tar.bz2 upstream-c75a0e86b13ec1cd35b0fa56cd5c222172a1407d.zip | |
ar71xx: add mask and shift for RXD/RDV bits in AR934X register file
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit
only specified the lower bits. The upper bits also have to be unset when the
lower bits should only be set.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45522
Diffstat (limited to 'target/linux/ar71xx/base-files')
0 files changed, 0 insertions, 0 deletions