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authorHauke Mehrtens <hauke@openwrt.org>2010-01-31 15:06:17 +0000
committerHauke Mehrtens <hauke@openwrt.org>2010-01-31 15:06:17 +0000
commitc7795f68e22e1027e1561f60107cc0be7888112f (patch)
treedf4b425f40945cf9d251f233f98a96c8eb0ce0c6 /target/linux/amazon/files/arch
parentb472315402a636111c9c6b4b99517db584a7fc9d (diff)
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[amazon] move files to correct position
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19453 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/amazon/files/arch')
-rw-r--r--target/linux/amazon/files/arch/mips/include/asm/mach-amazon/irq.h7
-rw-r--r--target/linux/amazon/files/arch/mips/include/asm/mach-amazon/mangle-port.h52
-rw-r--r--target/linux/amazon/files/arch/mips/include/asm/mach-amazon/war.h24
3 files changed, 83 insertions, 0 deletions
diff --git a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/irq.h b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/irq.h
new file mode 100644
index 0000000000..e72b7d5c11
--- /dev/null
+++ b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/irq.h
@@ -0,0 +1,7 @@
+#ifndef __AMAZON_IRQ_H
+#define __AMAZON_IRQ_H
+
+#define NR_IRQS 256
+#include_next <irq.h>
+
+#endif
diff --git a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/mangle-port.h b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/mangle-port.h
new file mode 100644
index 0000000000..af8c3e9394
--- /dev/null
+++ b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/mangle-port.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_AMAZON_MANGLE_PORT_H
+#define __ASM_MACH_AMAZON_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port) (port)
+#define __swizzle_addr_w(port) ((port) ^ 2)
+#define __swizzle_addr_l(port) (port)
+#define __swizzle_addr_q(port) (port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time. Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses. The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) le16_to_cpu(x)
+# define __mem_ioswabw(a, x) (x)
+# define ioswabl(a, x) le32_to_cpu(x)
+# define __mem_ioswabl(a, x) (x)
+# define ioswabq(a, x) le64_to_cpu(x)
+# define __mem_ioswabq(a, x) (x)
+
+#else
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (x)
+# define __mem_ioswabw(a, x) cpu_to_le16(x)
+# define ioswabl(a, x) (x)
+# define __mem_ioswabl(a, x) cpu_to_le32(x)
+# define ioswabq(a, x) (x)
+# define __mem_ioswabq(a, x) cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_AMAZON_MANGLE_PORT_H */
diff --git a/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/war.h b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/war.h
new file mode 100644
index 0000000000..da42ee5a21
--- /dev/null
+++ b/target/linux/amazon/files/arch/mips/include/asm/mach-amazon/war.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MIPS_MACH_AMAZON_WAR_H
+#define __ASM_MIPS_MACH_AMAZON_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif