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| author | Shiji Yang <yangshiji66@qq.com> | 2022-10-27 13:17:12 +0800 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2022-11-09 22:55:33 +0100 |
| commit | 8d4c22a9561dc43e81cfa15fcfdec86c052792cd (patch) | |
| tree | 9df651b3e81371485cce32f13780ec57c61aa34b /scripts/slugimage.pl | |
| parent | 520c90854ca73eb6c3d8feeda59766c90bdd4144 (diff) | |
| download | upstream-8d4c22a9561dc43e81cfa15fcfdec86c052792cd.tar.gz upstream-8d4c22a9561dc43e81cfa15fcfdec86c052792cd.tar.bz2 upstream-8d4c22a9561dc43e81cfa15fcfdec86c052792cd.zip | |
ath79: add missing clock name strings in SoC dtsi
For all SoC in the ath79 target, the PLL controller provides 3 main
clocks "cpu", "ddr" and "ahb" through the input clock "ref".
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Diffstat (limited to 'scripts/slugimage.pl')
0 files changed, 0 insertions, 0 deletions