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authorDaniel Golle <daniel@makrotopia.org>2022-09-03 01:57:08 +0100
committerDaniel Golle <daniel@makrotopia.org>2022-09-03 02:03:42 +0100
commit93e6581b900cfbead7888046c8ff7caa1eb79317 (patch)
tree2f2d30ce437a38a98ced0fcf6e950a3eefb9a152 /package
parent3889f90ee27f129340dc0ae7efccf8165e0fbe30 (diff)
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uboot-mediatek: backport fix for unstable UART on MT7622
Import pending patch "arm: dts: mt7622: force high-speed mode for uart" from Weijie Gao <weijie.gao@mediatek.com> fixing the UART problems on MT7622 which made it hard to use the U-Boot menu on devices with this SoC. This patch is also contained in commit c09eb08dad ("uboot-mediatek: add support for MT798x platforms") in the development branch. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'package')
-rw-r--r--package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch26
1 files changed, 26 insertions, 0 deletions
diff --git a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch
new file mode 100644
index 0000000000..9bd7a9e64d
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch
@@ -0,0 +1,26 @@
+From 79786aa175010dde78f95970939e8efadd7a3295 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 31 Aug 2022 19:04:34 +0800
+Subject: [PATCH 11/32] arm: dts: mt7622: force high-speed mode for uart
+
+The input clock for uart is too slow (25MHz) which introduces frequent data
+error on both receiving and transmitting even if the baudrate is 115200.
+
+Using high-speed can significantly solve this issue.
+
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ arch/arm/dts/mt7622.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/dts/mt7622.dtsi
++++ b/arch/arm/dts/mt7622.dtsi
+@@ -191,6 +191,7 @@
+ status = "disabled";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
++ mediatek,force-highspeed;
+ };
+
+ mmc0: mmc@11230000 {