sync ath9k with latest git code

SVN-Revision: 12038

15 files changed, 1972 insertions, 2638 deletions

diff --git a/package/ath9k/Makefile b/package/ath9k/Makefile
index b4ddc6d1a1..88ffa4258a 100644
--- a/package/ath9k/Makefile
+++ b/package/ath9k/Makefile
@@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=ath9k
-PKG_VERSION:=20080722
+PKG_VERSION:=20080731
 PKG_RELEASE:=1
 
 include $(INCLUDE_DIR)/package.mk
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h b/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
index ed440a036f..c3294c02fa 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
@@ -32,19 +32,19 @@
 #define	AR_SUBVENDOR_ID_NOG	0x0e11
 #define AR_SUBVENDOR_ID_NEW_A	0x7065
 
-#define	HAL_TXERR_XRETRY        0x01
-#define	HAL_TXERR_FILT	        0x02
-#define	HAL_TXERR_FIFO		0x04
-#define HAL_TXERR_XTXOP		0x08
-#define HAL_TXERR_TIMER_EXPIRED 0x10
-
-#define HAL_TX_BA               0x01
-#define HAL_TX_PWRMGMT          0x02
-#define HAL_TX_DESC_CFG_ERR     0x04
-#define HAL_TX_DATA_UNDERRUN    0x08
-#define HAL_TX_DELIM_UNDERRUN   0x10
-#define HAL_TX_SW_ABORTED       0x40
-#define HAL_TX_SW_FILTERED      0x80
+#define ATH9K_TXERR_XRETRY         0x01
+#define ATH9K_TXERR_FILT           0x02
+#define ATH9K_TXERR_FIFO           0x04
+#define ATH9K_TXERR_XTXOP          0x08
+#define ATH9K_TXERR_TIMER_EXPIRED  0x10
+
+#define ATH9K_TX_BA                0x01
+#define ATH9K_TX_PWRMGMT           0x02
+#define ATH9K_TX_DESC_CFG_ERR      0x04
+#define ATH9K_TX_DATA_UNDERRUN     0x08
+#define ATH9K_TX_DELIM_UNDERRUN    0x10
+#define ATH9K_TX_SW_ABORTED        0x40
+#define ATH9K_TX_SW_FILTERED       0x80
 
 #define NBBY    8
 #ifndef howmany
@@ -102,24 +102,19 @@ struct ath_rx_status {
 	u_int32_t evm2;
 };
 
-#define	HAL_RXERR_CRC		0x01
-#define	HAL_RXERR_PHY		0x02
-#define	HAL_RXERR_FIFO		0x04
-#define	HAL_RXERR_DECRYPT	0x08
-#define	HAL_RXERR_MIC		0x10
-
-#define HAL_RX_MORE             0x01
-#define HAL_RX_MORE_AGGR        0x02
-#define HAL_RX_GI               0x04
-#define HAL_RX_2040             0x08
-#define HAL_RX_DELIM_CRC_PRE    0x10
-#define HAL_RX_DELIM_CRC_POST   0x20
-#define HAL_RX_DECRYPT_BUSY     0x40
-
-enum hal_bool {
-	AH_FALSE = 0,
-	AH_TRUE = 1,
-};
+#define ATH9K_RXERR_CRC           0x01
+#define ATH9K_RXERR_PHY           0x02
+#define ATH9K_RXERR_FIFO          0x04
+#define ATH9K_RXERR_DECRYPT       0x08
+#define ATH9K_RXERR_MIC           0x10
+
+#define ATH9K_RX_MORE             0x01
+#define ATH9K_RX_MORE_AGGR        0x02
+#define ATH9K_RX_GI               0x04
+#define ATH9K_RX_2040             0x08
+#define ATH9K_RX_DELIM_CRC_PRE    0x10
+#define ATH9K_RX_DELIM_CRC_POST   0x20
+#define ATH9K_RX_DECRYPT_BUSY     0x40
 
 #define	HAL_RXKEYIX_INVALID	((u_int8_t)-1)
 #define	HAL_TXKEYIX_INVALID	((u_int)-1)
@@ -243,7 +238,6 @@ struct hal_ops_config {
 	u_int16_t ath_hal_antennaSwitchSwap;
 	int ath_hal_serializeRegMode;
 	int ath_hal_intrMitigation;
-	int ath_hal_debug;
 #define SPUR_DISABLE        	0
 #define SPUR_ENABLE_IOCTL   	1
 #define SPUR_ENABLE_EEPROM  	2
@@ -482,11 +476,11 @@ struct hal_channel_internal {
 	int8_t maxRegTxPower;
 	int8_t maxTxPower;
 	int8_t minTxPower;
-	enum hal_bool bssSendHere;
+	bool bssSendHere;
 	u_int8_t gainI;
-	enum hal_bool iqCalValid;
+	bool iqCalValid;
 	int32_t CalValid;
-	enum hal_bool oneTimeCalsDone;
+	bool oneTimeCalsDone;
 	int8_t iCoff;
 	int8_t qCoff;
 	int16_t rawNoiseFloor;
@@ -623,49 +617,20 @@ struct hal_country_entry {
 	u_int8_t iso[3];
 };
 
-#define HAL_DBG_RESET           0x00000001
-#define HAL_DBG_PHY_IO          0x00000002
-#define HAL_DBG_REG_IO          0x00000004
-#define HAL_DBG_RF_PARAM        0x00000008
-#define HAL_DBG_QUEUE           0x00000010
-#define HAL_DBG_EEPROM_DUMP     0x00000020
-#define HAL_DBG_EEPROM          0x00000040
-#define HAL_DBG_NF_CAL          0x00000080
-#define HAL_DBG_CALIBRATE       0x00000100
-#define HAL_DBG_CHANNEL         0x00000200
-#define HAL_DBG_INTERRUPT       0x00000400
-#define HAL_DBG_DFS             0x00000800
-#define HAL_DBG_DMA             0x00001000
-#define HAL_DBG_REGULATORY      0x00002000
-#define HAL_DBG_TX              0x00004000
-#define HAL_DBG_TXDESC          0x00008000
-#define HAL_DBG_RX              0x00010000
-#define HAL_DBG_RXDESC          0x00020000
-#define HAL_DBG_ANI             0x00040000
-#define HAL_DBG_BEACON          0x00080000
-#define HAL_DBG_KEYCACHE        0x00100000
-#define HAL_DBG_POWER_MGMT      0x00200000
-#define HAL_DBG_MALLOC		0x00400000
-#define HAL_DBG_POWER_OVERRIDE	0x01000000
-#define HAL_DBG_SPUR_MITIGATE	0x02000000
-#define HAL_DBG_UNMASKABLE      0xFFFFFFFF
-
 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
 
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
-#define OS_REG_RMW(_a, _r, _set, _clr)    \
+#define REG_RMW(_a, _r, _set, _clr)    \
 	REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
-#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
+#define REG_RMW_FIELD(_a, _r, _f, _v) \
 	REG_WRITE(_a, _r, \
 	(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
-#define OS_REG_SET_BIT(_a, _r, _f) \
+#define REG_SET_BIT(_a, _r, _f) \
 	REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
-#define OS_REG_CLR_BIT(_a, _r, _f) \
+#define REG_CLR_BIT(_a, _r, _f) \
 	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
-#define OS_REG_ath9k_regd_is_bit_set(_a, _r, _f) \
-	((REG_READ(_a, _r) & _f) != 0)
 
 #define HAL_COMP_BUF_MAX_SIZE   9216
 #define HAL_COMP_BUF_ALIGN_SIZE 512
@@ -913,7 +878,7 @@ struct ath_hal {
 	u_int32_t ah_magic;
 	u_int16_t ah_devid;
 	u_int16_t ah_subvendorid;
-	void *ah_sc;
+	struct ath_softc *ah_sc;
 	void __iomem *ah_sh;
 	u_int16_t ah_countryCode;
 	u_int32_t ah_macVersion;
@@ -936,25 +901,19 @@ struct ath_hal {
 	u_int16_t ah_currentRD2G;
 	char ah_iso[4];
 	enum start_adhoc_option ah_adHocMode;
-	enum hal_bool ah_commonMode;
+	bool ah_commonMode;
 	struct hal_channel_internal ah_channels[150];
 	u_int ah_nchan;
 	struct hal_channel_internal *ah_curchan;
 	u_int16_t ah_rfsilent;
-	enum hal_bool ah_rfkillEnabled;
-	enum hal_bool ah_isPciExpress;
+	bool ah_rfkillEnabled;
+	bool ah_isPciExpress;
 	u_int16_t ah_txTrigLevel;
 #ifndef ATH_NF_PER_CHAN
 	struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
 #endif
 };
 
-#define HDPRINTF(_ah, _m, _fmt, ...) do {				\
-		if (((_ah) == NULL && _m == HAL_DBG_UNMASKABLE) ||	\
-		    (((struct ath_hal *)(_ah))->ah_config.ath_hal_debug & _m)) \
-			printk(KERN_DEBUG _fmt , ##__VA_ARGS__);	\
-	} while (0)
-
 enum wireless_mode {
 	WIRELESS_MODE_11a = 0,
 	WIRELESS_MODE_11b = 2,
@@ -999,38 +958,39 @@ enum hal_status ath_hal_getcapability(struct ath_hal *ah,
 const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
 						   u_int mode);
 void ath9k_hw_detach(struct ath_hal *ah);
-struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
+struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+				struct ath_softc *sc,
+				void __iomem *mem,
 				enum hal_status *error);
-enum hal_bool ath9k_regd_init_channels(struct ath_hal *ah,
-				       struct hal_channel *chans,
-				       u_int maxchans, u_int *nchans,
-				       u_int8_t *regclassids,
-				       u_int maxregids, u_int *nregids,
-				       u_int16_t cc, u_int32_t modeSelect,
-				       enum hal_bool enableOutdoor,
-				       enum hal_bool
-				       enableExtendedChannels);
+bool ath9k_regd_init_channels(struct ath_hal *ah,
+			      struct hal_channel *chans,
+			      u_int maxchans, u_int *nchans,
+			      u_int8_t *regclassids,
+			      u_int maxregids, u_int *nregids,
+			      u_int16_t cc, u_int32_t modeSelect,
+			      bool enableOutdoor,
+			      bool enableExtendedChannels);
 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
 enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
 				     enum hal_int ints);
-enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
-			     struct hal_channel *chan,
-			     enum hal_ht_macmode macmode,
-			     u_int8_t txchainmask, u_int8_t rxchainmask,
-			     enum hal_ht_extprotspacing extprotspacing,
-			     enum hal_bool bChannelChange,
-			     enum hal_status *status);
-enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah);
+bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
+		    struct hal_channel *chan,
+		    enum hal_ht_macmode macmode,
+		    u_int8_t txchainmask, u_int8_t rxchainmask,
+		    enum hal_ht_extprotspacing extprotspacing,
+		    bool bChannelChange,
+		    enum hal_status *status);
+bool ath9k_hw_phy_disable(struct ath_hal *ah);
 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
-			     enum hal_bool *isCalDone);
+			     bool *isCalDone);
 void ath9k_hw_ani_monitor(struct ath_hal *ah,
 			  const struct hal_node_stats *stats,
 			  struct hal_channel *chan);
-enum hal_bool ath9k_hw_calibrate(struct ath_hal *ah,
-				 struct hal_channel *chan,
-				 u_int8_t rxchainmask,
-				 enum hal_bool longcal,
-				 enum hal_bool *isCalDone);
+bool ath9k_hw_calibrate(struct ath_hal *ah,
+			struct hal_channel *chan,
+			u_int8_t rxchainmask,
+			bool longcal,
+			bool *isCalDone);
 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
 			       struct hal_channel *chan);
 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
@@ -1038,70 +998,65 @@ void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
 			    u_int16_t assocId);
-enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
+bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
 void ath9k_hw_reset_tsf(struct ath_hal *ah);
-enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
-enum hal_bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
-				 const u_int8_t *mac);
-enum hal_bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
-					  u_int16_t entry,
-					  const struct hal_keyval *k,
-					  const u_int8_t *mac,
-					  int xorKey);
-enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
-				     u_int32_t setting);
+bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
+			const u_int8_t *mac);
+bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
+				 u_int16_t entry,
+				 const struct hal_keyval *k,
+				 const u_int8_t *mac,
+				 int xorKey);
+bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
+			    u_int32_t setting);
 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
-enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah);
-enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
-enum hal_bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
-					 enum hal_bool bIncTrigLevel);
+bool ath9k_hw_intrpend(struct ath_hal *ah);
+bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
+bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
+				bool bIncTrigLevel);
 void ath9k_hw_procmibevent(struct ath_hal *ah,
 			   const struct hal_node_stats *stats);
-enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set);
+bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
-enum hal_bool ath9k_hw_setupxtxdesc(struct ath_hal *ah,
-				    struct ath_desc *ds,
-				    u_int txRate1, u_int txTries1,
-				    u_int txRate2, u_int txTries2,
-				    u_int txRate3, u_int txTries3);
-enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah);
-enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
-enum hal_bool ath9k_hw_getcapability(struct ath_hal *ah,
-				     enum hal_capability_type type,
-				     u_int32_t capability,
-				     u_int32_t *result);
-enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
-				     enum hal_capability_type type,
-				     u_int32_t capability,
-				     u_int32_t setting,
-				     enum hal_status *status);
+bool ath9k_hw_phycounters(struct ath_hal *ah);
+bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_getcapability(struct ath_hal *ah,
+			    enum hal_capability_type type,
+			    u_int32_t capability,
+			    u_int32_t *result);
+bool ath9k_hw_setcapability(struct ath_hal *ah,
+			    enum hal_capability_type type,
+			    u_int32_t capability,
+			    u_int32_t setting,
+			    enum hal_status *status);
 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
-enum hal_bool ath9k_hw_setbssidmask(struct ath_hal *ah,
-				    const u_int8_t *mask);
-enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
-				enum hal_power_mode mode);
+bool ath9k_hw_setbssidmask(struct ath_hal *ah,
+			   const u_int8_t *mask);
+bool ath9k_hw_setpower(struct ath_hal *ah,
+		       enum hal_power_mode mode);
 enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
 u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
-enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
-enum hal_bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
-					enum hal_ant_setting settings,
-					struct hal_channel *chan,
-					u_int8_t *tx_chainmask,
-					u_int8_t *rx_chainmask,
-					u_int8_t *antenna_cfgd);
+bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
+bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
+			       enum hal_ant_setting settings,
+			       struct hal_channel *chan,
+			       u_int8_t *tx_chainmask,
+			       u_int8_t *rx_chainmask,
+			       u_int8_t *antenna_cfgd);
 void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
 enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
 					  u_int32_t cfg);
-enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
-				u_int32_t txdp);
-enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
+bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
+		       u_int32_t txdp);
+bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
 u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
 				 const struct hal_rate_table *rates,
 				 u_int32_t frameLen, u_int16_t rateix,
-				 enum hal_bool shortPreamble);
+				 bool shortPreamble);
 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
 				  struct ath_desc *lastds,
 				  u_int durUpdateEn, u_int rtsctsRate,
@@ -1113,25 +1068,25 @@ void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
 				   u_int burstDuration);
 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
-enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
+bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
 u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
 u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
-	struct hal_channel *chan);
+				     struct hal_channel *chan);
 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
-enum hal_bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
-	struct hal_txq_info *qInfo);
-enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
-				       const struct hal_txq_info *qInfo);
+bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
+			      struct hal_txq_info *qInfo);
+bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
+			      const struct hal_txq_info *qInfo);
 struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
-	const struct hal_channel *c);
+					      const struct hal_channel *c);
 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
-	u_int pktLen, enum hal_pkt_type type,
-	u_int txPower, u_int keyIx,
-	enum hal_key_type keyType, u_int flags);
-enum hal_bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
-	u_int segLen, enum hal_bool firstSeg,
-	enum hal_bool lastSeg,
-	const struct ath_desc *ds0);
+			    u_int pktLen, enum hal_pkt_type type,
+			    u_int txPower, u_int keyIx,
+			    enum hal_key_type keyType, u_int flags);
+bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
+			 u_int segLen, bool firstSeg,
+			 bool lastSeg,
+			 const struct ath_desc *ds0);
 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
 					u_int32_t *rxc_pcnt,
 					u_int32_t *rxf_pcnt,
@@ -1141,18 +1096,18 @@ void ath9k_hw_beaconinit(struct ath_hal *ah,
 			 u_int32_t next_beacon, u_int32_t beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
 				    const struct hal_beacon_state *bs);
-enum hal_bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
-				   u_int32_t size, u_int flags);
+bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
+			  u_int32_t size, u_int flags);
 void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
 void ath9k_hw_rxena(struct ath_hal *ah);
 void ath9k_hw_setopmode(struct ath_hal *ah);
-enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
+bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
 			     u_int32_t filter1);
 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
 void ath9k_hw_startpcureceive(struct ath_hal *ah);
 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
-enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
+bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
 enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
 				    struct ath_desc *ds, u_int32_t pa,
 				    struct ath_desc *nds, u_int64_t tsf);
@@ -1164,26 +1119,26 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
 				u_int aggrLen);
 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
-enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
+bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
 				     struct ath_desc *ds, u_int vmf);
-enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
-enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
+bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
+bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
 			  const struct hal_txq_info *qInfo);
 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
 const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
-enum hal_bool ath9k_hw_disable(struct ath_hal *ah);
+bool ath9k_hw_disable(struct ath_hal *ah);
 void ath9k_hw_rfdetach(struct ath_hal *ah);
 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 				  struct hal_channel_internal *chan,
 				  struct chan_centers *centers);
-enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
-				      u_int16_t flags, u_int16_t *low,
-				      u_int16_t *high);
-enum hal_bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
-					     struct hal_channel *chans,
-					     u_int32_t nchans);
+bool ath9k_get_channel_edges(struct ath_hal *ah,
+			     u_int16_t flags, u_int16_t *low,
+			     u_int16_t *high);
+bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
+				    struct hal_channel *chans,
+				    u_int32_t nchans);
 #endif
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c b/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
index 1a23fd164b..596591ec5a 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
@@ -45,7 +45,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
 	}
 
 	if (!ath9k_hw_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to update h/w beacon queue parameters\n",
 			__func__);
 		return 0;
@@ -76,7 +76,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
 	int ctsduration = 0;
 	struct hal_11n_rate_series  series[4];
 
-	DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
+	DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
 		__func__, skb, skb->len);
 
 	/* setup descriptors */
@@ -84,7 +84,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
 
 	flags = HAL_TXDESC_NOACK;
 
-	if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol) {
+	if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
 		ds->ds_link = bf->bf_daddr; /* self-linked */
 		flags |= HAL_TXDESC_VEOL;
 		/* Let hardware handle antenna switching. */
@@ -97,11 +97,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
 		 * SWBA's
 		 * XXX assumes two antenna
 		 */
-		if (sc->sc_stagbeacons)
-			antenna = ((sc->ast_be_xmit /
-					sc->sc_nbcnvaps) & 1 ? 2 : 1);
-		else
-			antenna = (sc->ast_be_xmit & 1 ? 2 : 1);
+		antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1);
 	}
 
 	ds->ds_data = bf->bf_buf_addr;
@@ -128,8 +124,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
 	/* NB: beacon's BufLen must be a multiple of 4 bytes */
 	ath9k_hw_filltxdesc(ah, ds
 			   , roundup(skb->len, 4) /* buffer length */
-			   , AH_TRUE /* first segment */
-			   , AH_TRUE /* last segment */
+			   , true /* first segment */
+			   , true /* last segment */
 			   , ds /* first descriptor */
 		);
 
@@ -219,7 +215,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
 	ASSERT(avp);
 
 	if (avp->av_bcbuf == NULL) {
-		DPRINTF(sc, ATH_DEBUG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
+		DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
 			__func__, avp, avp->av_bcbuf);
 		return NULL;
 	}
@@ -272,9 +268,9 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
 		 * the lock again which is a common function and that
 		 * acquires txq lock inside.
 		 */
-		if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
-			ath_tx_draintxq(sc, cabq, AH_FALSE);
-			DPRINTF(sc, ATH_DEBUG_BEACON,
+		if (sc->sc_nvaps > 1) {
+			ath_tx_draintxq(sc, cabq, false);
+			DPRINTF(sc, ATH_DBG_BEACON,
 				"%s: flush previous cabq traffic\n", __func__);
 		}
 	}
@@ -309,7 +305,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
 	ASSERT(avp);
 
 	if (avp->av_bcbuf == NULL) {
-		DPRINTF(sc, ATH_DEBUG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
+		DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
 			__func__, avp, avp != NULL ? avp->av_bcbuf : NULL);
 		return;
 	}
@@ -322,7 +318,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
 	/* NB: caller is known to have already stopped tx dma */
 	ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
 	ath9k_hw_txstart(ah, sc->sc_bhalq);
-	DPRINTF(sc, ATH_DEBUG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__,
+	DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__,
 		sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc);
 }
 
@@ -377,7 +373,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 				struct ath_buf, list);
 		list_del(&avp->av_bcbuf->list);
 
-		if (sc->sc_opmode == HAL_M_HOSTAP || !sc->sc_hasveol) {
+		if (sc->sc_opmode == HAL_M_HOSTAP ||
+			!sc->sc_ah->ah_caps.halVEOLSupport) {
 			int slot;
 			/*
 			 * Assign the vap to a beacon xmit slot. As
@@ -399,8 +396,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 					avp->av_bslot = slot;
 					/* NB: keep looking for a double slot */
 				}
-			KASSERT(sc->sc_bslot[avp->av_bslot] == ATH_IF_ID_ANY,
-				("beacon slot %u not empty?", avp->av_bslot));
+			BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY);
 			sc->sc_bslot[avp->av_bslot] = if_id;
 			sc->sc_nbcnvaps++;
 		}
@@ -409,14 +405,10 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 	/* release the previous beacon frame , if it already exists. */
 	bf = avp->av_bcbuf;
 	if (bf->bf_mpdu != NULL) {
-		struct ath_xmit_status tx_status;
-
-		skb = (struct sk_buff *) bf->bf_mpdu;
+		skb = (struct sk_buff *)bf->bf_mpdu;
 		ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
 				     get_dma_mem_context(bf, bf_dmacontext));
-		tx_status.flags = 0;
-		tx_status.retries = 0;
-		ath_tx_complete(sc, skb, &tx_status, NULL);
+		dev_kfree_skb_any(skb);
 		bf->bf_mpdu = NULL;
 	}
 
@@ -424,10 +416,12 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 	 * NB: the beacon data buffer must be 32-bit aligned;
 	 * we assume the wbuf routines will return us something
 	 * with this alignment (perhaps should assert).
+	 * FIXME: Fill avp->av_boff.bo_tim,avp->av_btxctl.txpower and
+	 * avp->av_btxctl.shortPreamble
 	 */
-	skb = ath_get_beacon(sc, if_id, &avp->av_boff, &avp->av_btxctl);
+	skb = ieee80211_beacon_get(sc->hw, avp->av_if_data);
 	if (skb == NULL) {
-		DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get skb\n",
+		DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n",
 			__func__);
 		return -ENOMEM;
 	}
@@ -438,8 +432,9 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 	 * of the beacon frame leaves the tstamp field immediately
 	 * following the header.
 	 */
-	if (sc->sc_stagbeacons && avp->av_bslot > 0) {
+	if (avp->av_bslot > 0) {
 		u_int64_t tsfadjust;
+		__le64 val;
 		int intval;
 
 		/* FIXME: Use default value for now: Sujith */
@@ -458,15 +453,15 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 		 * others get a timestamp aligned to the next interval.
 		 */
 		tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF;
-		tsfadjust = cpu_to_le64(tsfadjust<<10);     /* TU->TSF */
+		val = cpu_to_le64(tsfadjust << 10);     /* TU->TSF */
 
-		DPRINTF(sc, ATH_DEBUG_BEACON,
+		DPRINTF(sc, ATH_DBG_BEACON,
 			"%s: %s beacons, bslot %d intval %u tsfadjust %llu\n",
-			__func__, sc->sc_stagbeacons ? "stagger" : "burst",
+			__func__, "stagger",
 			avp->av_bslot, intval, (unsigned long long)tsfadjust);
 
 		wh = (struct ieee80211_hdr *)skb->data;
-		memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
+		memcpy(&wh[1], &val, sizeof(val));
 	}
 
 	bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE,
@@ -495,14 +490,10 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
 
 		bf = avp->av_bcbuf;
 		if (bf->bf_mpdu != NULL) {
-			struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu;
-			struct ath_xmit_status tx_status;
-
+			struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
 			ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
 				get_dma_mem_context(bf, bf_dmacontext));
-			tx_status.flags = 0;
-			tx_status.retries = 0;
-			ath_tx_complete(sc, skb, &tx_status, NULL);
+			dev_kfree_skb_any(skb);
 			bf->bf_mpdu = NULL;
 		}
 		list_add_tail(&bf->list, &sc->sc_bbuf);
@@ -527,13 +518,9 @@ void ath_beacon_free(struct ath_softc *sc)
 	list_for_each_entry(bf, &sc->sc_bbuf, list) {
 		if (bf->bf_mpdu != NULL) {
 			struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu;
-			struct ath_xmit_status tx_status;
-
 			ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
 				get_dma_mem_context(bf, bf_dmacontext));
-			tx_status.flags = 0;
-			tx_status.retries = 0;
-			ath_tx_complete(sc, skb, &tx_status, NULL);
+			dev_kfree_skb_any(skb);
 			bf->bf_mpdu = NULL;
 		}
 	}
@@ -562,6 +549,9 @@ void ath9k_beacon_tasklet(unsigned long data)
 	u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
 	u_int32_t show_cycles = 0;
 	u_int32_t bc = 0; /* beacon count */
+	u_int64_t tsf;
+	u_int32_t tsftu;
+	u_int16_t intval;
 
 	if (sc->sc_noreset) {
 		show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
@@ -586,7 +576,7 @@ void ath9k_beacon_tasklet(unsigned long data)
 		 */
 		if (sc->sc_bmisscount < BSTUCK_THRESH) {
 			if (sc->sc_noreset) {
-				DPRINTF(sc, ATH_DEBUG_BEACON,
+				DPRINTF(sc, ATH_DBG_BEACON,
 					"%s: missed %u consecutive beacons\n",
 					__func__, sc->sc_bmisscount);
 				if (show_cycles) {
@@ -596,19 +586,19 @@ void ath9k_beacon_tasklet(unsigned long data)
 					 * stickiness.
 					 */
 					DPRINTF(sc,
-						ATH_DEBUG_BEACON,
+						ATH_DBG_BEACON,
 						"%s: busy times: rx_clear=%d, "
 						"rx_frame=%d, tx_frame=%d\n",
 						__func__, rx_clear, rx_frame,
 						tx_frame);
 				} else {
 					DPRINTF(sc,
-						ATH_DEBUG_BEACON,
+						ATH_DBG_BEACON,
 						"%s: unable to obtain "
 						"busy times\n", __func__);
 				}
 			} else {
-				DPRINTF(sc, ATH_DEBUG_BEACON,
+				DPRINTF(sc, ATH_DBG_BEACON,
 					"%s: missed %u consecutive beacons\n",
 					__func__, sc->sc_bmisscount);
 			}
@@ -616,13 +606,13 @@ void ath9k_beacon_tasklet(unsigned long data)
 			if (sc->sc_noreset) {
 				if (sc->sc_bmisscount == BSTUCK_THRESH) {
 					DPRINTF(sc,
-						ATH_DEBUG_BEACON,
+						ATH_DBG_BEACON,
 						"%s: beacon is officially "
 						"stuck\n", __func__);
 					ath9k_hw_dmaRegDump(ah);
 				}
 			} else {
-				DPRINTF(sc, ATH_DEBUG_BEACON,
+				DPRINTF(sc, ATH_DBG_BEACON,
 					"%s: beacon is officially stuck\n",
 					__func__);
 				ath_bstuck_process(sc);
@@ -634,11 +624,11 @@ void ath9k_beacon_tasklet(unsigned long data)
 	if (sc->sc_bmisscount != 0) {
 		if (sc->sc_noreset) {
 			DPRINTF(sc,
-				ATH_DEBUG_BEACON,
+				ATH_DBG_BEACON,
 				"%s: resume beacon xmit after %u misses\n",
 				__func__, sc->sc_bmisscount);
 		} else {
-			DPRINTF(sc, ATH_DEBUG_BEACON,
+			DPRINTF(sc, ATH_DBG_BEACON,
 				"%s: resume beacon xmit after %u misses\n",
 				__func__, sc->sc_bmisscount);
 		}
@@ -646,55 +636,29 @@ void ath9k_beacon_tasklet(unsigned long data)
 	}
 
 	/*
-	 * Generate beacon frames.  If we are sending frames
-	 * staggered then calculate the slot for this frame based
+	 * Generate beacon frames. we are sending frames
+	 * staggered so calculate the slot for this frame based
 	 * on the tsf to safeguard against missing an swba.
-	 * Otherwise we are bursting all frames together and need
-	 * to generate a frame for each vap that is up and running.
 	 */
-	if (sc->sc_stagbeacons) {
-		/* staggered beacons */
-		u_int64_t tsf;
-		u_int32_t tsftu;
-		u_int16_t intval;
 
-		/* FIXME: Use default value for now - Sujith */
-		intval = ATH_DEFAULT_BINTVAL;
+	/* FIXME: Use default value for now - Sujith */
+	intval = ATH_DEFAULT_BINTVAL;
 
-		tsf = ath9k_hw_gettsf64(ah);
-		tsftu = TSF_TO_TU(tsf>>32, tsf);
-		slot = ((tsftu % intval) * ATH_BCBUF) / intval;
-		if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
-		DPRINTF(sc, ATH_DEBUG_BEACON,
+	tsf = ath9k_hw_gettsf64(ah);
+	tsftu = TSF_TO_TU(tsf>>32, tsf);
+	slot = ((tsftu % intval) * ATH_BCBUF) / intval;
+	if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
+	DPRINTF(sc, ATH_DBG_BEACON,
 			"%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
 			__func__, slot, (unsigned long long) tsf, tsftu,
 			intval, if_id);
-		bfaddr = 0;
-		if (if_id != ATH_IF_ID_ANY) {
-			bf = ath_beacon_generate(sc, if_id);
-			if (bf != NULL) {
-				bfaddr = bf->bf_daddr;
-				bc = 1;
-			}
+	bfaddr = 0;
+	if (if_id != ATH_IF_ID_ANY) {
+		bf = ath_beacon_generate(sc, if_id);
+		if (bf != NULL) {
+			bfaddr = bf->bf_daddr;
+			bc = 1;
 		}
-	} else {
-		/* XXX: Clean this up, move work to a helper */
-		/* burst'd beacons */
-		u_int32_t *bflink;
-		bflink = &bfaddr;
-		/* XXX rotate/randomize order? */
-		for (slot = 0; slot < ATH_BCBUF; slot++) {
-			if_id = sc->sc_bslot[slot];
-			if (if_id != ATH_IF_ID_ANY) {
-				bf = ath_beacon_generate(sc, if_id);
-				if (bf != NULL) {
-					*bflink = bf->bf_daddr;
-					bflink = &bf->bf_desc->ds_link;
-					bc++;
-				}
-			}
-		}
-		*bflink = 0;    /* link of last frame */
 	}
 	/*
 	 * Handle slot time change when a non-ERP station joins/leaves
@@ -719,27 +683,6 @@ void ath9k_beacon_tasklet(unsigned long data)
 	} else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
 		ath_setslottime(sc);        /* commit change to hardware */
 
-	if ((!sc->sc_stagbeacons || slot == 0) && (!sc->sc_diversity)) {
-		int otherant;
-		/*
-		 * Check recent per-antenna transmit statistics and flip
-		 * the default rx antenna if noticeably more frames went out
-		 * on the non-default antenna.  Only do this if rx diversity
-		 * is off.
-		 * XXX assumes 2 anntenae
-		 */
-		otherant = sc->sc_defant & 1 ? 2 : 1;
-		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] +
-			ATH_ANTENNA_DIFF) {
-			DPRINTF(sc, ATH_DEBUG_BEACON,
-				"%s: flip defant to %u, %u > %u\n",
-				__func__, otherant, sc->sc_ant_tx[otherant],
-				sc->sc_ant_tx[sc->sc_defant]);
-			ath_setdefantenna(sc, otherant);
-		}
-		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
-	}
-
 	if (bfaddr != 0) {
 		/*
 		 * Stop any current dma and put the new frame(s) on the queue.
@@ -747,7 +690,7 @@ void ath9k_beacon_tasklet(unsigned long data)
 		 * are still pending on the queue.
 		 */
 		if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: beacon queue %u did not stop?\n",
 				__func__, sc->sc_bhalq);
 			/* NB: the HAL still stops DMA, so proceed */
@@ -771,7 +714,7 @@ void ath9k_beacon_tasklet(unsigned long data)
 
 void ath_bstuck_process(struct ath_softc *sc)
 {
-	DPRINTF(sc, ATH_DEBUG_BEACON,
+	DPRINTF(sc, ATH_DBG_BEACON,
 		"%s: stuck beacon; resetting (bmiss count %u)\n",
 		__func__, sc->sc_bmisscount);
 	ath_internal_reset(sc);
@@ -834,11 +777,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		 */
 		/* NB: the beacon interval is kept internally in TU's */
 		intval = conf.beacon_interval & HAL_BEACON_PERIOD;
-		if (sc->sc_stagbeacons)
-			intval /= ATH_BCBUF;    /* for staggered beacons */
-		if ((sc->sc_nostabeacons) &&
-		    (av_opmode == HAL_M_HOSTAP))
-			nexttbtt = 0;
+		intval /= ATH_BCBUF;    /* for staggered beacons */
 	} else {
 		intval = conf.beacon_interval & HAL_BEACON_PERIOD;
 	}
@@ -847,13 +786,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		nexttbtt = intval;
 	else if (intval)        /* NB: can be 0 for monitor mode */
 		nexttbtt = roundup(nexttbtt, intval);
-	DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
+	DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
 		__func__, nexttbtt, intval, conf.beacon_interval);
 	/* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
-	if ((sc->sc_opmode == HAL_M_STA) ||
-	     ((sc->sc_opmode == HAL_M_HOSTAP) &&
-	      (av_opmode == HAL_M_STA) &&
-	      (sc->sc_nostabeacons))) {
+	if (sc->sc_opmode == HAL_M_STA) {
 		struct hal_beacon_state bs;
 		u_int64_t tsf;
 		u_int32_t tsftu;
@@ -936,7 +872,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		if (bs.bs_sleepduration > bs.bs_dtimperiod)
 			bs.bs_sleepduration = bs.bs_dtimperiod;
 
-		DPRINTF(sc, ATH_DEBUG_BEACON,
+		DPRINTF(sc, ATH_DBG_BEACON,
 			"%s: tsf %llu "
 			"tsf:tu %u "
 			"intval %u "
@@ -963,12 +899,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 			, bs.bs_timoffset
 			);
 
-		if (!(sc->sc_nostabeacons)) {
-			ath9k_hw_set_interrupts(ah, 0);
-			ath9k_hw_set_sta_beacon_timers(ah, &bs);
-			sc->sc_imask |= HAL_INT_BMISS;
-			ath9k_hw_set_interrupts(ah, sc->sc_imask);
-		}
+		ath9k_hw_set_interrupts(ah, 0);
+		ath9k_hw_set_sta_beacon_timers(ah, &bs);
+		sc->sc_imask |= HAL_INT_BMISS;
+		ath9k_hw_set_interrupts(ah, sc->sc_imask);
 	} else {
 		u_int64_t tsf;
 		u_int32_t tsftu;
@@ -990,7 +924,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 				} while (nexttbtt < tsftu);
 			}
 #undef FUDGE
-			DPRINTF(sc, ATH_DEBUG_BEACON,
+			DPRINTF(sc, ATH_DBG_BEACON,
 				"%s: IBSS nexttbtt %u intval %u (%u)\n",
 				__func__, nexttbtt,
 				intval & ~HAL_BEACON_RESET_TSF,
@@ -1004,7 +938,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 			 * deal with things.
 			 */
 			intval |= HAL_BEACON_ENA;
-			if (!sc->sc_hasveol)
+			if (!ah->ah_caps.halVEOLSupport)
 				sc->sc_imask |= HAL_INT_SWBA;
 			ath_beaconq_config(sc);
 		} else if (sc->sc_opmode == HAL_M_HOSTAP) {
@@ -1023,7 +957,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		 * When using a self-linked beacon descriptor in
 		 * ibss mode load it once here.
 		 */
-		if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol)
+		if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
 			ath_beacon_start_adhoc(sc, 0);
 	}
 #undef TSF_TO_TU
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/core.c b/package/ath9k/src/drivers/net/wireless/ath9k/core.c
index a0810acc7d..587f307b8b 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/core.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/core.c
@@ -19,7 +19,7 @@
 #include "core.h"
 #include "regd.h"
 
-static int ath_outdoor = AH_FALSE;		/* enable outdoor use */
+static int ath_outdoor;		/* enable outdoor use */
 
 static const u_int8_t ath_bcast_mac[ETH_ALEN] =
     { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@@ -65,7 +65,7 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
 
 	memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 	rt = sc->sc_rates[mode];
-	KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
+	BUG_ON(!rt);
 
 	for (i = 0; i < rt->rateCount; i++)
 		sc->sc_rixmap[rt->info[i].rateCode] = (u_int8_t) i;
@@ -152,7 +152,7 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
 				ATH9K_MODE_SEL_11NG_HT40MINUS);
 		break;
 	default:
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid mode %u\n",
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid mode %u\n",
 			__func__, mode);
 		return 0;
 	}
@@ -176,8 +176,8 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
 
 static int ath_getchannels(struct ath_softc *sc,
 			   u_int cc,
-			   enum hal_bool outDoor,
-			   enum hal_bool xchanMode)
+			   bool outDoor,
+			   bool xchanMode)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	struct hal_channel *chans;
@@ -187,7 +187,7 @@ static int ath_getchannels(struct ath_softc *sc,
 
 	chans = kmalloc(ATH_CHAN_MAX * sizeof(struct hal_channel), GFP_KERNEL);
 	if (chans == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to allocate channel table\n", __func__);
 		return -ENOMEM;
 	}
@@ -205,7 +205,7 @@ static int ath_getchannels(struct ath_softc *sc,
 				      xchanMode)) {
 		u_int32_t rd = ah->ah_currentRD;
 
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to collect channel list from hal; "
 			"regdomain likely %u country code %u\n",
 			__func__, rd, cc);
@@ -290,7 +290,7 @@ static int ath_stop(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: invalid %u\n",
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n",
 		__func__, sc->sc_invalid);
 
 	/*
@@ -311,7 +311,7 @@ static int ath_stop(struct ath_softc *sc)
 
 	if (!sc->sc_invalid)
 		ath9k_hw_set_interrupts(ah, 0);
-	ath_draintxq(sc, AH_FALSE);
+	ath_draintxq(sc, false);
 	if (!sc->sc_invalid) {
 		ath_stoprecv(sc);
 		ath9k_hw_phy_disable(ah);
@@ -342,7 +342,7 @@ void ath_scan_start(struct ath_softc *sc)
 
 	/* Restore previous power management state. */
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
+	DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
 		now / 1000, now % 1000, __func__, rfilt);
 }
 
@@ -361,11 +361,13 @@ void ath_scan_end(struct ath_softc *sc)
 	u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
 
 	sc->sc_scanning = 0;
+	/* Request for a full reset due to rx packet filter changes */
+	sc->sc_full_reset = 1;
 	rfilt = ath_calcrxfilter(sc);
 	ath9k_hw_setrxfilter(ah, rfilt);
 	ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
+	DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
 		now / 1000, now % 1000, __func__, rfilt, sc->sc_curaid);
 }
 
@@ -379,13 +381,13 @@ void ath_scan_end(struct ath_softc *sc)
 int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	enum hal_bool fastcc = AH_TRUE, stopped;
+	bool fastcc = true, stopped;
 	enum hal_ht_macmode ht_macmode;
 
 	if (sc->sc_invalid)	/* if the device is invalid or removed */
 		return -EIO;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG,
+	DPRINTF(sc, ATH_DBG_CONFIG,
 		"%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
 		__func__,
 		ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel,
@@ -410,7 +412,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 		 * the relevant bits of the h/w.
 		 */
 		ath9k_hw_set_interrupts(ah, 0);	/* disable interrupts */
-		ath_draintxq(sc, AH_FALSE);	/* clear pending tx frames */
+		ath_draintxq(sc, false);	/* clear pending tx frames */
 		stopped = ath_stoprecv(sc);	/* turn off frame recv */
 
 		/* XXX: do not flush receive queue here. We don't want
@@ -418,7 +420,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 		 * changing channel. */
 
 		if (!stopped || sc->sc_full_reset)
-			fastcc = AH_FALSE;
+			fastcc = false;
 
 		spin_lock_bh(&sc->sc_resetlock);
 		if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,
@@ -426,7 +428,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 					sc->sc_rx_chainmask,
 					sc->sc_ht_extprotspacing,
 					fastcc, &status)) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: unable to reset channel %u (%uMhz) "
 				"flags 0x%x hal status %u\n", __func__,
 				ath9k_hw_mhz2ieee(ah, hchan->channel,
@@ -443,7 +445,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 
 		/* Re-enable rx framework */
 		if (ath_startrecv(sc) != 0) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: unable to restart recv logic\n", __func__);
 			return -EIO;
 		}
@@ -507,10 +509,10 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
 	 * sc_chainmask_auto_sel is used for internal global auto-switching
 	 * enabled/disabled setting
 	 */
-	if ((sc->sc_no_tx_3_chains == AH_FALSE) ||
-	    (sc->sc_config.chainmask_sel == AH_FALSE))
+	if (sc->sc_ah->ah_caps.halTxChainMask != ATH_CHAINMASK_SEL_3X3) {
 		cm->cur_tx_mask = sc->sc_tx_chainmask;
 		return cm->cur_tx_mask;
+	}
 
 	if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
 		return cm->cur_tx_mask;
@@ -541,56 +543,31 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
 	return cm->cur_tx_mask;
 }
 
-/******************/
-/* VAP management */
-/******************/
-
 /*
- *  Down VAP instance
- *
- *  This routine will stop the indicated VAP and put it in a "down" state.
- *  The down state is basically an initialization state that can be brought
- *  back up by calling the opposite up routine.
- *  This routine will bring the interface out of power save mode, set the
- *  LED states, update the rate control processing, stop DMA transfers, and
- *  set the VAP into the down state.
-*/
+ * Update tx/rx chainmask. For legacy association,
+ * hard code chainmask to 1x1, for 11n association, use
+ * the chainmask configuration.
+ */
 
-int ath_vap_down(struct ath_softc *sc, int if_id, u_int flags)
+void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 {
-	struct ath_hal *ah = sc->sc_ah;
-	struct ath_vap *avp;
-
-	avp = sc->sc_vaps[if_id];
-	if (avp == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
-			__func__, if_id);
-		return -EINVAL;
-	}
-
-#ifdef CONFIG_SLOW_ANT_DIV
-	if (sc->sc_slowAntDiv)
-		ath_slow_ant_div_stop(&sc->sc_antdiv);
-#endif
-
-	/* update ratectrl about the new state */
-	ath_rate_newstate(sc, avp, 0);
-
-	/* Reclaim beacon resources */
-	if (sc->sc_opmode == HAL_M_HOSTAP || sc->sc_opmode == HAL_M_IBSS) {
-		ath9k_hw_stoptxdma(ah, sc->sc_bhalq);
-		ath_beacon_return(sc, avp);
-	}
-
-	if (flags & ATH_IF_HW_OFF) {
-		sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
-		ath9k_hw_set_interrupts(ah, sc->sc_imask & ~HAL_INT_GLOBAL);
-		sc->sc_beacons = 0;
+	sc->sc_update_chainmask = 1;
+	if (is_ht) {
+		sc->sc_tx_chainmask = sc->sc_ah->ah_caps.halTxChainMask;
+		sc->sc_rx_chainmask = sc->sc_ah->ah_caps.halRxChainMask;
+	} else {
+		sc->sc_tx_chainmask = 1;
+		sc->sc_rx_chainmask = 1;
 	}
 
-	return 0;
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
+		__func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 }
 
+/******************/
+/* VAP management */
+/******************/
+
 /*
  *  VAP in Listen mode
  *
@@ -608,14 +585,13 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 
 	avp = sc->sc_vaps[if_id];
 	if (avp == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
 			__func__, if_id);
 		return -EINVAL;
 	}
 
 #ifdef CONFIG_SLOW_ANT_DIV
-	if (sc->sc_slowAntDiv)
-		ath_slow_ant_div_stop(&sc->sc_antdiv);
+	ath_slow_ant_div_stop(&sc->sc_antdiv);
 #endif
 
 	/* update ratectrl about the new state */
@@ -630,7 +606,7 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 	} else
 		sc->sc_curaid = 0;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG,
+	DPRINTF(sc, ATH_DBG_CONFIG,
 		"%s: RX filter 0x%x bssid %s aid 0x%x\n",
 		__func__, rfilt, print_mac(mac,
 			sc->sc_curbssid), sc->sc_curaid);
@@ -648,210 +624,25 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 	return 0;
 }
 
-int ath_vap_join(struct ath_softc *sc, int if_id,
-		 const u_int8_t bssid[ETH_ALEN], u_int flags)
-{
-	struct ath_hal *ah = sc->sc_ah;
-	struct ath_vap *avp;
-	u_int32_t rfilt = 0;
-	DECLARE_MAC_BUF(mac);
-
-	avp = sc->sc_vaps[if_id];
-	if (avp == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
-			__func__, if_id);
-		return -EINVAL;
-	}
-
-	/* update ratectrl about the new state */
-	ath_rate_newstate(sc, avp, 0);
-
-	rfilt = ath_calcrxfilter(sc);
-	ath9k_hw_setrxfilter(ah, rfilt);
-
-	memcpy(sc->sc_curbssid, bssid, ETH_ALEN);
-	sc->sc_curaid = 0;
-	ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
-
-	DPRINTF(sc, ATH_DEBUG_CONFIG,
-		"%s: RX filter 0x%x bssid %s aid 0x%x\n",
-		__func__, rfilt,
-		print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
-
-	/*
-	 * Update tx/rx chainmask. For legacy association,
-	 * hard code chainmask to 1x1, for 11n association, use
-	 * the chainmask configuration.
-	 */
-	sc->sc_update_chainmask = 1;
-	if (flags & ATH_IF_HT) {
-		sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
-		sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
-	} else {
-		sc->sc_tx_chainmask = 1;
-		sc->sc_rx_chainmask = 1;
-	}
-
-	/* Enable rx chain mask detection if configured to do so */
-
-	sc->sc_rx_chainmask_detect = 0;
-
-	/* Set aggregation protection mode parameters */
-
-	sc->sc_config.ath_aggr_prot = 0;
-
-	/*
-	 * Reset our TSF so that its value is lower than the beacon that we are
-	 * trying to catch. Only then hw will update its TSF register with the
-	 * new beacon. Reset the TSF before setting the BSSID to avoid allowing
-	 * in any frames that would update our TSF only to have us clear it
-	 * immediately thereafter.
-	 */
-	ath9k_hw_reset_tsf(ah);
-
-	/*
-	 * XXXX
-	 * Disable BMISS interrupt when we're not associated
-	 */
-	ath9k_hw_set_interrupts(ah,
-		sc->sc_imask & ~(HAL_INT_SWBA | HAL_INT_BMISS));
-	sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
-	/* need to reconfigure the beacons when it moves to RUN */
-	sc->sc_beacons = 0;
-
-	return 0;
-}
-
-int ath_vap_up(struct ath_softc *sc,
-	       int if_id,
-	       const u_int8_t bssid[ETH_ALEN],
-	       u_int8_t aid, u_int flags)
-{
-	struct ath_hal *ah = sc->sc_ah;
-	struct ath_vap *avp;
-	u_int32_t rfilt = 0;
-	int i, error = 0;
-	DECLARE_MAC_BUF(mac);
-
-	ASSERT(if_id != ATH_IF_ID_ANY);
-	avp = sc->sc_vaps[if_id];
-	if (avp == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
-			__func__, if_id);
-		return -EINVAL;
-	}
-
-	/* update ratectrl about the new state */
-	ath_rate_newstate(sc, avp, 1);
-
-	rfilt = ath_calcrxfilter(sc);
-	ath9k_hw_setrxfilter(ah, rfilt);
-
-	if (avp->av_opmode == HAL_M_STA || avp->av_opmode == HAL_M_IBSS) {
-		memcpy(sc->sc_curbssid, bssid, ETH_ALEN);
-		sc->sc_curaid = aid;
-		ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
-	}
-
-	DPRINTF(sc, ATH_DEBUG_CONFIG,
-		"%s: RX filter 0x%x bssid %s aid 0x%x\n",
-		__func__, rfilt,
-		print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
-
-	if ((avp->av_opmode != IEEE80211_IF_TYPE_STA) &&
-		(flags & ATH_IF_PRIVACY)) {
-		for (i = 0; i < IEEE80211_WEP_NKID; i++)
-			if (ath9k_hw_keyisvalid(ah, (u_int16_t) i))
-				ath9k_hw_keysetmac(ah, (u_int16_t) i, bssid);
-	}
-
-	switch (avp->av_opmode) {
-	case HAL_M_HOSTAP:
-	case HAL_M_IBSS:
-		/*
-		 * Allocate and setup the beacon frame.
-		 *
-		 * Stop any previous beacon DMA.  This may be
-		 * necessary, for example, when an ibss merge
-		 * causes reconfiguration; there will be a state
-		 * transition from RUN->RUN that means we may
-		 * be called with beacon transmission active.
-		 */
-		ath9k_hw_stoptxdma(ah, sc->sc_bhalq);
-
-		error = ath_beacon_alloc(sc, if_id);
-		if (error != 0)
-			goto bad;
-
-		if (flags & ATH_IF_BEACON_ENABLE)
-			sc->sc_beacons = 0;
-
-		break;
-	case HAL_M_STA:
-		/*
-		 * start rx chain mask detection if it is enabled.
-		 * Use the default chainmask as starting point.
-		 */
-		if (sc->sc_rx_chainmask_detect) {
-			if (flags & ATH_IF_HT)
-				sc->sc_rx_chainmask =
-					ah->ah_caps.halRxChainMask;
-			else
-				sc->sc_rx_chainmask = 1;
-
-			sc->sc_rx_chainmask_start = 1;
-		}
-		break;
-	default:
-		break;
-	}
-	/* Moved beacon_config after dfs_wait check
-	 * so that ath_beacon_config won't be called duing dfswait
-	 * period - this will fix the beacon stuck afer DFS
-	 * CAC period issue
-	 * Configure the beacon and sleep timers. */
-
-	if (!sc->sc_beacons && !(flags & ATH_IF_BEACON_SYNC)) {
-		ath_beacon_config(sc, if_id);
-		sc->sc_beacons = 1;
-	}
-
-	/* Reset rssi stats; maybe not the best place... */
-	if (flags & ATH_IF_HW_ON) {
-		sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
-		sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
-		sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
-		sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
-	}
-bad:
-	return error;
-}
-
 int ath_vap_attach(struct ath_softc *sc,
 		   int if_id,
 		   struct ieee80211_vif *if_data,
-		   enum hal_opmode opmode,
-		   enum hal_opmode iv_opmode,
-		   int nostabeacons)
+		   enum hal_opmode opmode)
 {
 	struct ath_vap *avp;
 
 	if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Invalid interface id = %u\n", __func__, if_id);
 		return -EINVAL;
 	}
 
 	switch (opmode) {
 	case HAL_M_STA:
-		sc->sc_nostabeacons = nostabeacons;
-		break;
 	case HAL_M_IBSS:
 	case HAL_M_MONITOR:
 		break;
 	case HAL_M_HOSTAP:
-		/* copy nostabeacons - for WDS client */
-		sc->sc_nostabeacons = nostabeacons;
 		/* XXX not right, beacon buffer is allocated on RUN trans */
 		if (list_empty(&sc->sc_bbuf))
 			return -ENOMEM;
@@ -868,24 +659,13 @@ int ath_vap_attach(struct ath_softc *sc,
 	memzero(avp, sizeof(struct ath_vap));
 	avp->av_if_data = if_data;
 	/* Set the VAP opmode */
-	avp->av_opmode = iv_opmode;
+	avp->av_opmode = opmode;
 	avp->av_bslot = -1;
 	INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
 	INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
 	spin_lock_init(&avp->av_mcastq.axq_lock);
-	if (opmode == HAL_M_HOSTAP || opmode == HAL_M_IBSS) {
-		if (sc->sc_hastsfadd) {
-			/*
-			 * Multiple vaps are to transmit beacons and we
-			 * have h/w support for TSF adjusting; enable use
-			 * of staggered beacons.
-			 */
-			/* XXX check for beacon interval too small */
-			sc->sc_stagbeacons = 1;
-		}
-	}
-	if (sc->sc_hastsfadd)
-		ath9k_hw_set_tsfadjust(sc->sc_ah, sc->sc_stagbeacons);
+
+	ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
 
 	sc->sc_vaps[if_id] = avp;
 	sc->sc_nvaps++;
@@ -906,7 +686,7 @@ int ath_vap_detach(struct ath_softc *sc, int if_id)
 
 	avp = sc->sc_vaps[if_id];
 	if (avp == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
 			__func__, if_id);
 		return -EINVAL;
 	}
@@ -919,32 +699,17 @@ int ath_vap_detach(struct ath_softc *sc, int if_id)
 	 * XXX can we do this w/o affecting other vap's?
 	 */
 	ath9k_hw_set_interrupts(ah, 0);	/* disable interrupts */
-	ath_draintxq(sc, AH_FALSE);	/* stop xmit side */
+	ath_draintxq(sc, false);	/* stop xmit side */
 	ath_stoprecv(sc);	/* stop recv side */
 	ath_flushrecv(sc);	/* flush recv queue */
 
 	/* Reclaim any pending mcast bufs on the vap. */
-	ath_tx_draintxq(sc, &avp->av_mcastq, AH_FALSE);
-
-	if (sc->sc_opmode == HAL_M_HOSTAP && sc->sc_nostabeacons)
-		sc->sc_nostabeacons = 0;
+	ath_tx_draintxq(sc, &avp->av_mcastq, false);
 
 	kfree(avp);
 	sc->sc_vaps[if_id] = NULL;
 	sc->sc_nvaps--;
 
-	/* restart H/W in case there are other VAPs */
-	if (sc->sc_nvaps) {
-		/* Restart rx+tx machines if device is still running. */
-		if (ath_startrecv(sc) != 0)	/* restart recv */
-			DPRINTF(sc, ATH_DEBUG_FATAL,
-				"%s: unable to start recv logic\n", __func__);
-		if (sc->sc_beacons)
-			/* restart beacons */
-			ath_beacon_config(sc, ATH_IF_ID_ANY);
-
-		ath9k_hw_set_interrupts(ah, sc->sc_imask);
-	}
 	return 0;
 }
 
@@ -954,7 +719,7 @@ int ath_vap_config(struct ath_softc *sc,
 	struct ath_vap *avp;
 
 	if (if_id >= ATH_BCBUF) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Invalid interface id = %u\n", __func__, if_id);
 		return -EINVAL;
 	}
@@ -979,7 +744,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
 	int error = 0;
 	enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
 
 	/*
 	 * Stop anything previously setup.  This is safe
@@ -1006,8 +771,8 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
 	spin_lock_bh(&sc->sc_resetlock);
 	if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
 			   sc->sc_tx_chainmask, sc->sc_rx_chainmask,
-			   sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+			   sc->sc_ht_extprotspacing, false, &status)) {
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to reset hardware; hal status %u "
 			"(freq %u flags 0x%x)\n", __func__, status,
 			sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
@@ -1030,7 +795,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
 	 * here except setup the interrupt mask.
 	 */
 	if (ath_startrecv(sc) != 0) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to start recv logic\n", __func__);
 		error = -EIO;
 		goto done;
@@ -1043,14 +808,14 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
 	if (ah->ah_caps.halGTTSupport)
 		sc->sc_imask |= HAL_INT_GTT;
 
-	if (sc->sc_hashtsupport)
+	if (ah->ah_caps.halHTSupport)
 		sc->sc_imask |= HAL_INT_CST;
 
 	/*
 	 * Enable MIB interrupts when there are hardware phy counters.
 	 * Note we only do this (at the moment) for station mode.
 	 */
-	if (sc->sc_needmib &&
+	if (ath9k_hw_phycounters(ah) &&
 	    ((sc->sc_opmode == HAL_M_STA) || (sc->sc_opmode == HAL_M_IBSS)))
 		sc->sc_imask |= HAL_INT_MIB;
 	/*
@@ -1101,7 +866,7 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
 	struct ath_hal *ah = sc->sc_ah;
 
 	if (ath_startrecv(sc) != 0)	/* restart recv */
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to start recv logic\n", __func__);
 
 	/*
@@ -1143,8 +908,8 @@ int ath_reset(struct ath_softc *sc)
 	if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
 			   ht_macmode,
 			   sc->sc_tx_chainmask, sc->sc_rx_chainmask,
-			   sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+			   sc->sc_ht_extprotspacing, false, &status)) {
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to reset hardware; hal status %u\n",
 			__func__, status);
 		error = -EIO;
@@ -1180,11 +945,12 @@ int ath_suspend(struct ath_softc *sc)
 /* Interrupt handler.  Most of the actual processing is deferred.
  * It's the caller's responsibility to ensure the chip is awake. */
 
-int ath_intr(struct ath_softc *sc)
+irqreturn_t ath_isr(int irq, void *dev)
 {
+	struct ath_softc *sc = dev;
 	struct ath_hal *ah = sc->sc_ah;
 	enum hal_int status;
-	int sched = ATH_ISR_NOSCHED;
+	bool sched = false;
 
 	do {
 		if (sc->sc_invalid) {
@@ -1193,10 +959,10 @@ int ath_intr(struct ath_softc *sc)
 			 * touch anything. Note this can happen early
 			 * on if the IRQ is shared.
 			 */
-			return ATH_ISR_NOTMINE;
+			return IRQ_NONE;
 		}
 		if (!ath9k_hw_intrpend(ah)) {	/* shared irq, not for us */
-			return ATH_ISR_NOTMINE;
+			return IRQ_NONE;
 		}
 
 		/*
@@ -1215,16 +981,16 @@ int ath_intr(struct ath_softc *sc)
 		 */
 
 		if (!status)
-			return ATH_ISR_NOTMINE;
+			return IRQ_NONE;
 
 		sc->sc_intrstatus = status;
 
 		if (status & HAL_INT_FATAL) {
 			/* need a chip reset */
-			sched = ATH_ISR_SCHED;
+			sched = true;
 		} else if (status & HAL_INT_RXORN) {
 			/* need a chip reset */
-			sched = ATH_ISR_SCHED;
+			sched = true;
 		} else {
 			if (status & HAL_INT_SWBA) {
 				/* schedule a tasklet for beacon handling */
@@ -1236,22 +1002,22 @@ int ath_intr(struct ath_softc *sc)
 				 *     RXE bit is written, but it doesn't work
 				 *     at least on older hardware revs.
 				 */
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			}
 
 			if (status & HAL_INT_TXURN)
 				/* bump tx trigger level */
-				ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
+				ath9k_hw_updatetxtriglevel(ah, true);
 			/* XXX: optimize this */
 			if (status & HAL_INT_RX)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			if (status & HAL_INT_TX)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			if (status & HAL_INT_BMISS)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			/* carrier sense timeout */
 			if (status & HAL_INT_CST)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			if (status & HAL_INT_MIB) {
 				/*
 				 * Disable interrupts until we service the MIB
@@ -1268,26 +1034,23 @@ int ath_intr(struct ath_softc *sc)
 				ath9k_hw_set_interrupts(ah, sc->sc_imask);
 			}
 			if (status & HAL_INT_TIM_TIMER) {
-				if (!sc->sc_hasautosleep) {
+				if (!ah->ah_caps.halAutoSleepSupport) {
 					/* Clear RxAbort bit so that we can
 					 * receive frames */
 					ath9k_hw_setrxabort(ah, 0);
-					/* Set flag indicating we're waiting
-					 * for a beacon */
-					sc->sc_waitbeacon = 1;
-
-					sched = ATH_ISR_SCHED;
+					sched = true;
 				}
 			}
 		}
 	} while (0);
 
-	if (sched == ATH_ISR_SCHED)
+	if (sched) {
 		/* turn off every interrupt except SWBA */
 		ath9k_hw_set_interrupts(ah, (sc->sc_imask & HAL_INT_SWBA));
+		tasklet_schedule(&sc->intr_tq);
+	}
 
-	return sched;
-
+	return IRQ_HANDLED;
 }
 
 /* Deferred interrupt processing  */
@@ -1335,11 +1098,6 @@ static void ath9k_tasklet(unsigned long data)
 	ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 }
 
-void ath_set_macmode(struct ath_softc *sc, enum hal_ht_macmode macmode)
-{
-	ath9k_hw_set11nmac2040(sc->sc_ah, macmode);
-}
-
 int ath_init(u_int16_t devid, struct ath_softc *sc)
 {
 	struct ath_hal *ah = NULL;
@@ -1352,7 +1110,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	sc->sc_invalid = 1;
 
 	sc->sc_debug = DBG_DEFAULT;
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
 
 	/* Initialize tasklet */
 	tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
@@ -1371,7 +1129,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 
 	ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
 	if (ah == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to attach hardware; HAL status %u\n",
 			__func__, status);
 		error = -ENXIO;
@@ -1382,29 +1140,10 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	/* Get the chipset-specific aggr limit. */
 	sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit;
 
-	/*
-	 * Check if the MAC has multi-rate retry support.
-	 * We do this by trying to setup a fake extended
-	 * descriptor.  MAC's that don't have support will
-	 * return false w/o doing anything.  MAC's that do
-	 * support it will return true w/o doing anything.
-	 *
-	 *  XXX This is lame.  Just query a hal property, Luke!
-	 */
-	sc->sc_mrretry = ath9k_hw_setupxtxdesc(ah, NULL, 0, 0, 0, 0, 0, 0);
-
-	/*
-	 * Check if the device has hardware counters for PHY
-	 * errors.  If so we need to enable the MIB interrupt
-	 * so we can act on stat triggers.
-	 */
-	if (ath9k_hw_phycounters(ah))
-		sc->sc_needmib = 1;
-
 	/* Get the hardware key cache size. */
 	sc->sc_keymax = ah->ah_caps.halKeyCacheSize;
 	if (sc->sc_keymax > ATH_KEYMAX) {
-		DPRINTF(sc, ATH_DEBUG_KEYCACHE,
+		DPRINTF(sc, ATH_DBG_KEYCACHE,
 			"%s: Warning, using only %u entries in %u key cache\n",
 			__func__, ATH_KEYMAX, sc->sc_keymax);
 		sc->sc_keymax = ATH_KEYMAX;
@@ -1463,14 +1202,14 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	 */
 	sc->sc_bhalq = ath_beaconq_setup(ah);
 	if (sc->sc_bhalq == -1) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup a beacon xmit queue\n", __func__);
 		error = -EIO;
 		goto bad2;
 	}
 	sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
 	if (sc->sc_cabq == NULL) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup CAB xmit queue\n", __func__);
 		error = -EIO;
 		goto bad2;
@@ -1485,7 +1224,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	/* Setup data queues */
 	/* NB: ensure BK queue is the lowest priority h/w queue */
 	if (!ath_tx_setup(sc, HAL_WME_AC_BK)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for BK traffic\n",
 			__func__);
 		error = -EIO;
@@ -1493,30 +1232,27 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	}
 
 	if (!ath_tx_setup(sc, HAL_WME_AC_BE)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for BE traffic\n",
 			__func__);
 		error = -EIO;
 		goto bad2;
 	}
 	if (!ath_tx_setup(sc, HAL_WME_AC_VI)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for VI traffic\n",
 			__func__);
 		error = -EIO;
 		goto bad2;
 	}
 	if (!ath_tx_setup(sc, HAL_WME_AC_VO)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to setup xmit queue for VO traffic\n",
 			__func__);
 		error = -EIO;
 		goto bad2;
 	}
 
-	if (ah->ah_caps.halHTSupport)
-		sc->sc_hashtsupport = 1;
-
 	sc->sc_rc = ath_rate_attach(ah);
 	if (sc->sc_rc == NULL) {
 		error = EIO;
@@ -1532,8 +1268,6 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 		 */
 		ath9k_hw_setcapability(sc->sc_ah, HAL_CAP_TKIP_MIC, 0, 1, NULL);
 	}
-	sc->sc_hasclrkey = ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
-						  HAL_CIPHER_CLR, NULL);
 
 	/*
 	 * Check whether the separate key cache entries
@@ -1556,26 +1290,11 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	sc->sc_config.txpowlimit_override = 0;
 
 	/* 11n Capabilities */
-	if (sc->sc_hashtsupport) {
+	if (ah->ah_caps.halHTSupport) {
 		sc->sc_txaggr = 1;
 		sc->sc_rxaggr = 1;
 	}
 
-	/* Check for misc other capabilities. */
-	sc->sc_hasbmask = ah->ah_caps.halBssIdMaskSupport ? 1 : 0;
-	sc->sc_hastsfadd =
-		ath9k_hw_getcapability(ah, HAL_CAP_TSF_ADJUST, 0, NULL);
-
-	/*
-	 * If we cannot transmit on three chains, prevent chain mask
-	 * selection logic from switching between 2x2 and 3x3 chain
-	 * masks based on RSSI.
-	 */
-	sc->sc_no_tx_3_chains =
-	    (ah->ah_caps.halTxChainMask == ATH_CHAINMASK_SEL_3X3) ?
-		AH_TRUE : AH_FALSE;
-	sc->sc_config.chainmask_sel = sc->sc_no_tx_3_chains;
-
 	sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
 	sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
 
@@ -1586,37 +1305,15 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	sc->sc_rxchaindetect_delta5GHz = 30;
 	sc->sc_rxchaindetect_delta2GHz = 30;
 
-	/*
-	 * Query the hal about antenna support
-	 * Enable rx fast diversity if hal has support
-	 */
-	if (ath9k_hw_getcapability(ah, HAL_CAP_DIVERSITY, 0, NULL)) {
-		sc->sc_hasdiversity = 1;
-		ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
-			1, AH_TRUE, NULL);
-		sc->sc_diversity = 1;
-	} else {
-		sc->sc_hasdiversity = 0;
-		sc->sc_diversity = 0;
-		ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
-			1, AH_FALSE, NULL);
-	}
+	ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, true, NULL);
 	sc->sc_defant = ath9k_hw_getdefantenna(ah);
 
-	/*
-	 * Not all chips have the VEOL support we want to
-	 * use with IBSS beacons; check here for it.
-	 */
-	sc->sc_hasveol = ah->ah_caps.halVEOLSupport;
-
 	ath9k_hw_getmac(ah, sc->sc_myaddr);
-	if (sc->sc_hasbmask) {
+	if (ah->ah_caps.halBssIdMaskSupport) {
 		ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
 		ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
 		ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
 	}
-	sc->sc_hasautosleep = ah->ah_caps.halAutoSleepSupport;
-	sc->sc_waitbeacon = 0;
 	sc->sc_slottime = HAL_SLOT_TIME_9;	/* default to short slot time */
 
 	/* initialize beacon slots */
@@ -1627,11 +1324,8 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	sc->sc_config.swBeaconProcess = 1;
 
 #ifdef CONFIG_SLOW_ANT_DIV
-	sc->sc_slowAntDiv = 1;
 	/* range is 40 - 255, we use something in the middle */
 	ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
-#else
-	sc->sc_slowAntDiv = 0;
 #endif
 
 	return 0;
@@ -1651,7 +1345,7 @@ void ath_deinit(struct ath_softc *sc)
 	struct ath_hal *ah = sc->sc_ah;
 	int i;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s\n", __func__);
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
 
 	ath_stop(sc);
 	if (!sc->sc_invalid)
@@ -1695,9 +1389,6 @@ struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
 	ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
 	list_add(&an->list, &sc->node_list);
 
-	DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p for: %s\n",
-		__func__, an, print_mac(mac, addr));
-
 	return an;
 }
 
@@ -1721,9 +1412,6 @@ void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
 
 	spin_unlock_irqrestore(&sc->node_lock, flags);
 
-	DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p for: %s\n",
-		__func__, an, print_mac(mac, an->an_addr));
-
 	kfree(an);
 }
 
@@ -1799,6 +1487,7 @@ void ath_newassoc(struct ath_softc *sc,
 /**************/
 /* Encryption */
 /**************/
+
 void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
 {
 	ath9k_hw_keyreset(sc->sc_ah, keyix);
@@ -1811,12 +1500,12 @@ int ath_keyset(struct ath_softc *sc,
 	       struct hal_keyval *hk,
 	       const u_int8_t mac[ETH_ALEN])
 {
-	enum hal_bool status;
+	bool status;
 
 	status = ath9k_hw_set_keycache_entry(sc->sc_ah,
-		keyix, hk, mac, AH_FALSE);
+		keyix, hk, mac, false);
 
-	return status != AH_FALSE;
+	return status != false;
 }
 
 /***********************/
@@ -2020,12 +1709,12 @@ int ath_descdma_setup(struct ath_softc *sc,
 	struct ath_buf *bf;
 	int i, bsize, error;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
 		__func__, name, nbuf, ndesc);
 
 	/* ath_desc must be a multiple of DWORDs */
 	if ((sizeof(struct ath_desc) % 4) != 0) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: ath_desc not DWORD aligned\n",
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
 			__func__);
 		ASSERT((sizeof(struct ath_desc) % 4) == 0);
 		error = -ENOMEM;
@@ -2062,7 +1751,7 @@ int ath_descdma_setup(struct ath_softc *sc,
 		goto fail;
 	}
 	ds = dd->dd_desc;
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
 		__func__, dd->dd_name, ds, (u_int32_t) dd->dd_desc_len,
 		ito64(dd->dd_desc_paddr), /*XXX*/(u_int32_t) dd->dd_desc_len);
 
@@ -2143,14 +1832,6 @@ void ath_internal_reset(struct ath_softc *sc)
 	ath_reset_end(sc, 0);
 }
 
-void ath_setrxfilter(struct ath_softc *sc)
-{
-	u_int32_t rxfilt;
-
-	rxfilt = ath_calcrxfilter(sc);
-	ath9k_hw_setrxfilter(sc->sc_ah, rxfilt);
-}
-
 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
 {
 	int qnum;
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/core.h b/package/ath9k/src/drivers/net/wireless/ath9k/core.h
index 9348107187..b2713438eb 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/core.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/core.h
@@ -156,13 +156,6 @@ static inline void list_cut_position(struct list_head *list,
 		}				\
 	} while (0)
 
-#define KASSERT(exp, msg) do {			\
-		if (unlikely(!(exp))) {         \
-			printk msg;		\
-			BUG();			\
-		}				\
-	} while (0)
-
 /* XXX: remove */
 #define memzero(_buf, _len) memset(_buf, 0, _len)
 
@@ -184,23 +177,29 @@ static inline unsigned long get_timestamp(void)
 /*************/
 
 enum ATH_DEBUG {
-	ATH_DEBUG_XMIT          = 0x00000001,   /* basic xmit operation */
-	ATH_DEBUG_RECV          = 0x00000002,   /* basic recv operation */
-	ATH_DEBUG_BEACON        = 0x00000004,   /* beacon handling */
-	ATH_DEBUG_TX_PROC       = 0x00000008,   /* tx ISR proc */
-	ATH_DEBUG_RX_PROC       = 0x00000010,   /* rx ISR proc */
-	ATH_DEBUG_BEACON_PROC   = 0x00000020,   /* beacon ISR proc */
-	ATH_DEBUG_RATE          = 0x00000040,   /* rate control */
-	ATH_DEBUG_CONFIG        = 0x00000080,   /* configuration */
-	ATH_DEBUG_KEYCACHE      = 0x00000100,   /* key cache management */
-	ATH_DEBUG_NODE          = 0x00000200,   /* node management */
-	ATH_DEBUG_AGGR		= 0x00000400,	/* Aggregation */
-	ATH_DEBUG_CWM		= 0x00000800,	/* Channel Width Management */
-	ATH_DEBUG_FATAL         = 0x00001000,   /* fatal errors */
-	ATH_DEBUG_ANY           = 0xffffffff
+	ATH_DBG_RESET		= 0x00000001,
+	ATH_DBG_PHY_IO		= 0x00000002,
+	ATH_DBG_REG_IO		= 0x00000004,
+	ATH_DBG_QUEUE		= 0x00000008,
+	ATH_DBG_EEPROM		= 0x00000010,
+	ATH_DBG_NF_CAL		= 0x00000020,
+	ATH_DBG_CALIBRATE	= 0x00000040,
+	ATH_DBG_CHANNEL		= 0x00000080,
+	ATH_DBG_INTERRUPT	= 0x00000100,
+	ATH_DBG_REGULATORY	= 0x00000200,
+	ATH_DBG_ANI		= 0x00000400,
+	ATH_DBG_POWER_MGMT	= 0x00000800,
+	ATH_DBG_XMIT		= 0x00001000,
+	ATH_DBG_BEACON		= 0x00002000,
+	ATH_DBG_RATE		= 0x00004000,
+	ATH_DBG_CONFIG		= 0x00008000,
+	ATH_DBG_KEYCACHE	= 0x00010000,
+	ATH_DBG_AGGR		= 0x00020000,
+	ATH_DBG_FATAL		= 0x00040000,
+	ATH_DBG_ANY		= 0xffffffff
 };
 
-#define DBG_DEFAULT (ATH_DEBUG_FATAL)
+#define DBG_DEFAULT (ATH_DBG_FATAL)
 
 #define	DPRINTF(sc, _m, _fmt, ...) do {			\
 		if (sc->sc_debug & (_m))                \
@@ -214,7 +213,6 @@ enum ATH_DEBUG {
 /* Per-instance load-time (note: NOT run-time) configurations
  * for Atheros Device */
 struct ath_config {
-	u_int8_t    chainmask_sel; /* enable automatic tx chainmask selection */
 	u_int32_t   ath_aggr_prot;
 	u_int16_t   txpowlimit;
 	u_int16_t   txpowlimit_override;
@@ -249,6 +247,7 @@ struct ath_chainmask_sel {
 };
 
 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
+void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 
 /*************************/
 /* Descriptor Management */
@@ -452,9 +451,8 @@ struct ath_arx {
 	struct ath_arx_tid  tid[WME_NUM_TID];
 };
 
-void ath_setrxfilter(struct ath_softc *sc);
 int ath_startrecv(struct ath_softc *sc);
-enum hal_bool ath_stoprecv(struct ath_softc *sc);
+bool ath_stoprecv(struct ath_softc *sc);
 void ath_flushrecv(struct ath_softc *sc);
 u_int32_t ath_calcrxfilter(struct ath_softc *sc);
 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
@@ -635,9 +633,9 @@ struct ath_tx_stat {
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 int ath_tx_setup(struct ath_softc *sc, int haltype);
-void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx);
+void ath_draintxq(struct ath_softc *sc, bool retry_tx);
 void ath_tx_draintxq(struct ath_softc *sc,
-	struct ath_txq *txq, enum hal_bool retry_tx);
+	struct ath_txq *txq, bool retry_tx);
 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 void ath_tx_node_cleanup(struct ath_softc *sc,
 	struct ath_node *an, bool bh_flag);
@@ -695,7 +693,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
 #define ATH_DS_BA_SEQ(_ds)               ((_ds)->ds_us.tx.ts_seqnum)
 #define ATH_DS_BA_BITMAP(_ds)            (&(_ds)->ds_us.tx.ba_low)
-#define ATH_DS_TX_BA(_ds)                ((_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
+#define ATH_DS_TX_BA(_ds)	((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 #define ATH_AN_2_TID(_an, _tidno)        (&(_an)->an_aggr.tx.tid[(_tidno)])
 
 enum ATH_AGGR_STATUS {
@@ -822,10 +820,6 @@ void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi);
 void ath_get_beaconconfig(struct ath_softc *sc,
 			  int if_id,
 			  struct ath_beacon_config *conf);
-struct sk_buff *ath_get_beacon(struct ath_softc *sc,
-			       int if_id,
-			       struct ath_beacon_offset *bo,
-			       struct ath_tx_control *txctl);
 int ath_update_beacon(struct ath_softc *sc,
 		      int if_id,
 		      struct ath_beacon_offset *bo,
@@ -880,23 +874,11 @@ struct ath_vap {
 int ath_vap_attach(struct ath_softc *sc,
 		   int if_id,
 		   struct ieee80211_vif *if_data,
-		   enum hal_opmode opmode,
-		   enum hal_opmode iv_opmode,
-		   int nostabeacons);
+		   enum hal_opmode opmode);
 int ath_vap_detach(struct ath_softc *sc, int if_id);
 int ath_vap_config(struct ath_softc *sc,
 	int if_id, struct ath_vap_config *if_config);
-int ath_vap_down(struct ath_softc *sc, int if_id, u_int flags);
 int ath_vap_listen(struct ath_softc *sc, int if_id);
-int ath_vap_join(struct ath_softc *sc,
-		 int if_id,
-		 const u_int8_t bssid[ETH_ALEN],
-		 u_int flags);
-int ath_vap_up(struct ath_softc *sc,
-	       int if_id,
-	       const u_int8_t bssid[ETH_ALEN],
-	       u_int8_t aid,
-	       u_int flags);
 
 /*********************/
 /* Antenna diversity */
@@ -972,12 +954,6 @@ void ath_setdefantenna(void *sc, u_int antenna);
 
 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 
-#define ATH_ISR_NOSCHED         0x0000	/* Do not schedule bottom half */
-/* Schedule the bottom half for execution */
-#define ATH_ISR_SCHED           0x0001
-/* This was not my interrupt, for shared IRQ's */
-#define ATH_ISR_NOTMINE         0x0002
-
 #define RSSI_LPF_THRESHOLD         -20
 #define ATH_RSSI_EP_MULTIPLIER     (1<<7)  /* pow2 to optimize out * and / */
 #define ATH_RATE_DUMMY_MARKER      0
@@ -1042,34 +1018,13 @@ struct ath_softc {
 	enum hal_opmode         sc_opmode;  /* current operating mode */
 
 	/* Properties, Config */
-	unsigned int
-		sc_invalid             : 1, /* being detached */
-		sc_mrretry             : 1, /* multi-rate retry support */
-		sc_needmib             : 1, /* enable MIB stats intr */
-		sc_hasdiversity        : 1, /* rx diversity available */
-		sc_diversity           : 1, /* enable rx diversity */
-		sc_hasveol             : 1, /* tx VEOL support */
-		sc_beacons             : 1, /* beacons running */
-		sc_hasbmask            : 1, /* bssid mask support */
-		sc_hastsfadd           : 1, /* tsf adjust support */
-		sc_scanning            : 1, /* scanning active */
-		sc_nostabeacons        : 1, /* no beacons for station */
-		sc_hasclrkey           : 1, /* CLR key supported */
-		sc_stagbeacons         : 1, /* use staggered beacons */
-		sc_txaggr              : 1, /* enable 11n tx aggregation */
-		sc_rxaggr              : 1, /* enable 11n rx aggregation */
-		sc_hasautosleep        : 1, /* automatic sleep after TIM */
-		sc_waitbeacon          : 1, /* waiting for first beacon
-						after waking up */
-		sc_no_tx_3_chains      : 1, /* user, hardware, regulatory
-					or country may disallow transmit on
-					three chains. */
-		sc_update_chainmask    : 1, /* change chain mask */
-		sc_rx_chainmask_detect : 1, /* enable rx chain mask detection */
-		sc_rx_chainmask_start  : 1, /* start rx chain mask detection */
-		sc_hashtsupport        : 1, /* supports 11n */
-		sc_full_reset          : 1, /* force full reset */
-		sc_slowAntDiv          : 1; /* enable slow antenna diversity */
+	u_int8_t                sc_invalid;	/* being detached */
+	u_int8_t                sc_beacons;	/* beacons running */
+	u_int8_t                sc_scanning;	/* scanning active */
+	u_int8_t                sc_txaggr;	/* enable 11n tx aggregation */
+	u_int8_t                sc_rxaggr;	/* enable 11n rx aggregation */
+	u_int8_t                sc_update_chainmask;	/* change chain mask */
+	u_int8_t                sc_full_reset;		/* force full reset */
 	enum wireless_mode      sc_curmode;     /* current phy mode */
 	u_int16_t               sc_curtxpow;    /* current tx power limit */
 	u_int16_t               sc_curaid;      /* current association id */
@@ -1119,7 +1074,7 @@ struct ath_softc {
 
 	/* Crypto */
 	u_int                   sc_keymax;      /* size of key cache */
-	u_int8_t                sc_keymap[ATH_KEYBYTES];/* key use bit map */
+	DECLARE_BITMAP		(sc_keymap, ATH_KEYBYTES);/* key use bit map */
 	u_int8_t		sc_splitmic;	/* split TKIP MIC keys */
 	int                     sc_keytype;     /* type of the key being used */
 
@@ -1181,7 +1136,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc);
 void ath_deinit(struct ath_softc *sc);
 int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
 int ath_suspend(struct ath_softc *sc);
-int ath_intr(struct ath_softc *sc);
+irqreturn_t ath_isr(int irq, void *dev);
 int ath_reset(struct ath_softc *sc);
 void ath_scan_start(struct ath_softc *sc);
 void ath_scan_end(struct ath_softc *sc);
@@ -1202,7 +1157,6 @@ void ath_setup_rate(struct ath_softc *sc,
 /* Utility Functions */
 /*********************/
 
-void ath_set_macmode(struct ath_softc *sc, enum hal_ht_macmode macmode);
 void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
 int ath_keyset(struct ath_softc *sc,
 	       u_int16_t keyix,
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/hw.c b/package/ath9k/src/drivers/net/wireless/ath9k/hw.c
index de91934468..a16dbfbd49 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/hw.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/hw.c
@@ -16,7 +16,7 @@
 
 #include <linux/io.h>
 
-#include "ath9k.h"
+#include "core.h"
 #include "hw.h"
 #include "reg.h"
 #include "phy.h"
@@ -111,14 +111,14 @@ static struct hal_rate_table ar5416_11a_table = {
 	8,
 	{0},
 	{
-		{AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
-		{AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
-		{AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
-		{AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
-		{AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
-		{AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
-		{AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
-		{AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
+		{true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
+		{true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
+		{true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
+		{true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
+		{true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
+		{true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
+		{true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
+		{true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
 	},
 };
 
@@ -126,10 +126,10 @@ static struct hal_rate_table ar5416_11b_table = {
 	4,
 	{0},
 	{
-		{AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
-		{AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
-		{AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
-		{AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
+		{true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
+		{true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
+		{true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
+		{true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
 	},
 };
 
@@ -137,19 +137,19 @@ static struct hal_rate_table ar5416_11g_table = {
 	12,
 	{0},
 	{
-		{AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
-		{AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
-		{AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
-		{AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
-
-		{AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
-		{AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
-		{AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
-		{AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
-		{AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
-		{AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
-		{AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
-		{AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
+		{true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
+		{true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
+		{true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
+		{true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
+
+		{false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
+		{false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
+		{true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
+		{true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
+		{true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
+		{true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
+		{true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
+		{true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
 	},
 };
 
@@ -157,35 +157,35 @@ static struct hal_rate_table ar5416_11ng_table = {
 	28,
 	{0},
 	{
-		{AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
-		{AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
-		{AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
-		{AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
-
-		{AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
-		{AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
-		{AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
-		{AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
-		{AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
-		{AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
-		{AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
-		{AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
-		{AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 4},
-		{AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 6},
-		{AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 6},
-		{AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 8},
-		{AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 8},
-		{AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 8},
-		{AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 8},
-		{AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 8},
-		{AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 4},
-		{AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 6},
-		{AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
-		{AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
-		{AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
-		{AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
-		{AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
-		{AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
+		{true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
+		{true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
+		{true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
+		{true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
+
+		{false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
+		{false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
+		{true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
+		{true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
+		{true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
+		{true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
+		{true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
+		{true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
+		{true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
+		{true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
+		{true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
+		{true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
+		{true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
+		{true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
+		{true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
+		{true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
+		{true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
+		{true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
+		{true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
+		{true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
+		{true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
+		{true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
+		{true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
+		{true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
 	},
 };
 
@@ -193,30 +193,30 @@ static struct hal_rate_table ar5416_11na_table = {
 	24,
 	{0},
 	{
-		{AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
-		{AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
-		{AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
-		{AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
-		{AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
-		{AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
-		{AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
-		{AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
-		{AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 0},
-		{AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 2},
-		{AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 2},
-		{AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 4},
-		{AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 4},
-		{AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 4},
-		{AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 4},
-		{AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 4},
-		{AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 0},
-		{AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 2},
-		{AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
-		{AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
-		{AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
-		{AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
-		{AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
-		{AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
+		{true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
+		{true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
+		{true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
+		{true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
+		{true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
+		{true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
+		{true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
+		{true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
+		{true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
+		{true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
+		{true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
+		{true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
+		{true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
+		{true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
+		{true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
+		{true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
+		{true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
+		{true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
+		{true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
+		{true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
+		{true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
+		{true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
+		{true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
+		{true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
 	},
 };
 
@@ -230,27 +230,27 @@ static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
 	return WIRELESS_MODE_11a;
 }
 
-static enum hal_bool ath9k_hw_wait(struct ath_hal *ah,
-			    u_int reg,
-			    u_int32_t mask,
-			    u_int32_t val)
+static bool ath9k_hw_wait(struct ath_hal *ah,
+			  u_int reg,
+			  u_int32_t mask,
+			  u_int32_t val)
 {
 	int i;
 
 	for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 		if ((REG_READ(ah, reg) & mask) == val)
-			return AH_TRUE;
+			return true;
 
 		udelay(AH_TIME_QUANTUM);
 	}
-	HDPRINTF(ah, HAL_DBG_PHY_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 		 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 		 __func__, reg, REG_READ(ah, reg), mask, val);
-	return AH_FALSE;
+	return false;
 }
 
-static enum hal_bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
-				   u_int16_t *data)
+static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
+				 u_int16_t *data)
 {
 	(void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 
@@ -258,13 +258,13 @@ static enum hal_bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
 			   AR_EEPROM_STATUS_DATA,
 			   AR_EEPROM_STATUS_DATA_BUSY |
 			   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
-		return AH_FALSE;
+		return false;
 	}
 
 	*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 		   AR_EEPROM_STATUS_DATA_VAL);
 
-	return AH_TRUE;
+	return true;
 }
 
 static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
@@ -274,7 +274,7 @@ static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
 	ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
 
 	if (!ahp->ah_cal_mem) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: cannot remap eeprom region \n", __func__);
 		return HAL_EIO;
 	}
@@ -282,13 +282,13 @@ static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
 	return HAL_OK;
 }
 
-static enum hal_bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
-				  u_int16_t *data)
+static bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
+				u_int16_t *data)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	*data = ioread16(ahp->ah_cal_mem + off);
-	return AH_TRUE;
+	return true;
 }
 
 static void ath9k_hw_read_revisions(struct ath_hal *ah)
@@ -314,7 +314,7 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah)
 		ah->ah_macRev = val & AR_SREV_REVISION;
 
 		if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
-			ah->ah_isPciExpress = AH_TRUE;
+			ah->ah_isPciExpress = true;
 	}
 }
 
@@ -368,7 +368,6 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah)
 	}
 
 	ah->ah_config.ath_hal_intrMitigation = 0;
-	ah->ah_config.ath_hal_debug = 0;
 }
 
 static inline void ath9k_hw_override_ini(struct ath_hal *ah,
@@ -513,9 +512,9 @@ ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
 	return HAL_EINVAL;
 }
 
-static inline enum hal_bool ath9k_hw_nvram_read(struct ath_hal *ah,
-						u_int off,
-						u_int16_t *data)
+static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
+				       u_int off,
+				       u_int16_t *data)
 {
 	if (ath9k_hw_use_flash(ah))
 		return ath9k_hw_flash_read(ah, off, data);
@@ -523,7 +522,7 @@ static inline enum hal_bool ath9k_hw_nvram_read(struct ath_hal *ah,
 		return ath9k_hw_eeprom_read(ah, off, data);
 }
 
-static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
+static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416_eeprom *eep = &ahp->ah_eeprom;
@@ -531,7 +530,7 @@ static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 	int addr, ar5416_eep_start_loc = 0;
 
 	if (!ath9k_hw_use_flash(ah)) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: Reading from EEPROM, not flash\n", __func__);
 		ar5416_eep_start_loc = 256;
 	}
@@ -544,18 +543,18 @@ static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 	     addr++) {
 		if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
 					 eep_data)) {
-			HDPRINTF(ah, HAL_DBG_EEPROM,
+			DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 				 "%s: Unable to read eeprom region \n",
 				 __func__);
-			return AH_FALSE;
+			return false;
 		}
 		eep_data++;
 	}
-	return AH_TRUE;
+	return true;
 }
 
 /* XXX: Clean me up, make me more legible */
-static enum hal_bool
+static bool
 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 				 struct hal_channel_internal *chan)
 {
@@ -602,33 +601,34 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 
 		if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
 			if ((eep->baseEepHeader.version &
-			AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_3) {
+			     AR5416_EEP_VER_MINOR_MASK) >=
+			    AR5416_EEP_MINOR_VER_3) {
 				txRxAttenLocal = pModal->txRxAttenCh[i];
 				if (AR_SREV_9280_10_OR_LATER(ah)) {
-					OS_REG_RMW_FIELD(ah,
-						 AR_PHY_GAIN_2GHZ +
-						 regChainOffset,
-					 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
-						 pModal->
-						 bswMargin[i]);
-					OS_REG_RMW_FIELD(ah,
-						 AR_PHY_GAIN_2GHZ +
-						 regChainOffset,
-						 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
-						 pModal->
-						 bswAtten[i]);
-					OS_REG_RMW_FIELD(ah,
-						 AR_PHY_GAIN_2GHZ +
-						 regChainOffset,
-					 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
-						 pModal->
-						 xatten2Margin[i]);
-					OS_REG_RMW_FIELD(ah,
-						 AR_PHY_GAIN_2GHZ +
-						 regChainOffset,
-						 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
-						 pModal->
-						 xatten2Db[i]);
+					REG_RMW_FIELD(ah,
+						AR_PHY_GAIN_2GHZ +
+						regChainOffset,
+						AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
+						pModal->
+						bswMargin[i]);
+					REG_RMW_FIELD(ah,
+						AR_PHY_GAIN_2GHZ +
+						regChainOffset,
+						AR_PHY_GAIN_2GHZ_XATTEN1_DB,
+						pModal->
+						bswAtten[i]);
+					REG_RMW_FIELD(ah,
+						AR_PHY_GAIN_2GHZ +
+						regChainOffset,
+						AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
+						pModal->
+						xatten2Margin[i]);
+					REG_RMW_FIELD(ah,
+						AR_PHY_GAIN_2GHZ +
+						regChainOffset,
+						AR_PHY_GAIN_2GHZ_XATTEN2_DB,
+						pModal->
+						xatten2Db[i]);
 				} else {
 					REG_WRITE(ah,
 						  AR_PHY_GAIN_2GHZ +
@@ -638,8 +638,8 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 							    regChainOffset) &
 						   ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 						  | SM(pModal->
-					       bswMargin[i],
-					       AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+						  bswMargin[i],
+						  AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 					REG_WRITE(ah,
 						  AR_PHY_GAIN_2GHZ +
 						  regChainOffset,
@@ -648,20 +648,20 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 							    regChainOffset) &
 						   ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 						  | SM(pModal->bswAtten[i],
-					       AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+						  AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 				}
 			}
 			if (AR_SREV_9280_10_OR_LATER(ah)) {
-				OS_REG_RMW_FIELD(ah,
-						 AR_PHY_RXGAIN +
-						 regChainOffset,
-						 AR9280_PHY_RXGAIN_TXRX_ATTEN,
-						 txRxAttenLocal);
-				OS_REG_RMW_FIELD(ah,
-						 AR_PHY_RXGAIN +
-						 regChainOffset,
-						 AR9280_PHY_RXGAIN_TXRX_MARGIN,
-						 pModal->rxTxMarginCh[i]);
+				REG_RMW_FIELD(ah,
+					      AR_PHY_RXGAIN +
+					      regChainOffset,
+					      AR9280_PHY_RXGAIN_TXRX_ATTEN,
+					      txRxAttenLocal);
+				REG_RMW_FIELD(ah,
+					      AR_PHY_RXGAIN +
+					      regChainOffset,
+					      AR9280_PHY_RXGAIN_TXRX_MARGIN,
+					      pModal->rxTxMarginCh[i]);
 			} else {
 				REG_WRITE(ah,
 					  AR_PHY_RXGAIN + regChainOffset,
@@ -728,21 +728,21 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 					  AR_AN_TOP2_LOCALBIAS,
 					  AR_AN_TOP2_LOCALBIAS_S,
 					  pModal->local_bias);
-		HDPRINTF(NULL, HAL_DBG_UNMASKABLE, "ForceXPAon: %d\n",
-			 pModal->force_xpaon);
-		OS_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
-				 pModal->force_xpaon);
+		DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
+			pModal->force_xpaon);
+		REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
+			      pModal->force_xpaon);
 	}
 
-	OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
-			 pModal->switchSettling);
-	OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
-			 pModal->adcDesiredSize);
+	REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
+		      pModal->switchSettling);
+	REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
+		      pModal->adcDesiredSize);
 
 	if (!AR_SREV_9280_10_OR_LATER(ah))
-		OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
-				 AR_PHY_DESIRED_SZ_PGA,
-				 pModal->pgaDesiredSize);
+		REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+			      AR_PHY_DESIRED_SZ_PGA,
+			      pModal->pgaDesiredSize);
 
 	REG_WRITE(ah, AR_PHY_RF_CTL4,
 		  SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
@@ -753,40 +753,40 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 		  | SM(pModal->txFrameToXpaOn,
 		       AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 
-	OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
-			 pModal->txEndToRxOn);
+	REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
+		      pModal->txEndToRxOn);
 	if (AR_SREV_9280_10_OR_LATER(ah)) {
-		OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
-				 pModal->thresh62);
-		OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
-				 AR_PHY_EXT_CCA0_THRESH62,
-				 pModal->thresh62);
+		REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
+			      pModal->thresh62);
+		REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
+			      AR_PHY_EXT_CCA0_THRESH62,
+			      pModal->thresh62);
 	} else {
-		OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
-				 pModal->thresh62);
-		OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
-				 AR_PHY_EXT_CCA_THRESH62,
-				 pModal->thresh62);
+		REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
+			      pModal->thresh62);
+		REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
+			      AR_PHY_EXT_CCA_THRESH62,
+			      pModal->thresh62);
 	}
 
 	if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 	    AR5416_EEP_MINOR_VER_2) {
-		OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
-				 AR_PHY_TX_END_DATA_START,
-				 pModal->txFrameToDataStart);
-		OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
-				 pModal->txFrameToPaOn);
+		REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
+			      AR_PHY_TX_END_DATA_START,
+			      pModal->txFrameToDataStart);
+		REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
+			      pModal->txFrameToPaOn);
 	}
 
 	if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 	    AR5416_EEP_MINOR_VER_3) {
 		if (IS_CHAN_HT40(chan))
-			OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
-					 AR_PHY_SETTLING_SWITCH,
-					 pModal->swSettleHt40);
+			REG_RMW_FIELD(ah, AR_PHY_SETTLING,
+				      AR_PHY_SETTLING_SWITCH,
+				      pModal->swSettleHt40);
 	}
 
-	return AH_TRUE;
+	return true;
 }
 
 static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
@@ -795,7 +795,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 	u_int16_t *eepdata;
 	int i;
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	enum hal_bool need_swap = AH_FALSE;
+	bool need_swap = false;
 	struct ar5416_eeprom *eep =
 		(struct ar5416_eeprom *) &ahp->ah_eeprom;
 
@@ -805,18 +805,18 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 
 		if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 					&magic)) {
-			HDPRINTF(ah, HAL_DBG_EEPROM,
+			DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 				 "%s: Reading Magic # failed\n", __func__);
-			return AH_FALSE;
+			return false;
 		}
-		HDPRINTF(ah, HAL_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
 			 __func__, magic);
 
 		if (magic != AR5416_EEPROM_MAGIC) {
 			magic2 = swab16(magic);
 
 			if (magic2 == AR5416_EEPROM_MAGIC) {
-				need_swap = AH_TRUE;
+				need_swap = true;
 				eepdata = (u_int16_t *) (&ahp->ah_eeprom);
 
 				for (addr = 0;
@@ -829,22 +829,22 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 					*eepdata = temp;
 					eepdata++;
 
-					HDPRINTF(ah, HAL_DBG_EEPROM_DUMP,
+					DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 						 "0x%04X  ", *eepdata);
 					if (((addr + 1) % 6) == 0)
-						HDPRINTF(ah,
-							 HAL_DBG_EEPROM_DUMP,
+						DPRINTF(ah->ah_sc,
+							 ATH_DBG_EEPROM,
 							 "\n");
 				}
 			} else {
-				HDPRINTF(ah, HAL_DBG_EEPROM,
+				DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 					 "Invalid EEPROM Magic. "
 					"endianness missmatch.\n");
 				return HAL_EEBADSUM;
 			}
 		}
 	}
-	HDPRINTF(ah, HAL_DBG_EEPROM, "need_swap = %s.\n",
+	DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 		 need_swap ? "True" : "False");
 
 	if (need_swap)
@@ -852,7 +852,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 	else
 		el = ahp->ah_eeprom.baseEepHeader.length;
 
-	if (el < sizeof(struct ar5416_eeprom))
+	if (el > sizeof(struct ar5416_eeprom))
 		el = sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
 	else
 		el = el / sizeof(u_int16_t);
@@ -866,7 +866,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 		u_int32_t integer, j;
 		u_int16_t word;
 
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "EEPROM Endianness is not native.. Changing \n");
 
 		word = swab16(eep->baseEepHeader.length);
@@ -913,7 +913,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 
 	if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
 	    ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 			 sum, ar5416_get_eep_ver(ahp));
 		return HAL_EEBADSUM;
@@ -922,7 +922,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 	return HAL_OK;
 }
 
-static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
+static bool ath9k_hw_chip_test(struct ath_hal *ah)
 {
 	u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 	u_int32_t regHold[2];
@@ -942,11 +942,11 @@ static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
 			REG_WRITE(ah, addr, wrData);
 			rdData = REG_READ(ah, addr);
 			if (rdData != wrData) {
-				HDPRINTF(ah, HAL_DBG_REG_IO,
+				DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 				 "%s: address test failed "
 				"addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 				 __func__, addr, wrData, rdData);
-				return AH_FALSE;
+				return false;
 			}
 		}
 		for (j = 0; j < 4; j++) {
@@ -954,17 +954,17 @@ static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
 			REG_WRITE(ah, addr, wrData);
 			rdData = REG_READ(ah, addr);
 			if (wrData != rdData) {
-				HDPRINTF(ah, HAL_DBG_REG_IO,
+				DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 				 "%s: address test failed "
 				"addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 				 __func__, addr, wrData, rdData);
-				return AH_FALSE;
+				return false;
 			}
 		}
 		REG_WRITE(ah, regAddr[i], regHold[i]);
 	}
 	udelay(100);
-	return AH_TRUE;
+	return true;
 }
 
 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah)
@@ -999,11 +999,11 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
 			  REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 }
 
-enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
-				     enum hal_capability_type type,
-				     u_int32_t capability,
-				     u_int32_t setting,
-				     enum hal_status *status)
+bool ath9k_hw_setcapability(struct ath_hal *ah,
+			    enum hal_capability_type type,
+			    u_int32_t capability,
+			    u_int32_t setting,
+			    enum hal_status *status)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	u_int32_t v;
@@ -1016,7 +1016,7 @@ enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
 		else
 			ahp->ah_staId1Defaults &=
 				~AR_STA_ID1_CRPT_MIC_ENABLE;
-		return AH_TRUE;
+		return true;
 	case HAL_CAP_DIVERSITY:
 		v = REG_READ(ah, AR_PHY_CCK_DETECT);
 		if (setting)
@@ -1024,21 +1024,21 @@ enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
 		else
 			v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 		REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
-		return AH_TRUE;
+		return true;
 	case HAL_CAP_MCAST_KEYSRCH:
 		if (setting)
 			ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
 		else
 			ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
-		return AH_TRUE;
+		return true;
 	case HAL_CAP_TSF_ADJUST:
 		if (setting)
 			ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
 		else
 			ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
-		return AH_TRUE;
+		return true;
 	default:
-		return AH_FALSE;
+		return false;
 	}
 }
 
@@ -1054,17 +1054,17 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
 		   (AR_MACMISC_MISC_OBS_BUS_1 <<
 		    AR_MACMISC_MISC_OBS_BUS_MSB_S)));
 
-	HDPRINTF(ah, HAL_DBG_REG_IO, "Raw DMA Debug values:\n");
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
 	for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
 		if (i % 4 == 0)
-			HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
+			DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
 
 		val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
-		HDPRINTF(ah, HAL_DBG_REG_IO, "%d: %08x ", i, val[i]);
+		DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
 	}
 
-	HDPRINTF(ah, HAL_DBG_REG_IO, "\n\n");
-	HDPRINTF(ah, HAL_DBG_REG_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 		 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
 
 	for (i = 0; i < ATH9K_NUM_QUEUES;
@@ -1079,7 +1079,7 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
 			dcuBase++;
 		}
 
-		HDPRINTF(ah, HAL_DBG_REG_IO,
+		DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 			 "%2d          %2x      %1x     %2x           %2x\n",
 			 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
 			 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
@@ -1088,29 +1088,30 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
 			 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
 	}
 
-	HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
-	HDPRINTF(ah, HAL_DBG_REG_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 		 "qcu_stitch state:   %2x    qcu_fetch state:        %2x\n",
 		 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
-	HDPRINTF(ah, HAL_DBG_REG_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 		 "qcu_complete state: %2x    dcu_complete state:     %2x\n",
 		 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
-	HDPRINTF(ah, HAL_DBG_REG_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 		 "dcu_arb state:      %2x    dcu_fp state:           %2x\n",
 		 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
-	HDPRINTF(ah, HAL_DBG_REG_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 		 "chan_idle_dur:     %3d    chan_idle_dur_valid:     %1d\n",
 		 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
-	HDPRINTF(ah, HAL_DBG_REG_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 		 "txfifo_valid_0:      %1d    txfifo_valid_1:          %1d\n",
 		 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
-	HDPRINTF(ah, HAL_DBG_REG_IO,
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 		 "txfifo_dcu_num_0:   %2d    txfifo_dcu_num_1:       %2d\n",
 		 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
 
-	HDPRINTF(ah, HAL_DBG_REG_IO, "pcu observe 0x%x \n",
-		 REG_READ(ah, AR_OBS_BUS_1));
-	HDPRINTF(ah, HAL_DBG_REG_IO, "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
+		REG_READ(ah, AR_OBS_BUS_1));
+	DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
+		"AR_CR 0x%x \n", REG_READ(ah, AR_CR));
 }
 
 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
@@ -1127,7 +1128,7 @@ u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
 	u_int32_t cc = REG_READ(ah, AR_CCCNT);
 
 	if (cycles == 0 || cycles > cc) {
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: cycle counter wrap. ExtBusy = 0\n",
 			 __func__);
 		good = 0;
@@ -1173,7 +1174,8 @@ static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
 }
 
 
-static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
+static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
+					      struct ath_softc *sc,
 					      void __iomem *mem,
 					      enum hal_status *status)
 {
@@ -1184,7 +1186,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
 
 	ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 	if (ahp == NULL) {
-		HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			 "%s: cannot allocate memory for state block\n",
 			 __func__);
 		*status = HAL_ENOMEM;
@@ -1320,7 +1322,7 @@ static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
 		ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 	}
 	if (sum == 0 || sum == 0xffff * 3) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: mac address read failed: %s\n", __func__,
 			 print_mac(mac, ahp->ah_macaddr));
 		return HAL_EEBADMAC;
@@ -1348,7 +1350,7 @@ static inline int16_t ath9k_hw_interpolate(u_int16_t target,
 }
 
 static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
-					   enum hal_bool is2GHz)
+					   bool is2GHz)
 {
 
 	if (fbin == AR5416_BCHAN_UNUSED)
@@ -1359,14 +1361,14 @@ static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
 
 static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
 					       u_int16_t i,
-					       enum hal_bool is2GHz)
+					       bool is2GHz)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416_eeprom *eep =
 		(struct ar5416_eeprom *) &ahp->ah_eeprom;
 	u_int16_t spur_val = AR_NO_SPUR;
 
-	HDPRINTF(ah, HAL_DBG_ANI,
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 		 "Getting spur idx %d is2Ghz. %d val %x\n",
 		 i, is2GHz, ah->ah_config.ath_hal_spurChans[i][is2GHz]);
 
@@ -1375,7 +1377,7 @@ static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
 		break;
 	case SPUR_ENABLE_IOCTL:
 		spur_val = ah->ah_config.ath_hal_spurChans[i][is2GHz];
-		HDPRINTF(ah, HAL_DBG_ANI,
+		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 			 "Getting spur val from new loc. %d\n", spur_val);
 		break;
 	case SPUR_ENABLE_EEPROM:
@@ -1388,12 +1390,12 @@ static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
 
 static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
 {
-	enum hal_bool rfStatus = AH_FALSE;
+	bool rfStatus = false;
 	enum hal_status ecode = HAL_OK;
 
 	rfStatus = ath9k_hw_init_rf(ah, &ecode);
 	if (!rfStatus) {
-		HDPRINTF(ah, HAL_DBG_RESET,
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			 "%s: RF setup failed, status %u\n", __func__,
 			 ecode);
 		return ecode;
@@ -1419,7 +1421,7 @@ static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
 	case AR_RAD2122_SREV_MAJOR:
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: 5G Radio Chip Rev 0x%02X is not "
 			"supported by this driver\n",
 			 __func__, ah->ah_analog5GhzRev);
@@ -1535,12 +1537,12 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
 	case HAL_M_HOSTAP:
 		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 			  | AR_STA_ID1_KSRCH_MODE);
-		OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 		break;
 	case HAL_M_IBSS:
 		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 			  | AR_STA_ID1_KSRCH_MODE);
-		OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 		break;
 	case HAL_M_STA:
 	case HAL_M_MONITOR:
@@ -1570,7 +1572,7 @@ ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
 	REG_WRITE(ah, AR_PHY_MODE, rfMode);
 }
 
-static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
+static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
 {
 	u_int32_t rst_flags;
 	u_int32_t tmpReg;
@@ -1602,9 +1604,10 @@ static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
 
 	REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), 0);
 	if (!ath9k_hw_wait(ah, (u_int16_t) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC stuck in MAC reset\n",
-			 __func__);
-		return AH_FALSE;
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
+			"%s: RTC stuck in MAC reset\n",
+			__func__);
+		return false;
 	}
 
 	if (!AR_SREV_9100(ah))
@@ -1615,10 +1618,10 @@ static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
 	if (AR_SREV_9100(ah))
 		udelay(50);
 
-	return AH_TRUE;
+	return true;
 }
 
-static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
+static inline bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
 {
 	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
 		  AR_RTC_FORCE_WAKE_ON_INT);
@@ -1630,9 +1633,9 @@ static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
 			   AR_RTC_STATUS,
 			   AR_RTC_STATUS_M,
 			   AR_RTC_STATUS_ON)) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC not waking up\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
 			 __func__);
-		return AH_FALSE;
+		return false;
 	}
 
 	ath9k_hw_read_revisions(ah);
@@ -1640,8 +1643,8 @@ static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
 	return ath9k_hw_set_reset(ah, HAL_RESET_WARM);
 }
 
-static enum hal_bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
-					    u_int32_t type)
+static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
+				   u_int32_t type)
 {
 	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
 		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
@@ -1655,7 +1658,7 @@ static enum hal_bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
 		return ath9k_hw_set_reset(ah, type);
 		break;
 	default:
-		return AH_FALSE;
+		return false;
 	}
 }
 
@@ -1663,7 +1666,7 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
 			struct ath_hal *ah, struct hal_channel *chan)
 {
 	if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u/0x%x; not marked as "
 			 "2GHz or 5GHz\n", __func__, chan->channel,
 			 chan->channelFlags);
@@ -1675,7 +1678,7 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
 	     ^ IS(chan, CHANNEL_HT20)
 	     ^ IS(chan, CHANNEL_HT40PLUS)
 	     ^ IS(chan, CHANNEL_HT40MINUS)) == 0) {
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u/0x%x; not marked as "
 			 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
 			 __func__, chan->channel, chan->channelFlags);
@@ -1685,7 +1688,7 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
 	return ath9k_regd_check_channel(ah, chan);
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_get_lower_upper_index(u_int8_t target,
 			       u_int8_t *pList,
 			       u_int16_t listSize,
@@ -1696,25 +1699,25 @@ ath9k_hw_get_lower_upper_index(u_int8_t target,
 
 	if (target <= pList[0]) {
 		*indexL = *indexR = 0;
-		return AH_TRUE;
+		return true;
 	}
 	if (target >= pList[listSize - 1]) {
 		*indexL = *indexR = (u_int16_t) (listSize - 1);
-		return AH_TRUE;
+		return true;
 	}
 
 	for (i = 0; i < listSize - 1; i++) {
 		if (pList[i] == target) {
 			*indexL = *indexR = i;
-			return AH_TRUE;
+			return true;
 		}
 		if (target < pList[i + 1]) {
 			*indexL = i;
 			*indexR = (u_int16_t) (i + 1);
-			return AH_FALSE;
+			return false;
 		}
 	}
-	return AH_FALSE;
+	return false;
 }
 
 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
@@ -1779,7 +1782,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
 	if (nf & 0x100)
 		nf = 0 - ((nf ^ 0x1ff) + 1);
-	HDPRINTF(ah, HAL_DBG_CALIBRATE,
+	DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 		 "NF calibrated [ctl] [chain 0] is %d\n", nf);
 	nfarray[0] = nf;
 
@@ -1792,7 +1795,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
 	if (nf & 0x100)
 		nf = 0 - ((nf ^ 0x1ff) + 1);
-	HDPRINTF(ah, HAL_DBG_NF_CAL,
+	DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
 		 "NF calibrated [ctl] [chain 1] is %d\n", nf);
 	nfarray[1] = nf;
 
@@ -1801,7 +1804,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 			AR_PHY_CH2_MINCCA_PWR);
 		if (nf & 0x100)
 			nf = 0 - ((nf ^ 0x1ff) + 1);
-		HDPRINTF(ah, HAL_DBG_NF_CAL,
+		DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
 			 "NF calibrated [ctl] [chain 2] is %d\n", nf);
 		nfarray[2] = nf;
 	}
@@ -1815,7 +1818,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
 	if (nf & 0x100)
 		nf = 0 - ((nf ^ 0x1ff) + 1);
-	HDPRINTF(ah, HAL_DBG_NF_CAL,
+	DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
 		 "NF calibrated [ext] [chain 0] is %d\n", nf);
 	nfarray[3] = nf;
 
@@ -1828,7 +1831,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
 	if (nf & 0x100)
 		nf = 0 - ((nf ^ 0x1ff) + 1);
-	HDPRINTF(ah, HAL_DBG_CALIBRATE,
+	DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 		 "NF calibrated [ext] [chain 1] is %d\n", nf);
 	nfarray[4] = nf;
 
@@ -1837,13 +1840,13 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 			AR_PHY_CH2_EXT_MINCCA_PWR);
 		if (nf & 0x100)
 			nf = 0 - ((nf ^ 0x1ff) + 1);
-		HDPRINTF(ah, HAL_DBG_NF_CAL,
+		DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
 			 "NF calibrated [ext] [chain 2] is %d\n", nf);
 		nfarray[5] = nf;
 	}
 }
 
-static enum hal_bool
+static bool
 getNoiseFloorThresh(struct ath_hal *ah,
 		    const struct hal_channel_internal *chan,
 		    int16_t *nft)
@@ -1865,21 +1868,21 @@ getNoiseFloorThresh(struct ath_hal *ah,
 		*nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel flags 0x%x\n", __func__,
 			 chan->channelFlags);
-		return AH_FALSE;
+		return false;
 	}
-	return AH_TRUE;
+	return true;
 }
 
 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
 {
-	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
-		       AR_PHY_AGC_CONTROL_ENABLE_NF);
-	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
-		       AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
-	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
+		    AR_PHY_AGC_CONTROL_ENABLE_NF);
+	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
+		    AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 }
 
 static void
@@ -1918,11 +1921,11 @@ ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
 		}
 	}
 
-	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
-		       AR_PHY_AGC_CONTROL_ENABLE_NF);
-	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
-		       AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
-	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
+		    AR_PHY_AGC_CONTROL_ENABLE_NF);
+	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
+		    AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 
 	for (j = 0; j < 1000; j++) {
 		if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
@@ -1956,7 +1959,7 @@ static int16_t ath9k_hw_getnf(struct ath_hal *ah,
 
 	chan->channelFlags &= (~CHANNEL_CW_INT);
 	if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: NF did not complete in calibration window\n",
 			 __func__);
 		nf = 0;
@@ -1967,7 +1970,7 @@ static int16_t ath9k_hw_getnf(struct ath_hal *ah,
 		nf = nfarray[0];
 		if (getNoiseFloorThresh(ah, chan, &nfThresh)
 		    && nf > nfThresh) {
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "%s: noise floor failed detected; "
 				 "detected %d, threshold %d\n", __func__,
 				 nf, nfThresh);
@@ -2001,7 +2004,7 @@ static void ath9k_enable_mib_counters(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	HDPRINTF(ah, HAL_DBG_ANI, "Enable mib counters\n");
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
 
 	ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
 
@@ -2018,7 +2021,7 @@ static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	HDPRINTF(ah, HAL_DBG_ANI, "Disabling MIB counters\n");
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
 
 	REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
 
@@ -2044,7 +2047,7 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
 		}
 	}
 
-	HDPRINTF(ah, HAL_DBG_ANI,
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 		 "No more channel states left. Using channel 0\n");
 	return 0;
 }
@@ -2078,10 +2081,11 @@ static void ath9k_hw_ani_attach(struct ath_hal *ah)
 		}
 	}
 	if (ahp->ah_hasHwPhyCounters) {
-		HDPRINTF(ah, HAL_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n",
-			 ahp->ah_ani[0].ofdmPhyErrBase);
-		HDPRINTF(ah, HAL_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
-			 ahp->ah_ani[0].cckPhyErrBase);
+		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
+			"Setting OfdmErrBase = 0x%08x\n",
+			ahp->ah_ani[0].ofdmPhyErrBase);
+		DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
+			ahp->ah_ani[0].cckPhyErrBase);
 
 		REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
 		REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
@@ -2114,7 +2118,7 @@ static void ath9k_hw_ani_detach(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	HDPRINTF(ah, HAL_DBG_ANI, "Detaching Ani\n");
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
 	if (ahp->ah_hasHwPhyCounters) {
 		ath9k_hw_disable_mib_counters(ah);
 		REG_WRITE(ah, AR_PHY_ERR_1, 0);
@@ -2123,8 +2127,8 @@ static void ath9k_hw_ani_detach(struct ath_hal *ah)
 }
 
 
-static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
-					  enum hal_ani_cmd cmd, int param)
+static bool ath9k_hw_ani_control(struct ath_hal *ah,
+				 enum hal_ani_cmd cmd, int param)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct ar5416AniState *aniState = ahp->ah_curani;
@@ -2134,26 +2138,26 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
 		u_int level = param;
 
 		if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
-			HDPRINTF(ah, HAL_DBG_ANI,
+			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 				 "%s: level out of range (%u > %u)\n",
 				 __func__, level,
 				 (unsigned) ARRAY_SIZE(ahp->
 						       ah_totalSizeDesired));
-			return AH_FALSE;
-		}
-
-		OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
-				 AR_PHY_DESIRED_SZ_TOT_DES,
-				 ahp->ah_totalSizeDesired[level]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
-				 AR_PHY_AGC_CTL1_COARSE_LOW,
-				 ahp->ah_coarseLow[level]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
-				 AR_PHY_AGC_CTL1_COARSE_HIGH,
-				 ahp->ah_coarseHigh[level]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
-				 AR_PHY_FIND_SIG_FIRPWR,
-				 ahp->ah_firpwr[level]);
+			return false;
+		}
+
+		REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+			      AR_PHY_DESIRED_SZ_TOT_DES,
+			      ahp->ah_totalSizeDesired[level]);
+		REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+			      AR_PHY_AGC_CTL1_COARSE_LOW,
+			      ahp->ah_coarseLow[level]);
+		REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+			      AR_PHY_AGC_CTL1_COARSE_HIGH,
+			      ahp->ah_coarseHigh[level]);
+		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+			      AR_PHY_FIND_SIG_FIRPWR,
+			      ahp->ah_firpwr[level]);
 
 		if (level > aniState->noiseImmunityLevel)
 			ahp->ah_stats.ast_ani_niup++;
@@ -2171,44 +2175,44 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
 		const int m2CountThrLow[] = { 63, 48 };
 		u_int on = param ? 1 : 0;
 
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
-				 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
-				 m1ThreshLow[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
-				 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
-				 m2ThreshLow[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-				 AR_PHY_SFCORR_M1_THRESH,
-				 m1Thresh[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-				 AR_PHY_SFCORR_M2_THRESH,
-				 m2Thresh[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-				 AR_PHY_SFCORR_M2COUNT_THR,
-				 m2CountThr[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
-				 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
-				 m2CountThrLow[on]);
-
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-				 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
-				 m1ThreshLow[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-				 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
-				 m2ThreshLow[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-				 AR_PHY_SFCORR_EXT_M1_THRESH,
-				 m1Thresh[on]);
-		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-				 AR_PHY_SFCORR_EXT_M2_THRESH,
-				 m2Thresh[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			      AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
+			      m1ThreshLow[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			      AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
+			      m2ThreshLow[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			      AR_PHY_SFCORR_M1_THRESH,
+			      m1Thresh[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			      AR_PHY_SFCORR_M2_THRESH,
+			      m2Thresh[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			      AR_PHY_SFCORR_M2COUNT_THR,
+			      m2CountThr[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			      AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
+			      m2CountThrLow[on]);
+
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			      AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
+			      m1ThreshLow[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			      AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
+			      m2ThreshLow[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			      AR_PHY_SFCORR_EXT_M1_THRESH,
+			      m1Thresh[on]);
+		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			      AR_PHY_SFCORR_EXT_M2_THRESH,
+			      m2Thresh[on]);
 
 		if (on)
-			OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
-				       AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+			REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
+				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 		else
-			OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
-				       AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+			REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
+				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
 		if (!on != aniState->ofdmWeakSigDetectOff) {
 			if (on)
@@ -2223,9 +2227,9 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
 		const int weakSigThrCck[] = { 8, 6 };
 		u_int high = param ? 1 : 0;
 
-		OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
-				 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
-				 weakSigThrCck[high]);
+		REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
+			      AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
+			      weakSigThrCck[high]);
 		if (high != aniState->cckWeakSigThreshold) {
 			if (high)
 				ahp->ah_stats.ast_ani_cckhigh++;
@@ -2240,15 +2244,15 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
 		u_int level = param;
 
 		if (level >= ARRAY_SIZE(firstep)) {
-			HDPRINTF(ah, HAL_DBG_ANI,
+			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 				 "%s: level out of range (%u > %u)\n",
 				 __func__, level,
-				 (unsigned) ARRAY_SIZE(firstep));
-			return AH_FALSE;
+				(unsigned) ARRAY_SIZE(firstep));
+			return false;
 		}
-		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
-				 AR_PHY_FIND_SIG_FIRSTEP,
-				 firstep[level]);
+		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+			      AR_PHY_FIND_SIG_FIRSTEP,
+			      firstep[level]);
 		if (level > aniState->firstepLevel)
 			ahp->ah_stats.ast_ani_stepup++;
 		else if (level < aniState->firstepLevel)
@@ -2262,16 +2266,16 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
 		u_int level = param;
 
 		if (level >= ARRAY_SIZE(cycpwrThr1)) {
-			HDPRINTF(ah, HAL_DBG_ANI,
+			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 				 "%s: level out of range (%u > %u)\n",
 				 __func__, level,
 				 (unsigned)
-				 ARRAY_SIZE(cycpwrThr1));
-			return AH_FALSE;
+				ARRAY_SIZE(cycpwrThr1));
+			return false;
 		}
-		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
-				 AR_PHY_TIMING5_CYCPWR_THR1,
-				 cycpwrThr1[level]);
+		REG_RMW_FIELD(ah, AR_PHY_TIMING5,
+			      AR_PHY_TIMING5_CYCPWR_THR1,
+			      cycpwrThr1[level]);
 		if (level > aniState->spurImmunityLevel)
 			ahp->ah_stats.ast_ani_spurup++;
 		else if (level < aniState->spurImmunityLevel)
@@ -2282,27 +2286,27 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
 	case HAL_ANI_PRESENT:
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_ANI, "%s: invalid cmd %u\n", __func__,
-			 cmd);
-		return AH_FALSE;
+		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
+			"%s: invalid cmd %u\n", __func__, cmd);
+		return false;
 	}
 
-	HDPRINTF(ah, HAL_DBG_ANI, "%s: ANI parameters:\n", __func__);
-	HDPRINTF(ah, HAL_DBG_ANI,
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 		"noiseImmunityLevel=%d, spurImmunityLevel=%d, "
 		"ofdmWeakSigDetectOff=%d\n",
 		 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
 		 !aniState->ofdmWeakSigDetectOff);
-	HDPRINTF(ah, HAL_DBG_ANI,
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 		"cckWeakSigThreshold=%d, "
 		"firstepLevel=%d, listenTime=%d\n",
 		 aniState->cckWeakSigThreshold, aniState->firstepLevel,
 		 aniState->listenTime);
-	HDPRINTF(ah, HAL_DBG_ANI,
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 		 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
 		 aniState->cycleCount, aniState->ofdmPhyErrCount,
 		 aniState->cckPhyErrCount);
-	return AH_TRUE;
+	return true;
 }
 
 static void ath9k_ani_restart(struct ath_hal *ah)
@@ -2319,7 +2323,7 @@ static void ath9k_ani_restart(struct ath_hal *ah)
 	if (ahp->ah_hasHwPhyCounters) {
 		if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
 			aniState->ofdmPhyErrBase = 0;
-			HDPRINTF(ah, HAL_DBG_ANI,
+			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 				 "OFDM Trigger is too high for hw counters\n");
 		} else {
 			aniState->ofdmPhyErrBase =
@@ -2327,13 +2331,13 @@ static void ath9k_ani_restart(struct ath_hal *ah)
 		}
 		if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
 			aniState->cckPhyErrBase = 0;
-			HDPRINTF(ah, HAL_DBG_ANI,
+			DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 				 "CCK Trigger is too high for hw counters\n");
 		} else {
 			aniState->cckPhyErrBase =
 				AR_PHY_COUNTMAX - aniState->cckTrigHigh;
 		}
-		HDPRINTF(ah, HAL_DBG_ANI,
+		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 			 "%s: Writing ofdmbase=%u   cckbase=%u\n",
 			 __func__, aniState->ofdmPhyErrBase,
 			 aniState->cckPhyErrBase);
@@ -2363,16 +2367,14 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 
 	if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
 		if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
-					 aniState->noiseImmunityLevel +
-					 1) == AH_TRUE) {
+					 aniState->noiseImmunityLevel + 1)) {
 			return;
 		}
 	}
 
 	if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
 		if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
-					 aniState->spurImmunityLevel +
-					 1) == AH_TRUE) {
+					 aniState->spurImmunityLevel + 1)) {
 			return;
 		}
 	}
@@ -2389,7 +2391,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 		if (!aniState->ofdmWeakSigDetectOff) {
 			if (ath9k_hw_ani_control(ah,
 					 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-					 AH_FALSE) == AH_TRUE) {
+					 false)) {
 				ath9k_hw_ani_control(ah,
 					HAL_ANI_SPUR_IMMUNITY_LEVEL,
 					0);
@@ -2405,7 +2407,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 		if (aniState->ofdmWeakSigDetectOff)
 			ath9k_hw_ani_control(ah,
 					     HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-					     AH_TRUE);
+					     true);
 		if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
 			ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
 					     aniState->firstepLevel + 1);
@@ -2416,7 +2418,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 			if (!aniState->ofdmWeakSigDetectOff)
 				ath9k_hw_ani_control(ah,
 					     HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-					     AH_FALSE);
+					     false);
 			if (aniState->firstepLevel > 0)
 				ath9k_hw_ani_control(ah,
 						     HAL_ANI_FIRSTEP_LEVEL,
@@ -2440,8 +2442,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
 	aniState = ahp->ah_curani;
 	if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
 		if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
-					 aniState->noiseImmunityLevel +
-					 1) == AH_TRUE) {
+					 aniState->noiseImmunityLevel + 1)) {
 			return;
 		}
 	}
@@ -2484,7 +2485,7 @@ static void ath9k_ani_reset(struct ath_hal *ah)
 
 	if (DO_ANI(ah) && ah->ah_opmode != HAL_M_STA
 	    && ah->ah_opmode != HAL_M_IBSS) {
-		HDPRINTF(ah, HAL_DBG_ANI,
+		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 			 "%s: Reset ANI state opmode %u\n", __func__,
 			 ah->ah_opmode);
 		ahp->ah_stats.ast_ani_reset++;
@@ -2551,7 +2552,7 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	u_int32_t phyCnt1, phyCnt2;
 
-	HDPRINTF(ah, HAL_DBG_ANI, "Processing Mib Intr\n");
+	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
 
 	REG_WRITE(ah, AR_FILT_OFDM, 0);
 	REG_WRITE(ah, AR_FILT_CCK, 0);
@@ -2601,8 +2602,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 	if (ah->ah_opmode == HAL_M_HOSTAP) {
 		if (aniState->firstepLevel > 0) {
 			if (ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
-						 aniState->firstepLevel -
-						 1) == AH_TRUE) {
+						 aniState->firstepLevel - 1)) {
 				return;
 			}
 		}
@@ -2614,8 +2614,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 			if (aniState->ofdmWeakSigDetectOff) {
 				if (ath9k_hw_ani_control(ah,
 					 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-					 AH_TRUE) ==
-				    AH_TRUE) {
+					 true) ==
+				    true) {
 					return;
 				}
 			}
@@ -2623,7 +2623,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 				if (ath9k_hw_ani_control
 				    (ah, HAL_ANI_FIRSTEP_LEVEL,
 				     aniState->firstepLevel - 1) ==
-				    AH_TRUE) {
+				    true) {
 					return;
 				}
 			}
@@ -2632,7 +2632,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 				if (ath9k_hw_ani_control
 				    (ah, HAL_ANI_FIRSTEP_LEVEL,
 				     aniState->firstepLevel - 1) ==
-				    AH_TRUE) {
+				    true) {
 					return;
 				}
 			}
@@ -2641,8 +2641,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 
 	if (aniState->spurImmunityLevel > 0) {
 		if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
-					 aniState->spurImmunityLevel -
-					 1) == AH_TRUE) {
+					 aniState->spurImmunityLevel - 1)) {
 			return;
 		}
 	}
@@ -2715,7 +2714,7 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
 		if (phyCnt1 < aniState->ofdmPhyErrBase ||
 		    phyCnt2 < aniState->cckPhyErrBase) {
 			if (phyCnt1 < aniState->ofdmPhyErrBase) {
-				HDPRINTF(ah, HAL_DBG_ANI,
+				DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 					 "%s: phyCnt1 0x%x, resetting "
 					 "counter value to 0x%x\n",
 					 __func__, phyCnt1,
@@ -2726,7 +2725,7 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
 					  AR_PHY_ERR_OFDM_TIMING);
 			}
 			if (phyCnt2 < aniState->cckPhyErrBase) {
-				HDPRINTF(ah, HAL_DBG_ANI,
+				DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 					 "%s: phyCnt2 0x%x, resetting "
 					 "counter value to 0x%x\n",
 					 __func__, phyCnt2,
@@ -2810,8 +2809,8 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
 
 	if (AR_SREV_9280_20_OR_LATER(ah)
 	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
-		OS_REG_RMW(ah, addr, (type << gpio_shift),
-			   (0x1f << gpio_shift));
+		REG_RMW(ah, addr, (type << gpio_shift),
+			(0x1f << gpio_shift));
 	} else {
 		tmp = REG_READ(ah, addr);
 		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
@@ -2821,9 +2820,9 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
 	}
 }
 
-static enum hal_bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
-				  enum hal_gpio_output_mux_type
-				  halSignalType)
+static bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
+				enum hal_gpio_output_mux_type
+				halSignalType)
 {
 	u_int32_t ah_signal_type;
 	u_int32_t gpio_shift;
@@ -2845,26 +2844,26 @@ static enum hal_bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
 	    && (halSignalType < ARRAY_SIZE(MuxSignalConversionTable)))
 		ah_signal_type = MuxSignalConversionTable[halSignalType];
 	else
-		return AH_FALSE;
+		return false;
 
 	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
 
 	gpio_shift = 2 * gpio;
 
-	OS_REG_RMW(ah,
-		   AR_GPIO_OE_OUT,
-		   (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
-		   (AR_GPIO_OE_OUT_DRV << gpio_shift));
+	REG_RMW(ah,
+		AR_GPIO_OE_OUT,
+		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
+		(AR_GPIO_OE_OUT_DRV << gpio_shift));
 
-	return AH_TRUE;
+	return true;
 }
 
-static enum hal_bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
-				u_int32_t val)
+static bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
+			      u_int32_t val)
 {
-	OS_REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
-		   AR_GPIO_BIT(gpio));
-	return AH_TRUE;
+	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
+		AR_GPIO_BIT(gpio));
+	return true;
 }
 
 static u_int32_t ath9k_hw_gpio_get(struct ath_hal *ah, u_int32_t gpio)
@@ -2887,7 +2886,7 @@ static inline enum hal_status ath9k_hw_post_attach(struct ath_hal *ah)
 	enum hal_status ecode;
 
 	if (!ath9k_hw_chip_test(ah)) {
-		HDPRINTF(ah, HAL_DBG_REG_IO,
+		DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 			 "%s: hardware self-test failed\n", __func__);
 		return HAL_ESELFTEST;
 	}
@@ -2919,23 +2918,23 @@ static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
 	switch (ah->ah_devid) {
 	case AR9280_DEVID_PCI:
 		if (reg == 0x7894) {
-			HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+			DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 				 "ini VAL: %x  EEPROM: %x\n", value,
 				 (pBase->version & 0xff));
 
 			if ((pBase->version & 0xff) > 0x0a) {
-				HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+				DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 					 "PWDCLKIND: %d\n",
 					 pBase->pwdclkind);
 				value &= ~AR_AN_TOP2_PWDCLKIND;
 				value |= AR_AN_TOP2_PWDCLKIND & (pBase->
 					 pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
 			} else {
-				HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+				DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 					 "PWDCLKIND Earlier Rev\n");
 			}
 
-			HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+			DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 				 "final ini VAL: %x\n", value);
 		}
 		break;
@@ -2943,7 +2942,7 @@ static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
 	return value;
 }
 
-static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
+static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
@@ -2964,7 +2963,7 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 			ah->ah_currentRD += 5;
 		else if (ah->ah_currentRD == 0x41)
 			ah->ah_currentRD = 0x43;
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 			 "%s: regdomain mapped to 0x%x\n", __func__,
 			 ah->ah_currentRD);
 	}
@@ -3011,22 +3010,22 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 	pCap->halLow5GhzChan = 4920;
 	pCap->halHigh5GhzChan = 6100;
 
-	pCap->halCipherCkipSupport = AH_FALSE;
-	pCap->halCipherTkipSupport = AH_TRUE;
-	pCap->halCipherAesCcmSupport = AH_TRUE;
+	pCap->halCipherCkipSupport = false;
+	pCap->halCipherTkipSupport = true;
+	pCap->halCipherAesCcmSupport = true;
 
-	pCap->halMicCkipSupport = AH_FALSE;
-	pCap->halMicTkipSupport = AH_TRUE;
-	pCap->halMicAesCcmSupport = AH_TRUE;
+	pCap->halMicCkipSupport = false;
+	pCap->halMicTkipSupport = true;
+	pCap->halMicAesCcmSupport = true;
 
-	pCap->halChanSpreadSupport = AH_TRUE;
+	pCap->halChanSpreadSupport = true;
 
 	pCap->halHTSupport =
-		ah->ah_config.ath_hal_htEnable ? AH_TRUE : AH_FALSE;
-	pCap->halGTTSupport = AH_TRUE;
-	pCap->halVEOLSupport = AH_TRUE;
-	pCap->halBssIdMaskSupport = AH_TRUE;
-	pCap->halMcastKeySrchSupport = AH_FALSE;
+		ah->ah_config.ath_hal_htEnable ? true : false;
+	pCap->halGTTSupport = true;
+	pCap->halVEOLSupport = true;
+	pCap->halBssIdMaskSupport = true;
+	pCap->halMcastKeySrchSupport = false;
 
 	if (capField & AR_EEPROM_EEPCAP_MAXQCU)
 		pCap->halTotalQueues =
@@ -3040,7 +3039,7 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 	else
 		pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
 
-	pCap->halFastCCSupport = AH_TRUE;
+	pCap->halFastCCSupport = true;
 	pCap->halNumMRRetries = 4;
 	pCap->halTxTrigLevelMax = MAX_TX_FIFO_THRESHOLD;
 
@@ -3050,21 +3049,21 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 		pCap->halNumGpioPins = AR_NUM_GPIO;
 
 	if (AR_SREV_9280_10_OR_LATER(ah)) {
-		pCap->halWowSupport = AH_TRUE;
-		pCap->halWowMatchPatternExact = AH_TRUE;
+		pCap->halWowSupport = true;
+		pCap->halWowMatchPatternExact = true;
 	} else {
-		pCap->halWowSupport = AH_FALSE;
-		pCap->halWowMatchPatternExact = AH_FALSE;
+		pCap->halWowSupport = false;
+		pCap->halWowMatchPatternExact = false;
 	}
 
 	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
-		pCap->halCSTSupport = AH_TRUE;
+		pCap->halCSTSupport = true;
 		pCap->halRtsAggrLimit = ATH_AMPDU_LIMIT_MAX;
 	} else {
 		pCap->halRtsAggrLimit = (8 * 1024);
 	}
 
-	pCap->halEnhancedPmSupport = AH_TRUE;
+	pCap->halEnhancedPmSupport = true;
 
 	ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
 	if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
@@ -3073,9 +3072,9 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 		ahp->ah_polarity =
 			MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
 
-		ath9k_hw_setcapability(ah, HAL_CAP_RFSILENT, 1, AH_TRUE,
+		ath9k_hw_setcapability(ah, HAL_CAP_RFSILENT, 1, true,
 				       NULL);
-		pCap->halRfSilentSupport = AH_TRUE;
+		pCap->halRfSilentSupport = true;
 	}
 
 	if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
@@ -3083,14 +3082,14 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 	    (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
 	    (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
 	    (ah->ah_macVersion == AR_SREV_VERSION_9280))
-		pCap->halAutoSleepSupport = AH_FALSE;
+		pCap->halAutoSleepSupport = false;
 	else
-		pCap->halAutoSleepSupport = AH_TRUE;
+		pCap->halAutoSleepSupport = true;
 
 	if (AR_SREV_9280(ah))
-		pCap->hal4kbSplitTransSupport = AH_FALSE;
+		pCap->hal4kbSplitTransSupport = false;
 	else
-		pCap->hal4kbSplitTransSupport = AH_TRUE;
+		pCap->hal4kbSplitTransSupport = true;
 
 	if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
 		pCap->halRegCap =
@@ -3111,7 +3110,7 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 	pCap->halNumAntCfg2GHz =
 		ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ);
 
-	return AH_TRUE;
+	return true;
 }
 
 static void ar5416DisablePciePhy(struct ath_hal *ah)
@@ -3134,21 +3133,21 @@ static void ar5416DisablePciePhy(struct ath_hal *ah)
 
 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
 {
-	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
 	if (setChip) {
-		OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
-			       AR_RTC_FORCE_WAKE_EN);
+		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
+			    AR_RTC_FORCE_WAKE_EN);
 		if (!AR_SREV_9100(ah))
 			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
 
-		OS_REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
-			       AR_RTC_RESET_EN);
+		REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
+			    AR_RTC_RESET_EN);
 	}
 }
 
 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
 {
-	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
 	if (setChip) {
 		struct hal_capabilities *pCap = &ah->ah_caps;
 
@@ -3156,14 +3155,14 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
 			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
 				  AR_RTC_FORCE_WAKE_ON_INT);
 		} else {
-			OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
-				       AR_RTC_FORCE_WAKE_EN);
+			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
+				    AR_RTC_FORCE_WAKE_EN);
 		}
 	}
 }
 
-static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
-					      int setChip)
+static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
+				     int setChip)
 {
 	u_int32_t val;
 	int i;
@@ -3172,16 +3171,16 @@ static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
 		if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
 		    AR_RTC_STATUS_SHUTDOWN) {
 			if (ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)
-			    != AH_TRUE) {
-				return AH_FALSE;
+			    != true) {
+				return false;
 			}
 		}
 		if (AR_SREV_9100(ah))
-			OS_REG_SET_BIT(ah, AR_RTC_RESET,
+			REG_SET_BIT(ah, AR_RTC_RESET,
 				       AR_RTC_RESET_EN);
 
-		OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
-			       AR_RTC_FORCE_WAKE_EN);
+		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
+			    AR_RTC_FORCE_WAKE_EN);
 		udelay(50);
 
 		for (i = POWER_UP_TIME / 50; i > 0; i--) {
@@ -3189,23 +3188,23 @@ static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
 			if (val == AR_RTC_STATUS_ON)
 				break;
 			udelay(50);
-			OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
+			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
 				       AR_RTC_FORCE_WAKE_EN);
 		}
 		if (i == 0) {
-			HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+			DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 				 "%s: Failed to wakeup in %uus\n",
 				 __func__, POWER_UP_TIME / 20);
-			return AH_FALSE;
+			return false;
 		}
 	}
 
-	OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
-	return AH_TRUE;
+	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	return true;
 }
 
-enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
-				enum hal_power_mode mode)
+bool ath9k_hw_setpower(struct ath_hal *ah,
+		       enum hal_power_mode mode)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	static const char *modes[] = {
@@ -3214,9 +3213,9 @@ enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
 		"NETWORK SLEEP",
 		"UNDEFINED"
 	};
-	int status = AH_TRUE, setChip = AH_TRUE;
+	int status = true, setChip = true;
 
-	HDPRINTF(ah, HAL_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
+	DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
 		 modes[ahp->ah_powerMode], modes[mode],
 		 setChip ? "set chip " : "");
 
@@ -3226,21 +3225,22 @@ enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
 		break;
 	case HAL_PM_FULL_SLEEP:
 		ath9k_set_power_sleep(ah, setChip);
-		ahp->ah_chipFullSleep = AH_TRUE;
+		ahp->ah_chipFullSleep = true;
 		break;
 	case HAL_PM_NETWORK_SLEEP:
 		ath9k_set_power_network_sleep(ah, setChip);
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+		DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 			 "%s: unknown power mode %u\n", __func__, mode);
-		return AH_FALSE;
+		return false;
 	}
 	ahp->ah_powerMode = mode;
 	return status;
 }
 
-static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
+static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
+					  struct ath_softc *sc,
 					  void __iomem *mem,
 					  enum hal_status *status)
 {
@@ -3261,17 +3261,17 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 	ath9k_hw_set_defaults(ah);
 
 	if (ah->ah_config.ath_hal_intrMitigation != 0)
-		ahp->ah_intrMitigation = AH_TRUE;
+		ahp->ah_intrMitigation = true;
 
 	if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't reset chip\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
 			 __func__);
 		ecode = HAL_EIO;
 		goto bad;
 	}
 
 	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE)) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't wakeup chip\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
 			 __func__);
 		ecode = HAL_EIO;
 		goto bad;
@@ -3286,14 +3286,15 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 				SER_REG_MODE_OFF;
 		}
 	}
-	HDPRINTF(ah, HAL_DBG_RESET, "%s: ath_hal_serializeRegMode is %d\n",
-		 __func__, ah->ah_config.ath_hal_serializeRegMode);
+	DPRINTF(ah->ah_sc, ATH_DBG_RESET,
+		"%s: ath_hal_serializeRegMode is %d\n",
+		__func__, ah->ah_config.ath_hal_serializeRegMode);
 
 	if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 	    (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 	    (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 	    (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
-		HDPRINTF(ah, HAL_DBG_RESET,
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
 			 "this driver\n", __func__,
 			 ah->ah_macVersion, ah->ah_macRev);
@@ -3304,7 +3305,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 	if (AR_SREV_9100(ah)) {
 		ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 		ahp->ah_suppCals = IQ_MISMATCH_CAL;
-		ah->ah_isPciExpress = AH_FALSE;
+		ah->ah_isPciExpress = false;
 	}
 	ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 
@@ -3342,7 +3343,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 		}
 	}
 
-	HDPRINTF(ah, HAL_DBG_RESET,
+	DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 		 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
 		 ah->ah_macVersion, ah->ah_macRev);
 
@@ -3477,7 +3478,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 #endif
 
 	if (!ath9k_hw_fill_cap_info(ah)) {
-		HDPRINTF(ah, HAL_DBG_RESET,
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
 		ecode = HAL_EEREAD;
 		goto bad;
@@ -3485,7 +3486,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 
 	ecode = ath9k_hw_init_macaddr(ah);
 	if (ecode != HAL_OK) {
-		HDPRINTF(ah, HAL_DBG_RESET,
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			 "%s: failed initializing mac address\n",
 			 __func__);
 		goto bad;
@@ -3521,33 +3522,33 @@ void ath9k_hw_detach(struct ath_hal *ah)
 	kfree(ah);
 }
 
-enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
-				      u_int16_t flags, u_int16_t *low,
-				      u_int16_t *high)
+bool ath9k_get_channel_edges(struct ath_hal *ah,
+			     u_int16_t flags, u_int16_t *low,
+			     u_int16_t *high)
 {
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
 	if (flags & CHANNEL_5GHZ) {
 		*low = pCap->halLow5GhzChan;
 		*high = pCap->halHigh5GhzChan;
-		return AH_TRUE;
+		return true;
 	}
 	if ((flags & CHANNEL_2GHZ)) {
 		*low = pCap->halLow2GhzChan;
 		*high = pCap->halHigh2GhzChan;
 
-		return AH_TRUE;
+		return true;
 	}
-	return AH_FALSE;
+	return false;
 }
 
-static inline enum hal_bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
-						    u_int8_t pwrMax,
-						    u_int8_t *pPwrList,
-						    u_int8_t *pVpdList,
-						    u_int16_t
-						    numIntercepts,
-						    u_int8_t *pRetVpdList)
+static inline bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
+					   u_int8_t pwrMax,
+					   u_int8_t *pPwrList,
+					   u_int8_t *pVpdList,
+					   u_int16_t
+					   numIntercepts,
+					   u_int8_t *pRetVpdList)
 {
 	u_int16_t i, k;
 	u_int8_t currPwr = pwrMin;
@@ -3575,7 +3576,7 @@ static inline enum hal_bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
 		currPwr += 2;
 	}
 
-	return AH_TRUE;
+	return true;
 }
 
 static inline void
@@ -3606,7 +3607,7 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 	int16_t vpdStep;
 	int16_t tmpVal;
 	u_int16_t sizeCurrVpdTable, maxIndex, tgtIndex;
-	enum hal_bool match;
+	bool match;
 	int16_t minDelta = 0;
 	struct chan_centers centers;
 
@@ -3760,7 +3761,7 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
 	return;
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 			     struct ar5416_eeprom *pEepData,
 			     struct hal_channel_internal *chan,
@@ -3814,14 +3815,14 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 		}
 	}
 
-	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
-			 (numXpdGain - 1) & 0x3);
-	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
-			 xpdGainValues[0]);
-	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
-			 xpdGainValues[1]);
-	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
-			 xpdGainValues[2]);
+	REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
+		      (numXpdGain - 1) & 0x3);
+	REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
+		      xpdGainValues[0]);
+	REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
+		      xpdGainValues[1]);
+	REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
+		      xpdGainValues[2]);
 
 	for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 		if (AR_SREV_5416_V20_OR_LATER(ah) &&
@@ -3874,11 +3875,11 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 					 24);
 				REG_WRITE(ah, regOffset, reg32);
 
-				HDPRINTF(ah, HAL_DBG_PHY_IO,
+				DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 					 "PDADC (%d,%4x): %4.4x %8.8x\n",
 					 i, regChainOffset, regOffset,
 					 reg32);
-				HDPRINTF(ah, HAL_DBG_PHY_IO,
+				DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 				"PDADC: Chain %d | PDADC %3d Value %3d | "
 				"PDADC %3d Value %3d | PDADC %3d Value %3d | "
 				"PDADC %3d Value %3d |\n",
@@ -3894,7 +3895,7 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
 	}
 	*pTxPowerIndexOffset = 0;
 
-	return AH_TRUE;
+	return true;
 }
 
 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
@@ -3902,7 +3903,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	u_int8_t i;
 
-	if (ah->ah_isPciExpress != AH_TRUE)
+	if (ah->ah_isPciExpress != true)
 		return;
 
 	if (ah->ah_config.ath_hal_pciePowerSaveEnable == 2)
@@ -3951,7 +3952,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
 		REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 	}
 
-	OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+	REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 
 	if (ah->ah_config.ath_hal_pcieWaen) {
 		REG_WRITE(ah, AR_WA, ah->ah_config.ath_hal_pcieWaen);
@@ -3970,7 +3971,7 @@ ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
 				  u_int16_t numChannels,
 				  struct cal_target_power_leg *pNewPower,
 				  u_int16_t numRates,
-				  enum hal_bool isExtTarget)
+				  bool isExtTarget)
 {
 	u_int16_t clo, chi;
 	int i;
@@ -4036,7 +4037,7 @@ ath9k_hw_get_target_powers(struct ath_hal *ah,
 			   u_int16_t numChannels,
 			   struct cal_target_power_ht *pNewPower,
 			   u_int16_t numRates,
-			   enum hal_bool isHt40Target)
+			   bool isHt40Target)
 {
 	u_int16_t clo, chi;
 	int i;
@@ -4099,7 +4100,7 @@ ath9k_hw_get_target_powers(struct ath_hal *ah,
 static inline u_int16_t
 ath9k_hw_get_max_edge_power(u_int16_t freq,
 			    struct cal_ctl_edges *pRdEdgesPower,
-			    enum hal_bool is2GHz)
+			    bool is2GHz)
 {
 	u_int16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 	int i;
@@ -4126,7 +4127,7 @@ ath9k_hw_get_max_edge_power(u_int16_t freq,
 	return twiceMaxEdgePower;
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 				  struct ar5416_eeprom *pEepData,
 				  struct hal_channel_internal *chan,
@@ -4220,17 +4221,17 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 			calTargetPowerCck,
 			AR5416_NUM_2G_CCK_TARGET_POWERS,
 			&targetPowerCck, 4,
-			AH_FALSE);
+			false);
 		ath9k_hw_get_legacy_target_powers(ah, chan,
 			pEepData->
 			calTargetPower2G,
 			AR5416_NUM_2G_20_TARGET_POWERS,
 			&targetPowerOfdm, 4,
-			AH_FALSE);
+			false);
 		ath9k_hw_get_target_powers(ah, chan,
 			pEepData->calTargetPower2GHT20,
 			AR5416_NUM_2G_20_TARGET_POWERS,
-			&targetPowerHt20, 8, AH_FALSE);
+			&targetPowerHt20, 8, false);
 
 		if (IS_CHAN_HT40(chan)) {
 			numCtlModes = ARRAY_SIZE(ctlModesFor11g);
@@ -4239,19 +4240,19 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 				calTargetPower2GHT40,
 				AR5416_NUM_2G_40_TARGET_POWERS,
 				&targetPowerHt40, 8,
-				AH_TRUE);
+				true);
 			ath9k_hw_get_legacy_target_powers(ah, chan,
 				pEepData->
 				calTargetPowerCck,
 				AR5416_NUM_2G_CCK_TARGET_POWERS,
 				&targetPowerCckExt,
-				4, AH_TRUE);
+				4, true);
 			ath9k_hw_get_legacy_target_powers(ah, chan,
 				pEepData->
 				calTargetPower2G,
 				AR5416_NUM_2G_20_TARGET_POWERS,
 				&targetPowerOfdmExt,
-				4, AH_TRUE);
+				4, true);
 		}
 	} else {
 
@@ -4265,11 +4266,11 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 			calTargetPower5G,
 			AR5416_NUM_5G_20_TARGET_POWERS,
 			&targetPowerOfdm, 4,
-			AH_FALSE);
+			false);
 		ath9k_hw_get_target_powers(ah, chan,
 			pEepData->calTargetPower5GHT20,
 			AR5416_NUM_5G_20_TARGET_POWERS,
-			&targetPowerHt20, 8, AH_FALSE);
+			&targetPowerHt20, 8, false);
 
 		if (IS_CHAN_HT40(chan)) {
 			numCtlModes = ARRAY_SIZE(ctlModesFor11a);
@@ -4278,18 +4279,18 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 				calTargetPower5GHT40,
 				AR5416_NUM_5G_40_TARGET_POWERS,
 				&targetPowerHt40, 8,
-				AH_TRUE);
+				true);
 			ath9k_hw_get_legacy_target_powers(ah, chan,
 				pEepData->
 				calTargetPower5G,
 				AR5416_NUM_5G_20_TARGET_POWERS,
 				&targetPowerOfdmExt,
-				4, AH_TRUE);
+				4, true);
 		}
 	}
 
 	for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
-		enum hal_bool isHt40CtlMode =
+		bool isHt40CtlMode =
 			(pCtlMode[ctlMode] == CTL_5GHT40)
 			|| (pCtlMode[ctlMode] == CTL_2GHT40);
 		if (isHt40CtlMode)
@@ -4303,7 +4304,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 		    && ar5416_get_eep_rev(ahp) <= 2)
 			twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 
-		HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+		DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 			"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
 			"EXT_ADDITIVE %d\n",
 			 ctlMode, numCtlModes, isHt40CtlMode,
@@ -4311,7 +4312,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 
 		for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
 		     i++) {
-			HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+			DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 				 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
 				"pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
 				"chan %d chanctl 0x%x\n",
@@ -4339,7 +4340,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 						IS_CHAN_2GHZ
 						(chan));
 
-				HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+				DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 					"    MATCH-EE_IDX %d: ch %d is2 %d "
 					"2xMinEdge %d chainmask %d chains %d\n",
 					 i, freq, IS_CHAN_2GHZ(chan),
@@ -4360,7 +4361,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 
 		minCtlPower = min(twiceMaxEdgePower, scaledPower);
 
-		HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+		DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 				"    SEL-Min ctlMode %d pCtlMode %d "
 				"2xMaxEdge %d sP %d minCtlPwr %d\n",
 			 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
@@ -4451,7 +4452,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 				targetPowerCckExt.tPow2x[0];
 		}
 	}
-	return AH_TRUE;
+	return true;
 }
 
 static enum hal_status
@@ -4483,7 +4484,7 @@ ath9k_hw_set_txpower(struct ath_hal *ah,
 					       twiceAntennaReduction,
 					       twiceMaxRegulatoryPower,
 					       powerLimit)) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			"ath9k_hw_set_txpower: unable to set "
 			"tx power per rate table\n");
 		return HAL_EIO;
@@ -4491,7 +4492,7 @@ ath9k_hw_set_txpower(struct ath_hal *ah,
 
 	if (!ath9k_hw_set_power_cal_table
 	    (ah, pEepData, chan, &txPowerIndexOffset)) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "ath9k_hw_set_txpower: unable to set power table\n");
 		return HAL_EIO;
 	}
@@ -4637,20 +4638,20 @@ ath9k_hw_set_delta_slope(struct ath_hal *ah,
 	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 				      &ds_coef_exp);
 
-	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
-			 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
-	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
-			 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
+	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+		      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
+	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+		      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 
 	coef_scaled = (9 * coef_scaled) / 10;
 
 	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 				      &ds_coef_exp);
 
-	OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
-			 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
-	OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
-			 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
+	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
+		      AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
+	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
+		      AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
 }
 
 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
@@ -4681,7 +4682,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
 	int8_t mask_amt;
 	int tmp_mask;
 	int cur_bb_spur;
-	enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
+	bool is2GHz = IS_CHAN_2GHZ(chan);
 
 	memset(&mask_m, 0, sizeof(int8_t) * 123);
 	memset(&mask_p, 0, sizeof(int8_t) * 123);
@@ -4716,12 +4717,12 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
 	}
 
 	if (AR_NO_SPUR == bb_spur) {
-		OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
-			       AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
+			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
 		return;
 	} else {
-		OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
-			       AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
+			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
 	}
 
 	bin = bb_spur * 320;
@@ -4925,7 +4926,7 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
 	int8_t mask_amt;
 	int tmp_mask;
 	int cur_bb_spur;
-	enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
+	bool is2GHz = IS_CHAN_2GHZ(chan);
 
 	memset(&mask_m, 0, sizeof(int8_t) * 123);
 	memset(&mask_p, 0, sizeof(int8_t) * 123);
@@ -5109,8 +5110,8 @@ static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
 
 	switch (rx_chainmask) {
 	case 0x5:
-		OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
-			       AR_PHY_SWAP_ALT_CHAIN);
+		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
+			    AR_PHY_SWAP_ALT_CHAIN);
 	case 0x3:
 		if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
 			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
@@ -5131,8 +5132,8 @@ static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
 
 	REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
 	if (tx_chainmask == 0x5) {
-		OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
-			       AR_PHY_SWAP_ALT_CHAIN);
+		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
+			    AR_PHY_SWAP_ALT_CHAIN);
 	}
 	if (AR_SREV_9100(ah))
 		REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
@@ -5241,69 +5242,69 @@ static u_int ath9k_hw_mac_to_clks(struct ath_hal *ah, u_int usecs)
 		return ath9k_hw_mac_clks(ah, usecs);
 }
 
-static enum hal_bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: bad ack timeout %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
 			 __func__, us);
 		ahp->ah_acktimeout = (u_int) -1;
-		return AH_FALSE;
+		return false;
 	} else {
-		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
-				 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
+		REG_RMW_FIELD(ah, AR_TIME_OUT,
+			      AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
 		ahp->ah_acktimeout = us;
-		return AH_TRUE;
+		return true;
 	}
 }
 
-static enum hal_bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: bad cts timeout %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
 			 __func__, us);
 		ahp->ah_ctstimeout = (u_int) -1;
-		return AH_FALSE;
+		return false;
 	} else {
-		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
-				 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
+		REG_RMW_FIELD(ah, AR_TIME_OUT,
+			      AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
 		ahp->ah_ctstimeout = us;
-		return AH_TRUE;
+		return true;
 	}
 }
-static enum hal_bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
-						   u_int tu)
+static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
+					  u_int tu)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (tu > 0xFFFF) {
-		HDPRINTF(ah, HAL_DBG_TX, "%s: bad global tx timeout %u\n",
-			 __func__, tu);
+		DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
+			"%s: bad global tx timeout %u\n", __func__, tu);
 		ahp->ah_globaltxtimeout = (u_int) -1;
-		return AH_FALSE;
+		return false;
 	} else {
-		OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
+		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 		ahp->ah_globaltxtimeout = tu;
-		return AH_TRUE;
+		return true;
 	}
 }
 
-enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
+bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (us < HAL_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: bad slot time %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
 			 __func__, us);
 		ahp->ah_slottime = (u_int) -1;
-		return AH_FALSE;
+		return false;
 	} else {
 		REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
 		ahp->ah_slottime = us;
-		return AH_TRUE;
+		return true;
 	}
 }
 
@@ -5311,7 +5312,7 @@ static inline void ath9k_hw_init_user_settings(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	HDPRINTF(ah, HAL_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
+	DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
 		 __func__, ahp->ah_miscMode);
 	if (ahp->ah_miscMode != 0)
 		REG_WRITE(ah, AR_PCU_MISC,
@@ -5444,13 +5445,13 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 				      min((u_int32_t) MAX_RATE_POWER,
 					  (u_int32_t) ah->ah_powerLimit));
 	if (status != HAL_OK) {
-		HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+		DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 			 "%s: error init'ing transmit power\n", __func__);
 		return HAL_EIO;
 	}
 
 	if (!ath9k_hw_set_rf_regs(ah, ichan, freqIndex)) {
-		HDPRINTF(ah, HAL_DBG_REG_IO,
+		DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 			 "%s: ar5416SetRfRegs failed\n", __func__);
 		return HAL_EIO;
 	}
@@ -5461,37 +5462,37 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,
 					      struct hal_cal_list *currCal)
 {
-	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
-			 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
-			 currCal->calData->calCountMax);
+	REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
+		      AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
+		      currCal->calData->calCountMax);
 
 	switch (currCal->calData->calType) {
 	case IQ_MISMATCH_CAL:
 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: starting IQ Mismatch Calibration\n",
 			 __func__);
 		break;
 	case ADC_GAIN_CAL:
 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: starting ADC Gain Calibration\n", __func__);
 		break;
 	case ADC_DC_CAL:
 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: starting ADC DC Calibration\n", __func__);
 		break;
 	case ADC_DC_INIT_CAL:
 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: starting Init ADC DC Calibration\n",
 			 __func__);
 		break;
 	}
 
-	OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
-		       AR_PHY_TIMING_CTRL4_DO_CAL);
+	REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
+		    AR_PHY_TIMING_CTRL4_DO_CAL);
 }
 
 static inline void ath9k_hw_reset_calibration(struct ath_hal *ah,
@@ -5519,11 +5520,11 @@ ath9k_hw_per_calibration(struct ath_hal *ah,
 			 struct hal_channel_internal *ichan,
 			 u_int8_t rxchainmask,
 			 struct hal_cal_list *currCal,
-			 enum hal_bool *isCalDone)
+			 bool *isCalDone)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	*isCalDone = AH_FALSE;
+	*isCalDone = false;
 
 	if (currCal->calState == CAL_RUNNING) {
 		if (!(REG_READ(ah,
@@ -5548,7 +5549,7 @@ ath9k_hw_per_calibration(struct ath_hal *ah,
 				ichan->CalValid |=
 					currCal->calData->calType;
 				currCal->calState = CAL_DONE;
-				*isCalDone = AH_TRUE;
+				*isCalDone = true;
 			} else {
 				ath9k_hw_setup_calibration(ah, currCal);
 			}
@@ -5558,18 +5559,18 @@ ath9k_hw_per_calibration(struct ath_hal *ah,
 	}
 }
 
-static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
-						   int init_cal_count)
+static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
+					  int init_cal_count)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_channel_internal ichan;
-	enum hal_bool isCalDone;
+	bool isCalDone;
 	struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
 	const struct hal_percal_data *calData = currCal->calData;
 	int i;
 
 	if (currCal == NULL)
-		return AH_FALSE;
+		return false;
 
 	ichan.CalValid = 0;
 
@@ -5578,19 +5579,19 @@ static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
 
 		if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
 				   AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "%s: Cal %d failed to complete in 100ms.\n",
 				 __func__, calData->calType);
 
 			ahp->ah_cal_list = ahp->ah_cal_list_last =
 				ahp->ah_cal_list_curr = NULL;
-			return AH_FALSE;
+			return false;
 		}
 
 		ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
 					 currCal, &isCalDone);
-		if (isCalDone == AH_FALSE) {
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		if (!isCalDone) {
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "%s: Not able to run Init Cal %d.\n",
 				 __func__, calData->calType);
 		}
@@ -5601,10 +5602,10 @@ static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
 	}
 
 	ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
-	return AH_TRUE;
+	return true;
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_channel_change(struct ath_hal *ah,
 			struct hal_channel *chan,
 			struct hal_channel_internal *ichan,
@@ -5615,34 +5616,34 @@ ath9k_hw_channel_change(struct ath_hal *ah,
 
 	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
 		if (ath9k_hw_numtxpending(ah, qnum)) {
-			HDPRINTF(ah, HAL_DBG_QUEUE,
+			DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
 				 "%s: Transmit frames pending on queue %d\n",
 				 __func__, qnum);
-			return AH_FALSE;
+			return false;
 		}
 	}
 
 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 	if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 			   AR_PHY_RFBUS_GRANT_EN)) {
-		HDPRINTF(ah, HAL_DBG_PHY_IO,
+		DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 			 "%s: Could not kill baseband RX\n", __func__);
-		return AH_FALSE;
+		return false;
 	}
 
 	ath9k_hw_set_regs(ah, chan, macmode);
 
 	if (AR_SREV_9280_10_OR_LATER(ah)) {
 		if (!(ath9k_hw_ar9280_set_channel(ah, ichan))) {
-			HDPRINTF(ah, HAL_DBG_CHANNEL,
+			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 				 "%s: failed to set channel\n", __func__);
-			return AH_FALSE;
+			return false;
 		}
 	} else {
 		if (!(ath9k_hw_set_channel(ah, ichan))) {
-			HDPRINTF(ah, HAL_DBG_CHANNEL,
+			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 				 "%s: failed to set channel\n", __func__);
-			return AH_FALSE;
+			return false;
 		}
 	}
 
@@ -5653,9 +5654,9 @@ ath9k_hw_channel_change(struct ath_hal *ah,
 				 min((u_int32_t) MAX_RATE_POWER,
 				     (u_int32_t) ah->ah_powerLimit))
 	    != HAL_OK) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: error init'ing transmit power\n", __func__);
-		return AH_FALSE;
+		return false;
 	}
 
 	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
@@ -5677,29 +5678,29 @@ ath9k_hw_channel_change(struct ath_hal *ah,
 		ath9k_hw_spur_mitigate(ah, chan);
 
 	if (!ichan->oneTimeCalsDone)
-		ichan->oneTimeCalsDone = AH_TRUE;
+		ichan->oneTimeCalsDone = true;
 
-	return AH_TRUE;
+	return true;
 }
 
-static enum hal_bool ath9k_hw_chip_reset(struct ath_hal *ah,
-					 struct hal_channel *chan)
+static bool ath9k_hw_chip_reset(struct ath_hal *ah,
+				struct hal_channel *chan)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM))
-		return AH_FALSE;
+		return false;
 
 	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
-		return AH_FALSE;
+		return false;
 
-	ahp->ah_chipFullSleep = AH_FALSE;
+	ahp->ah_chipFullSleep = false;
 
 	ath9k_hw_init_pll(ah, chan);
 
 	ath9k_hw_set_rfmode(ah, chan);
 
-	return AH_TRUE;
+	return true;
 }
 
 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
@@ -5712,7 +5713,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
 	regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 	REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 
-	OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
+	REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
 
 	regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 	REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
@@ -5728,24 +5729,25 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
 	}
 }
 
-enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
+bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
 {
 	REG_WRITE(ah, AR_CR, AR_CR_RXD);
 	if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
-		HDPRINTF(ah, HAL_DBG_RX, "%s: dma failed to stop in 10ms\n"
-			 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
-			 __func__,
-			 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
-		return AH_FALSE;
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
+			"%s: dma failed to stop in 10ms\n"
+			"AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
+			__func__,
+			REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
+		return false;
 	} else {
-		return AH_TRUE;
+		return true;
 	}
 }
 
 void ath9k_hw_startpcureceive(struct ath_hal *ah)
 {
-	OS_REG_CLR_BIT(ah, AR_DIAG_SW,
-		       (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
+	REG_CLR_BIT(ah, AR_DIAG_SW,
+		    (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 
 	ath9k_enable_mib_counters(ah);
 
@@ -5754,36 +5756,36 @@ void ath9k_hw_startpcureceive(struct ath_hal *ah)
 
 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
 {
-	OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
+	REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
 
 	ath9k_hw_disable_mib_counters(ah);
 }
 
-static enum hal_bool ath9k_hw_iscal_supported(struct ath_hal *ah,
-					      struct hal_channel *chan,
-					      enum hal_cal_types calType)
+static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
+				     struct hal_channel *chan,
+				     enum hal_cal_types calType)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
-	enum hal_bool retval = AH_FALSE;
+	bool retval = false;
 
 	switch (calType & ahp->ah_suppCals) {
 	case IQ_MISMATCH_CAL:
 		if (!IS_CHAN_B(chan))
-			retval = AH_TRUE;
+			retval = true;
 		break;
 	case ADC_GAIN_CAL:
 	case ADC_DC_CAL:
 		if (!IS_CHAN_B(chan)
 		    && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
-			retval = AH_TRUE;
+			retval = true;
 		break;
 	}
 
 	return retval;
 }
 
-static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
-					      struct hal_channel *chan)
+static inline bool ath9k_hw_init_cal(struct ath_hal *ah,
+				     struct hal_channel *chan)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_channel_internal *ichan =
@@ -5795,10 +5797,10 @@ static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
 
 	if (!ath9k_hw_wait
 	    (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: offset calibration failed to complete in 1ms; "
 			 "noisy environment?\n", __func__);
-		return AH_FALSE;
+		return false;
 	}
 
 	REG_WRITE(ah, AR_PHY_AGC_CONTROL,
@@ -5809,27 +5811,24 @@ static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
 		NULL;
 
 	if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
-		if (AH_TRUE ==
-		    ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
+		if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
 			INIT_CAL(&ahp->ah_adcGainCalData);
 			INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "%s: enabling ADC Gain Calibration.\n",
 				 __func__);
 		}
-		if (AH_TRUE ==
-		    ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
+		if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
 			INIT_CAL(&ahp->ah_adcDcCalData);
 			INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "%s: enabling ADC DC Calibration.\n",
 				 __func__);
 		}
-		if (AH_TRUE ==
-		    ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
+		if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
 			INIT_CAL(&ahp->ah_iqCalData);
 			INSERT_CAL(ahp, &ahp->ah_iqCalData);
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "%s: enabling IQ Calibration.\n",
 				 __func__);
 		}
@@ -5843,17 +5842,17 @@ static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
 
 	ichan->CalValid = 0;
 
-	return AH_TRUE;
+	return true;
 }
 
 
-enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
-			     struct hal_channel *chan,
-			     enum hal_ht_macmode macmode,
-			     u_int8_t txchainmask, u_int8_t rxchainmask,
-			     enum hal_ht_extprotspacing extprotspacing,
-			     enum hal_bool bChannelChange,
-			     enum hal_status *status)
+bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
+		    struct hal_channel *chan,
+		    enum hal_ht_macmode macmode,
+		    u_int8_t txchainmask, u_int8_t rxchainmask,
+		    enum hal_ht_extprotspacing extprotspacing,
+		    bool bChannelChange,
+		    enum hal_status *status)
 {
 #define FAIL(_code)     do { ecode = _code; goto bad; } while (0)
 	u_int32_t saveLedState;
@@ -5876,20 +5875,20 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 
 	ichan = ath9k_hw_check_chan(ah, chan);
 	if (ichan == NULL) {
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u/0x%x; no mapping\n",
 			 __func__, chan->channel, chan->channelFlags);
 		FAIL(HAL_EINVAL);
 	}
 
 	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
-		return AH_FALSE;
+		return false;
 
 	if (curchan)
 		ath9k_hw_getnf(ah, curchan);
 
 	if (bChannelChange &&
-	    (ahp->ah_chipFullSleep != AH_TRUE) &&
+	    (ahp->ah_chipFullSleep != true) &&
 	    (ah->ah_curchan != NULL) &&
 	    (chan->channel != ah->ah_curchan->channel) &&
 	    ((chan->channelFlags & CHANNEL_ALL) ==
@@ -5906,7 +5905,7 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 
 			ath9k_hw_start_nfcal(ah);
 
-			return AH_TRUE;
+			return true;
 		}
 	}
 
@@ -5923,14 +5922,14 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 	ath9k_hw_mark_phy_inactive(ah);
 
 	if (!ath9k_hw_chip_reset(ah, chan)) {
-		HDPRINTF(ah, HAL_DBG_RESET, "%s: chip reset failed\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
 			 __func__);
 		FAIL(HAL_EIO);
 	}
 
 	if (AR_SREV_9280(ah)) {
-		OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-			       AR_GPIO_JTAG_DISABLE);
+		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
+			    AR_GPIO_JTAG_DISABLE);
 
 		if (ah->ah_caps.halWirelessModes & ATH9K_MODE_SEL_11A) {
 			if (IS_CHAN_5GHZ(chan))
@@ -5954,7 +5953,7 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 		ath9k_hw_spur_mitigate(ah, chan);
 
 	if (!ath9k_hw_eeprom_set_board_values(ah, ichan)) {
-		HDPRINTF(ah, HAL_DBG_EEPROM,
+		DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 			 "%s: error setting board options\n", __func__);
 		FAIL(HAL_EIO);
 	}
@@ -6014,8 +6013,8 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 
 	if (ahp->ah_intrMitigation) {
 
-		OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
-		OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
+		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
+		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
 	}
 
 	ath9k_hw_init_bb(ah, chan);
@@ -6035,14 +6034,14 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 		u_int32_t mask;
 		mask = REG_READ(ah, AR_CFG);
 		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
-			HDPRINTF(ah, HAL_DBG_RESET,
+			DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 				 "%s CFG Byte Swap Set 0x%x\n", __func__,
 				 mask);
 		} else {
 			mask =
 				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
 			REG_WRITE(ah, AR_CFG, mask);
-			HDPRINTF(ah, HAL_DBG_RESET,
+			DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 				 "%s Setting CFG 0x%x\n", __func__,
 				 REG_READ(ah, AR_CFG));
 		}
@@ -6053,44 +6052,44 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 	}
 	chan->channelFlags = ichan->channelFlags;
 	chan->privFlags = ichan->privFlags;
-	return AH_TRUE;
+	return true;
 bad:
 	if (status)
 		*status = ecode;
-	return AH_FALSE;
+	return false;
 #undef FAIL
 }
 
-enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah)
+bool ath9k_hw_phy_disable(struct ath_hal *ah)
 {
 	return ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM);
 }
 
-enum hal_bool ath9k_hw_disable(struct ath_hal *ah)
+bool ath9k_hw_disable(struct ath_hal *ah)
 {
 	if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
-		return AH_FALSE;
+		return false;
 
 	return ath9k_hw_set_reset_reg(ah, HAL_RESET_COLD);
 }
 
-enum hal_bool
+bool
 ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
-		   u_int8_t rxchainmask, enum hal_bool longcal,
-		   enum hal_bool *isCalDone)
+		   u_int8_t rxchainmask, bool longcal,
+		   bool *isCalDone)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
 	struct hal_channel_internal *ichan =
 		ath9k_regd_check_channel(ah, chan);
 
-	*isCalDone = AH_TRUE;
+	*isCalDone = true;
 
 	if (ichan == NULL) {
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u/0x%x; no mapping\n",
 			 __func__, chan->channel, chan->channelFlags);
-		return AH_FALSE;
+		return false;
 	}
 
 	if (currCal &&
@@ -6098,11 +6097,11 @@ ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
 	     currCal->calState == CAL_WAITING)) {
 		ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
 					 isCalDone);
-		if (*isCalDone == AH_TRUE) {
+		if (*isCalDone) {
 			ahp->ah_cal_list_curr = currCal = currCal->calNext;
 
 			if (currCal->calState == CAL_WAITING) {
-				*isCalDone = AH_FALSE;
+				*isCalDone = false;
 				ath9k_hw_reset_calibration(ah, currCal);
 			}
 		}
@@ -6120,7 +6119,7 @@ ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
 		}
 	}
 
-	return AH_TRUE;
+	return true;
 }
 
 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
@@ -6135,7 +6134,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
 			REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 		ahp->ah_totalIqCorrMeas[i] +=
 			(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
 			 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
 			 ahp->ah_totalPowerMeasQ[i],
@@ -6158,7 +6157,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
 		ahp->ah_totalAdcQEvenPhase[i] +=
 			REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 			"oddq=0x%08x; evenq=0x%08x;\n",
 			 ahp->ah_CalSamples, i,
@@ -6184,7 +6183,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
 		ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
 			(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 			"oddq=0x%08x; evenq=0x%08x;\n",
 			 ahp->ah_CalSamples, i,
@@ -6208,11 +6207,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
 		powerMeasQ = ahp->ah_totalPowerMeasQ[i];
 		iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Starting IQ Cal and Correction for Chain %d\n",
 			 i);
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
 			 i, ahp->ah_totalIqCorrMeas[i]);
 
@@ -6224,11 +6223,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
 			iqCorrNeg = 1;
 		}
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
 			 iqCorrNeg);
 
 		iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
@@ -6238,14 +6237,14 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
 
 			iCoff = iqCorrMeas / iCoffDenom;
 			qCoff = powerMeasI / qCoffDenom - 64;
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "Chn %d iCoff = 0x%08x\n", i, iCoff);
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
 
 			iCoff = iCoff & 0x3f;
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
 			if (iqCorrNeg == 0x0)
 				iCoff = 0x40 - iCoff;
@@ -6255,24 +6254,24 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
 			else if (qCoff <= -16)
 				qCoff = 16;
 
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-				 i, iCoff, qCoff);
+				i, iCoff, qCoff);
 
-			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
-					 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
-					 iCoff);
-			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
-					 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
-					 qCoff);
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
-				 "IQ Cal and Correction done for Chain %d\n",
-				 i);
+			REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
+				      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
+				      iCoff);
+			REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
+				      AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
+				      qCoff);
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+				"IQ Cal and Correction done for Chain %d\n",
+				i);
 		}
 	}
 
-	OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
-		       AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
+	REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
+		    AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
 }
 
 static void
@@ -6289,19 +6288,19 @@ ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 		qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
 		qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Starting ADC Gain Cal for Chain %d\n", i);
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
 			 iOddMeasOffset);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
 			 iEvenMeasOffset);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
 			 qOddMeasOffset);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
 			 qEvenMeasOffset);
 
@@ -6313,10 +6312,10 @@ ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 				((qOddMeasOffset * 32) /
 				 qEvenMeasOffset) & 0x3f;
 
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "Chn %d gain_mismatch_i = 0x%08x\n", i,
 				 iGainMismatch);
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "Chn %d gain_mismatch_q = 0x%08x\n", i,
 				 qGainMismatch);
 
@@ -6325,7 +6324,7 @@ ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 			val |= (qGainMismatch) | (iGainMismatch << 6);
 			REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-			HDPRINTF(ah, HAL_DBG_CALIBRATE,
+			DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 				 "ADC Gain Cal done for Chain %d\n", i);
 		}
 	}
@@ -6352,19 +6351,19 @@ ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 		qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
 		qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Starting ADC DC Offset Cal for Chain %d\n", i);
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_odd_i = %d\n", i,
 			 iOddMeasOffset);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_even_i = %d\n", i,
 			 iEvenMeasOffset);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_odd_q = %d\n", i,
 			 qOddMeasOffset);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d pwr_meas_even_q = %d\n", i,
 			 qEvenMeasOffset);
 
@@ -6373,10 +6372,10 @@ ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 		qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
 			       numSamples) & 0x1ff;
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
 			 iDcMismatch);
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
 			 qDcMismatch);
 
@@ -6385,7 +6384,7 @@ ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 		val |= (qDcMismatch << 12) | (iDcMismatch << 21);
 		REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "ADC DC Offset Cal done for Chain %d\n", i);
 	}
 
@@ -6394,7 +6393,7 @@ ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
 		  AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
 }
 
-enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
+bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_channel_internal *ichan = ah->ah_curchan;
@@ -6410,9 +6409,9 @@ enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
 				 min((u_int32_t) MAX_RATE_POWER,
 				     (u_int32_t) ah->ah_powerLimit))
 	    != HAL_OK)
-		return AH_FALSE;
+		return false;
 
-	return AH_TRUE;
+	return true;
 }
 
 void
@@ -6454,14 +6453,14 @@ ath9k_hw_get_channel_centers(struct ath_hal *ah,
 
 void
 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
-			enum hal_bool *isCalDone)
+			bool *isCalDone)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_channel_internal *ichan =
 		ath9k_regd_check_channel(ah, chan);
 	struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
 
-	*isCalDone = AH_TRUE;
+	*isCalDone = true;
 
 	if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
 		return;
@@ -6470,7 +6469,7 @@ ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
 		return;
 
 	if (ichan == NULL) {
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: invalid channel %u/0x%x; no mapping\n",
 			 __func__, chan->channel, chan->channelFlags);
 		return;
@@ -6478,19 +6477,18 @@ ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
 
 
 	if (currCal->calState != CAL_DONE) {
-		HDPRINTF(ah, HAL_DBG_CALIBRATE,
+		DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 			 "%s: Calibration state incorrect, %d\n",
 			 __func__, currCal->calState);
 		return;
 	}
 
 
-	if (ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType)
-	    == AH_FALSE) {
+	if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType)) {
 		return;
 	}
 
-	HDPRINTF(ah, HAL_DBG_CALIBRATE,
+	DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 		 "%s: Resetting Cal %d state for channel %u/0x%x\n",
 		 __func__, currCal->calData->calType, chan->channel,
 		 chan->channelFlags);
@@ -6498,7 +6496,7 @@ ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
 	ichan->CalValid &= ~currCal->calData->calType;
 	currCal->calState = CAL_WAITING;
 
-	*isCalDone = AH_FALSE;
+	*isCalDone = false;
 }
 
 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac)
@@ -6508,12 +6506,12 @@ void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac)
 	memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
 }
 
-enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac)
+bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
-	return AH_TRUE;
+	return true;
 }
 
 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask)
@@ -6523,7 +6521,7 @@ void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask)
 	memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
 }
 
-enum hal_bool
+bool
 ath9k_hw_setbssidmask(struct ath_hal *ah, const u_int8_t *mask)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
@@ -6533,7 +6531,7 @@ ath9k_hw_setbssidmask(struct ath_hal *ah, const u_int8_t *mask)
 	REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
 	REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
 
-	return AH_TRUE;
+	return true;
 }
 
 #ifdef CONFIG_ATH9K_RFKILL
@@ -6541,14 +6539,14 @@ static void ath9k_enable_rfkill(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-		       AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
+	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
+		    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
 
-	OS_REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-		       AR_GPIO_INPUT_MUX2_RFSILENT);
+	REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
+		    AR_GPIO_INPUT_MUX2_RFSILENT);
 
 	ath9k_hw_cfg_gpio_input(ah, ahp->ah_gpioSelect);
-	OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
+	REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
 
 	if (ahp->ah_gpioBit == ath9k_hw_gpio_get(ah, ahp->ah_gpioSelect)) {
 
@@ -6592,7 +6590,7 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah)
 	while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
 		count++;
 		if (count > 10) {
-			HDPRINTF(ah, HAL_DBG_RESET,
+			DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 			 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
 				 __func__);
 			break;
@@ -6612,7 +6610,7 @@ void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna)
 	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
 }
 
-enum hal_bool
+bool
 ath9k_hw_setantennaswitch(struct ath_hal *ah,
 			  enum hal_ant_setting settings,
 			  struct hal_channel *chan,
@@ -6634,7 +6632,7 @@ ath9k_hw_setantennaswitch(struct ath_hal *ah,
 		case HAL_ANT_FIXED_A:
 			*tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
 			*rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
-			*antenna_cfgd = AH_TRUE;
+			*antenna_cfgd = true;
 			break;
 		case HAL_ANT_FIXED_B:
 			if (ah->ah_caps.halTxChainMask >
@@ -6642,12 +6640,12 @@ ath9k_hw_setantennaswitch(struct ath_hal *ah,
 				*tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
 			}
 			*rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
-			*antenna_cfgd = AH_TRUE;
+			*antenna_cfgd = true;
 			break;
 		case HAL_ANT_VARIABLE:
 			*tx_chainmask = tx_chainmask_cfg;
 			*rx_chainmask = rx_chainmask_cfg;
-			*antenna_cfgd = AH_TRUE;
+			*antenna_cfgd = true;
 			break;
 		default:
 			break;
@@ -6656,7 +6654,7 @@ ath9k_hw_setantennaswitch(struct ath_hal *ah,
 		ahp->ah_diversityControl = settings;
 	}
 
-	return AH_TRUE;
+	return true;
 }
 
 void ath9k_hw_setopmode(struct ath_hal *ah)
@@ -6664,7 +6662,7 @@ void ath9k_hw_setopmode(struct ath_hal *ah)
 	ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
 }
 
-enum hal_bool
+bool
 ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 		       u_int32_t capability, u_int32_t *result)
 {
@@ -6680,70 +6678,58 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 		case HAL_CIPHER_WEP:
 		case HAL_CIPHER_MIC:
 		case HAL_CIPHER_CLR:
-			return AH_TRUE;
+			return true;
 		default:
-			return AH_FALSE;
+			return false;
 		}
 	case HAL_CAP_TKIP_MIC:
 		switch (capability) {
 		case 0:
-			return AH_TRUE;
+			return true;
 		case 1:
 			return (ahp->ah_staId1Defaults &
-				AR_STA_ID1_CRPT_MIC_ENABLE) ? AH_TRUE :
-			AH_FALSE;
+				AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
+			false;
 		}
 	case HAL_CAP_TKIP_SPLIT:
 		return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
-			AH_FALSE : AH_TRUE;
+			false : true;
 	case HAL_CAP_WME_TKIPMIC:
 		return HAL_OK;
 	case HAL_CAP_PHYCOUNTERS:
 		return ahp->ah_hasHwPhyCounters ? HAL_OK : HAL_ENXIO;
 	case HAL_CAP_DIVERSITY:
-		switch (capability) {
-		case 0:
-			return AH_TRUE;
-		case 1:
-			return (REG_READ(ah, AR_PHY_CCK_DETECT) &
-				AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
-				AH_TRUE : AH_FALSE;
-		}
-		return AH_FALSE;
+		return (REG_READ(ah, AR_PHY_CCK_DETECT) &
+			AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
+			true : false;
 	case HAL_CAP_PHYDIAG:
-		return AH_TRUE;
+		return true;
 	case HAL_CAP_MCAST_KEYSRCH:
 		switch (capability) {
 		case 0:
-			return AH_TRUE;
+			return true;
 		case 1:
 			if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
-				return AH_FALSE;
+				return false;
 			} else {
 				return (ahp->ah_staId1Defaults &
-					AR_STA_ID1_MCAST_KSRCH) ? AH_TRUE :
-					AH_FALSE;
+					AR_STA_ID1_MCAST_KSRCH) ? true :
+					false;
 			}
 		}
-		return AH_FALSE;
+		return false;
 	case HAL_CAP_TSF_ADJUST:
-		switch (capability) {
-		case 0:
-			return AH_TRUE;
-		case 1:
-			return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
-				AH_TRUE : AH_FALSE;
-		}
-		return AH_FALSE;
+		return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
+			true : false;
 	case HAL_CAP_RFSILENT:
 		if (capability == 3)
-			return AH_FALSE;
+			return false;
 	case HAL_CAP_ANT_CFG_2GHZ:
 		*result = pCap->halNumAntCfg2GHz;
-		return AH_TRUE;
+		return true;
 	case HAL_CAP_ANT_CFG_5GHZ:
 		*result = pCap->halNumAntCfg5GHz;
-		return AH_TRUE;
+		return true;
 	case HAL_CAP_TXPOW:
 		switch (capability) {
 		case 0:
@@ -6758,9 +6744,9 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 			*result = ah->ah_tpScale;
 			return HAL_OK;
 		}
-		return AH_FALSE;
+		return false;
 	default:
-		return AH_FALSE;
+		return false;
 	}
 }
 
@@ -6789,32 +6775,32 @@ ath9k_hw_select_antconfig(struct ath_hal *ah, u_int32_t cfg)
 	return HAL_EINVAL;
 }
 
-enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah)
+bool ath9k_hw_intrpend(struct ath_hal *ah)
 {
 	u_int32_t host_isr;
 
 	if (AR_SREV_9100(ah))
-		return AH_TRUE;
+		return true;
 
 	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
 	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
-		return AH_TRUE;
+		return true;
 
 	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
 	if ((host_isr & AR_INTR_SYNC_DEFAULT)
 	    && (host_isr != AR_INTR_SPURIOUS))
-		return AH_TRUE;
+		return true;
 
-	return AH_FALSE;
+	return false;
 }
 
-enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
+bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 {
 	u_int32_t isr = 0;
 	u_int32_t mask2 = 0;
 	struct hal_capabilities *pCap = &ah->ah_caps;
 	u_int32_t sync_cause = 0;
-	enum hal_bool fatal_int = AH_FALSE;
+	bool fatal_int = false;
 
 	if (!AR_SREV_9100(ah)) {
 		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -6831,7 +6817,7 @@ enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 		*masked = 0;
 
 		if (!isr && !sync_cause)
-			return AH_FALSE;
+			return false;
 	} else {
 		*masked = 0;
 		isr = REG_READ(ah, AR_ISR);
@@ -6860,7 +6846,7 @@ enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 		isr = REG_READ(ah, AR_ISR_RAC);
 		if (isr == 0xffffffff) {
 			*masked = 0;
-			return AH_FALSE;
+			return false;
 		}
 
 		*masked = isr & HAL_INT_COMMON;
@@ -6890,7 +6876,7 @@ enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 		}
 
 		if (isr & AR_ISR_RXORN) {
-			HDPRINTF(ah, HAL_DBG_INTERRUPT,
+			DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
 				 "%s: receive FIFO overrun interrupt\n",
 				 __func__);
 		}
@@ -6906,27 +6892,27 @@ enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 		*masked |= mask2;
 	}
 	if (AR_SREV_9100(ah))
-		return AH_TRUE;
+		return true;
 	if (sync_cause) {
 		fatal_int =
 			(sync_cause &
 			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
-			? AH_TRUE : AH_FALSE;
+			? true : false;
 
-		if (AH_TRUE == fatal_int) {
+		if (fatal_int) {
 			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
-				HDPRINTF(ah, HAL_DBG_UNMASKABLE,
+				DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 					 "%s: received PCI FATAL interrupt\n",
 					 __func__);
 			}
 			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
-				HDPRINTF(ah, HAL_DBG_UNMASKABLE,
+				DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 					 "%s: received PCI PERR interrupt\n",
 					 __func__);
 			}
 		}
 		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
-			HDPRINTF(ah, HAL_DBG_INTERRUPT,
+			DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
 				 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
 				 __func__);
 			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
@@ -6934,7 +6920,7 @@ enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 			*masked |= HAL_INT_FATAL;
 		}
 		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
-			HDPRINTF(ah, HAL_DBG_INTERRUPT,
+			DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
 				 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
 				 __func__);
 		}
@@ -6942,7 +6928,7 @@ enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
 		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
 		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
 	}
-	return AH_TRUE;
+	return true;
 }
 
 enum hal_int ath9k_hw_intrget(struct ath_hal *ah)
@@ -6957,11 +6943,11 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 	u_int32_t mask, mask2;
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
-	HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
+	DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
 		 omask, ints);
 
 	if (omask & HAL_INT_GLOBAL) {
-		HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: disable IER\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
 			 __func__);
 		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
 		(void) REG_READ(ah, AR_IER);
@@ -7017,7 +7003,7 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 			mask2 |= AR_IMR_S2_CST;
 	}
 
-	HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
+	DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
 		 mask);
 	REG_WRITE(ah, AR_IMR, mask);
 	mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
@@ -7032,13 +7018,13 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 
 	if (!pCap->halAutoSleepSupport) {
 		if (ints & HAL_INT_TIM_TIMER)
-			OS_REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
 		else
-			OS_REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
 	}
 
 	if (ints & HAL_INT_GLOBAL) {
-		HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: enable IER\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
 			 __func__);
 		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
 		if (!AR_SREV_9100(ah)) {
@@ -7052,7 +7038,7 @@ enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
 			REG_WRITE(ah, AR_INTR_SYNC_MASK,
 				  AR_INTR_SYNC_DEFAULT);
 		}
-		HDPRINTF(ah, HAL_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
 			 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
 	}
 
@@ -7077,8 +7063,8 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
 		flags |= AR_TBTT_TIMER_EN;
 		break;
 	case HAL_M_IBSS:
-		OS_REG_SET_BIT(ah, AR_TXCFG,
-			       AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
+		REG_SET_BIT(ah, AR_TXCFG,
+			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
 		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
 			  TU_TO_USEC(next_beacon +
 				     (ahp->ah_atimWindow ? ahp->
@@ -7110,7 +7096,7 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
 		ath9k_hw_reset_tsf(ah);
 	}
 
-	OS_REG_SET_BIT(ah, AR_TIMER_MODE, flags);
+	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
 }
 
 void
@@ -7127,8 +7113,8 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
 	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
 		  TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
 
-	OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
-			 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
+	REG_RMW_FIELD(ah, AR_RSSI_THR,
+		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
 
 	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
 
@@ -7144,13 +7130,13 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
 	else
 		nextTbtt = bs->bs_nexttbtt;
 
-	HDPRINTF(ah, HAL_DBG_BEACON, "%s: next DTIM %d\n", __func__,
+	DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
 		 bs->bs_nextdtim);
-	HDPRINTF(ah, HAL_DBG_BEACON, "%s: next beacon %d\n", __func__,
+	DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
 		 nextTbtt);
-	HDPRINTF(ah, HAL_DBG_BEACON, "%s: beacon period %d\n", __func__,
+	DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
 		 beaconintval);
-	HDPRINTF(ah, HAL_DBG_BEACON, "%s: DTIM period %d\n", __func__,
+	DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
 		 dtimperiod);
 
 	REG_WRITE(ah, AR_NEXT_DTIM,
@@ -7172,30 +7158,30 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
 	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
 	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
 
-	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
-		       AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
-		       AR_DTIM_TIMER_EN);
+	REG_SET_BIT(ah, AR_TIMER_MODE,
+		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
+		    AR_DTIM_TIMER_EN);
 
 }
 
-enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry)
+bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry)
 {
 	if (entry < ah->ah_caps.halKeyCacheSize) {
 		u_int32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
 		if (val & AR_KEYTABLE_VALID)
-			return AH_TRUE;
+			return true;
 	}
-	return AH_FALSE;
+	return false;
 }
 
-enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
+bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
 {
 	u_int32_t keyType;
 
 	if (entry >= ah->ah_caps.halKeyCacheSize) {
-		HDPRINTF(ah, HAL_DBG_KEYCACHE,
+		DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 			 "%s: entry %u out of range\n", __func__, entry);
-		return AH_FALSE;
+		return false;
 	}
 	keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
 
@@ -7219,21 +7205,21 @@ enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
 	}
 
 	if (ah->ah_curchan == NULL)
-		return AH_TRUE;
+		return true;
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool
+bool
 ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
 		   const u_int8_t *mac)
 {
 	u_int32_t macHi, macLo;
 
 	if (entry >= ah->ah_caps.halKeyCacheSize) {
-		HDPRINTF(ah, HAL_DBG_KEYCACHE,
+		DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 			 "%s: entry %u out of range\n", __func__, entry);
-		return AH_FALSE;
+		return false;
 	}
 
 	if (mac != NULL) {
@@ -7249,10 +7235,10 @@ ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
 	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
 	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool
+bool
 ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 			    const struct hal_keyval *k,
 			    const u_int8_t *mac, int xorKey)
@@ -7266,9 +7252,9 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
 	if (entry >= pCap->halKeyCacheSize) {
-		HDPRINTF(ah, HAL_DBG_KEYCACHE,
+		DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 			 "%s: entry %u out of range\n", __func__, entry);
-		return AH_FALSE;
+		return false;
 	}
 	switch (k->kv_type) {
 	case HAL_CIPHER_AES_OCB:
@@ -7276,11 +7262,11 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		break;
 	case HAL_CIPHER_AES_CCM:
 		if (!pCap->halCipherAesCcmSupport) {
-			HDPRINTF(ah, HAL_DBG_KEYCACHE,
+			DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 				 "%s: AES-CCM not supported by "
 				 "mac rev 0x%x\n", __func__,
 				 ah->ah_macRev);
-			return AH_FALSE;
+			return false;
 		}
 		keyType = AR_KEYTABLE_TYPE_CCM;
 		break;
@@ -7288,18 +7274,18 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		keyType = AR_KEYTABLE_TYPE_TKIP;
 		if (ATH9K_IS_MIC_ENABLED(ah)
 		    && entry + 64 >= pCap->halKeyCacheSize) {
-			HDPRINTF(ah, HAL_DBG_KEYCACHE,
+			DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 				 "%s: entry %u inappropriate for TKIP\n",
 				 __func__, entry);
-			return AH_FALSE;
+			return false;
 		}
 		break;
 	case HAL_CIPHER_WEP:
 		if (k->kv_len < 40 / NBBY) {
-			HDPRINTF(ah, HAL_DBG_KEYCACHE,
+			DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 				 "%s: WEP key length %u too small\n",
 				 __func__, k->kv_len);
-			return AH_FALSE;
+			return false;
 		}
 		if (k->kv_len <= 40 / NBBY)
 			keyType = AR_KEYTABLE_TYPE_40;
@@ -7312,10 +7298,10 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 		keyType = AR_KEYTABLE_TYPE_CLR;
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_KEYCACHE,
+		DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
 			 "%s: cipher %u not supported\n", __func__,
 			 k->kv_type);
-		return AH_FALSE;
+		return false;
 	}
 
 	key0 = LE_READ_4(k->kv_val + 0) ^ xorMask;
@@ -7382,20 +7368,20 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
 	}
 
 	if (ah->ah_curchan == NULL)
-		return AH_TRUE;
+		return true;
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool
-ath9k_hw_updatetxtriglevel(struct ath_hal *ah, enum hal_bool bIncTrigLevel)
+bool
+ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	u_int32_t txcfg, curLevel, newLevel;
 	enum hal_int omask;
 
 	if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
-		return AH_FALSE;
+		return false;
 
 	omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~HAL_INT_GLOBAL);
 
@@ -7418,19 +7404,19 @@ ath9k_hw_updatetxtriglevel(struct ath_hal *ah, enum hal_bool bIncTrigLevel)
 	return newLevel != curLevel;
 }
 
-static enum hal_bool ath9k_hw_set_txq_props(struct ath_hal *ah,
-				     struct hal_tx_queue_info *qi,
-				     const struct hal_txq_info *qInfo)
+static bool ath9k_hw_set_txq_props(struct ath_hal *ah,
+				   struct hal_tx_queue_info *qi,
+				   const struct hal_txq_info *qInfo)
 {
 	u_int32_t cw;
 
 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
 			 __func__);
-		return AH_FALSE;
+		return false;
 	}
 
-	HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
+	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
 
 	qi->tqi_ver = qInfo->tqi_ver;
 	qi->tqi_subtype = qInfo->tqi_subtype;
@@ -7476,31 +7462,31 @@ static enum hal_bool ath9k_hw_set_txq_props(struct ath_hal *ah,
 	default:
 		break;
 	}
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
-				       const struct hal_txq_info *qInfo)
+bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
+			      const struct hal_txq_info *qInfo)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
 	if (q >= pCap->halTotalQueues) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
 			 __func__, q);
-		return AH_FALSE;
+		return false;
 	}
 	return ath9k_hw_set_txq_props(ah, &ahp->ah_txq[q], qInfo);
 }
 
-static enum hal_bool ath9k_hw_get_txq_props(struct ath_hal *ah,
-				     struct hal_txq_info *qInfo,
-				     const struct hal_tx_queue_info *qi)
+static bool ath9k_hw_get_txq_props(struct ath_hal *ah,
+				   struct hal_txq_info *qInfo,
+				   const struct hal_tx_queue_info *qi)
 {
 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
 			 __func__);
-		return AH_FALSE;
+		return false;
 	}
 
 	qInfo->tqi_qflags = qi->tqi_qflags;
@@ -7518,10 +7504,10 @@ static enum hal_bool ath9k_hw_get_txq_props(struct ath_hal *ah,
 	qInfo->tqi_burstTime = qi->tqi_burstTime;
 	qInfo->tqi_readyTime = qi->tqi_readyTime;
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool
+bool
 ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
 			 struct hal_txq_info *qInfo)
 {
@@ -7529,9 +7515,9 @@ ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
 	struct hal_capabilities *pCap = &ah->ah_caps;
 
 	if (q >= pCap->halTotalQueues) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
 			 __func__, q);
-		return AH_FALSE;
+		return false;
 	}
 	return ath9k_hw_get_txq_props(ah, qInfo, &ahp->ah_txq[q]);
 }
@@ -7564,22 +7550,22 @@ ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
 			    HAL_TX_QUEUE_INACTIVE)
 				break;
 		if (q == pCap->halTotalQueues) {
-			HDPRINTF(ah, HAL_DBG_QUEUE,
+			DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
 				 "%s: no available tx queue\n", __func__);
 			return -1;
 		}
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: bad tx queue type %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
 			 __func__, type);
 		return -1;
 	}
 
-	HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %u\n", __func__, q);
+	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
 
 	qi = &ahp->ah_txq[q];
 	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
-		HDPRINTF(ah, HAL_DBG_QUEUE,
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
 			 "%s: tx queue %u already active\n", __func__, q);
 		return -1;
 	}
@@ -7610,7 +7596,7 @@ ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	HDPRINTF(ah, HAL_DBG_INTERRUPT,
+	DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
 		 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
 		 __func__, ahp->ah_txOkInterruptMask,
 		 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
@@ -7618,35 +7604,34 @@ ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
 
 	REG_WRITE(ah, AR_IMR_S0,
 		  SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
-		  | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
-		);
+		  | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
 	REG_WRITE(ah, AR_IMR_S1,
 		  SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
-		  | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
-		);
-	OS_REG_RMW_FIELD(ah, AR_IMR_S2,
-			 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
+		  | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
+	REG_RMW_FIELD(ah, AR_IMR_S2,
+		      AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
 }
 
-enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
+bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
 	struct hal_tx_queue_info *qi;
 
 	if (q >= pCap->halTotalQueues) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
 			 __func__, q);
-		return AH_FALSE;
+		return false;
 	}
 	qi = &ahp->ah_txq[q];
 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
 			 __func__, q);
-		return AH_FALSE;
+		return false;
 	}
 
-	HDPRINTF(ah, HAL_DBG_QUEUE, "%s: release queue %u\n", __func__, q);
+	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
+		__func__, q);
 
 	qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
 	ahp->ah_txOkInterruptMask &= ~(1 << q);
@@ -7656,10 +7641,10 @@ enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
 	ahp->ah_txUrnInterruptMask &= ~(1 << q);
 	ath9k_hw_set_txq_interrupts(ah, qi);
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
+bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 	struct hal_capabilities *pCap = &ah->ah_caps;
@@ -7668,18 +7653,18 @@ enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 	u_int32_t cwMin, chanCwMin, value;
 
 	if (q >= pCap->halTotalQueues) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
 			 __func__, q);
-		return AH_FALSE;
+		return false;
 	}
 	qi = &ahp->ah_txq[q];
 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
-		HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue %u\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
 			 __func__, q);
-		return AH_TRUE;
+		return true;
 	}
 
-	HDPRINTF(ah, HAL_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
+	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
 
 	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
 		if (chan && IS_CHAN_B(chan))
@@ -7822,7 +7807,7 @@ enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
 		ahp->ah_txUrnInterruptMask &= ~(1 << q);
 	ath9k_hw_set_txq_interrupts(ah, qi);
 
-	return AH_TRUE;
+	return true;
 }
 
 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs)
@@ -7832,34 +7817,10 @@ void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs)
 	ahp->ah_intrTxqs &= ~(*txqs);
 }
 
-enum hal_bool
-ath9k_hw_setupxtxdesc(struct ath_hal *ah, struct ath_desc *ds,
-		      u_int txRate1, u_int txTries1,
-		      u_int txRate2, u_int txTries2,
-		      u_int txRate3, u_int txTries3)
-{
-	struct ar5416_desc *ads = AR5416DESC(ds);
-
-	if (txTries1) {
-		ads->ds_ctl2 |= AR_DurUpdateEna;
-		ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1);
-		ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
-	}
-	if (txTries2) {
-		ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2);
-		ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
-	}
-	if (txTries3) {
-		ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3);
-		ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
-	}
-	return AH_TRUE;
-}
-
-enum hal_bool
+bool
 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
-		    u_int segLen, enum hal_bool firstSeg,
-		    enum hal_bool lastSeg, const struct ath_desc *ds0)
+		    u_int segLen, bool firstSeg,
+		    bool lastSeg, const struct ath_desc *ds0)
 {
 	struct ar5416_desc *ads = AR5416DESC(ds);
 
@@ -7881,7 +7842,7 @@ ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
 	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
 	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
 	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
-	return AH_TRUE;
+	return true;
 }
 
 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
@@ -7909,28 +7870,28 @@ ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
 	ds->ds_txstat.ts_flags = 0;
 
 	if (ads->ds_txstatus1 & AR_ExcessiveRetries)
-		ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
 	if (ads->ds_txstatus1 & AR_Filtered)
-		ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
 	if (ads->ds_txstatus1 & AR_FIFOUnderrun)
-		ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
 	if (ads->ds_txstatus9 & AR_TxOpExceeded)
-		ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
 	if (ads->ds_txstatus1 & AR_TxTimerExpired)
-		ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
 
 	if (ads->ds_txstatus1 & AR_DescCfgErr)
-		ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
+		ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
 	if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
-		ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
-		ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
+		ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
+		ath9k_hw_updatetxtriglevel(ah, true);
 	}
 	if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
-		ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
-		ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
+		ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
+		ath9k_hw_updatetxtriglevel(ah, true);
 	}
 	if (ads->ds_txstatus0 & AR_TxBaStatus) {
-		ds->ds_txstat.ts_flags |= HAL_TX_BA;
+		ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
 		ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
 		ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
 	}
@@ -8141,34 +8102,34 @@ void ath9k_hw_rxena(struct ath_hal *ah)
 	REG_WRITE(ah, AR_CR, AR_CR_RXE);
 }
 
-enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set)
+bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
 {
 	if (set) {
 
-		OS_REG_SET_BIT(ah, AR_DIAG_SW,
-			       (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
+		REG_SET_BIT(ah, AR_DIAG_SW,
+			    (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 
 		if (!ath9k_hw_wait
 		    (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
 			u_int32_t reg;
 
-			OS_REG_CLR_BIT(ah, AR_DIAG_SW,
-				       (AR_DIAG_RX_DIS |
-					AR_DIAG_RX_ABORT));
+			REG_CLR_BIT(ah, AR_DIAG_SW,
+				    (AR_DIAG_RX_DIS |
+				     AR_DIAG_RX_ABORT));
 
 			reg = REG_READ(ah, AR_OBS_BUS_1);
-			HDPRINTF(ah, HAL_DBG_RX,
+			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				"%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
 				__func__, reg);
 
-			return AH_FALSE;
+			return false;
 		}
 	} else {
-		OS_REG_CLR_BIT(ah, AR_DIAG_SW,
-			       (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
+		REG_CLR_BIT(ah, AR_DIAG_SW,
+			    (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 	}
 
-	return AH_TRUE;
+	return true;
 }
 
 void
@@ -8179,7 +8140,7 @@ ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
 	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
 }
 
-enum hal_bool
+bool
 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
 		     u_int32_t size, u_int flags)
 {
@@ -8193,7 +8154,7 @@ ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
 	ads->ds_rxstatus8 &= ~AR_RxDone;
 	if (!pCap->halAutoSleepSupport)
 		memset(&(ads->u), 0, sizeof(ads->u));
-	return AH_TRUE;
+	return true;
 }
 
 enum hal_status
@@ -8234,31 +8195,31 @@ ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
 		(ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
 	ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
 	ds->ds_rxstat.rs_flags =
-		(ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
+		(ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
 	ds->ds_rxstat.rs_flags |=
-		(ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
+		(ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
 
 	if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
-		ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_PRE;
+		ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
 	if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
-		ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_POST;
+		ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
 	if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
-		ds->ds_rxstat.rs_flags |= HAL_RX_DECRYPT_BUSY;
+		ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
 
 	if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
 
 		if (ads.ds_rxstatus8 & AR_CRCErr)
-			ds->ds_rxstat.rs_status |= HAL_RXERR_CRC;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
 		else if (ads.ds_rxstatus8 & AR_PHYErr) {
 			u_int phyerr;
 
-			ds->ds_rxstat.rs_status |= HAL_RXERR_PHY;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
 			phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
 			ds->ds_rxstat.rs_phyerr = phyerr;
 		} else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
-			ds->ds_rxstat.rs_status |= HAL_RXERR_DECRYPT;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
 		else if (ads.ds_rxstatus8 & AR_MichaelErr)
-			ds->ds_rxstat.rs_status |= HAL_RXERR_MIC;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
 	}
 
 	return HAL_OK;
@@ -8284,12 +8245,12 @@ static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
 			ath9k_hw_computetxtime(ah, rt,
 					       WLAN_CTRL_FRAME_SIZE,
 					       cix,
-					       AH_FALSE);
+					       false);
 		rt->info[i].spAckDuration =
 			ath9k_hw_computetxtime(ah, rt,
 					       WLAN_CTRL_FRAME_SIZE,
 					       cix,
-					       AH_TRUE);
+					       true);
 	}
 }
 
@@ -8318,7 +8279,7 @@ const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
 		rt = &ar5416_11na_table;
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
 			 __func__, mode);
 		return NULL;
 	}
@@ -8347,7 +8308,9 @@ const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid)
 		ath9k_hw_devname(devid) : NULL;
 }
 
-struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
+struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+				struct ath_softc *sc,
+				void __iomem *mem,
 				enum hal_status *error)
 {
 	struct ath_hal *ah = NULL;
@@ -8361,7 +8324,7 @@ struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
 		ah = ath9k_hw_do_attach(devid, sc, mem, error);
 		break;
 	default:
-		HDPRINTF(ah, HAL_DBG_UNMASKABLE,
+		DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 			 "devid=0x%x not supported.\n", devid);
 		ah = NULL;
 		*error = HAL_ENXIO;
@@ -8383,7 +8346,7 @@ u_int16_t
 ath9k_hw_computetxtime(struct ath_hal *ah,
 		       const struct hal_rate_table *rates,
 		       u_int32_t frameLen, u_int16_t rateix,
-		       enum hal_bool shortPreamble)
+		       bool shortPreamble)
 {
 	u_int32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 	u_int32_t kbps;
@@ -8433,7 +8396,7 @@ ath9k_hw_computetxtime(struct ath_hal *ah,
 		break;
 
 	default:
-		HDPRINTF(ah, HAL_DBG_PHY_IO,
+		DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 			 "%s: unknown phy %u (rate ix %u)\n", __func__,
 			 rates->info[rateix].phy, rateix);
 		txTime = 0;
@@ -8489,7 +8452,7 @@ ath9k_hw_getchan_noise(struct ath_hal *ah, struct hal_channel *chan)
 
 	ichan = ath9k_regd_check_channel(ah, chan);
 	if (ichan == NULL) {
-		HDPRINTF(ah, HAL_DBG_NF_CAL,
+		DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
 			 "%s: invalid channel %u/0x%x; no mapping\n",
 			 __func__, chan->channel, chan->channelFlags);
 		return 0;
@@ -8501,7 +8464,7 @@ ath9k_hw_getchan_noise(struct ath_hal *ah, struct hal_channel *chan)
 		return ichan->rawNoiseFloor;
 }
 
-enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u_int32_t setting)
+bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u_int32_t setting)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -8509,14 +8472,14 @@ enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u_int32_t setting)
 		ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
 	else
 		ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah)
+bool ath9k_hw_phycounters(struct ath_hal *ah)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
-	return ahp->ah_hasHwPhyCounters ? AH_TRUE : AH_FALSE;
+	return ahp->ah_hasHwPhyCounters ? true : false;
 }
 
 u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q)
@@ -8524,21 +8487,21 @@ u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q)
 	return REG_READ(ah, AR_QTXDP(q));
 }
 
-enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
-				u_int32_t txdp)
+bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
+		       u_int32_t txdp)
 {
 	REG_WRITE(ah, AR_QTXDP(q), txdp);
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q)
+bool ath9k_hw_txstart(struct ath_hal *ah, u_int q)
 {
-	HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %u\n", __func__, q);
+	DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
 
 	REG_WRITE(ah, AR_Q_TXE, 1 << q);
 
-	return AH_TRUE;
+	return true;
 }
 
 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q)
@@ -8554,7 +8517,7 @@ u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q)
 	return npend;
 }
 
-enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
+bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
 {
 	u_int wait;
 
@@ -8569,7 +8532,7 @@ enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
 	if (ath9k_hw_numtxpending(ah, q)) {
 		u_int32_t tsfLow, j;
 
-		HDPRINTF(ah, HAL_DBG_QUEUE,
+		DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
 			 "%s: Num of pending TX Frames %d on Q %d\n",
 			 __func__, ath9k_hw_numtxpending(ah, q), q);
 
@@ -8579,29 +8542,29 @@ enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
 				  SM(10, AR_QUIET2_QUIET_DUR));
 			REG_WRITE(ah, AR_QUIET_PERIOD, 100);
 			REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
-			OS_REG_SET_BIT(ah, AR_TIMER_MODE,
+			REG_SET_BIT(ah, AR_TIMER_MODE,
 				       AR_QUIET_TIMER_EN);
 
 			if ((REG_READ(ah, AR_TSF_L32) >> 10) ==
 			    (tsfLow >> 10)) {
 				break;
 			}
-			HDPRINTF(ah, HAL_DBG_QUEUE,
+			DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
 				"%s: TSF have moved while trying to set "
 				"quiet time TSF: 0x%08x\n",
 				__func__, tsfLow);
 		}
 
-		OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+		REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
 
 		udelay(200);
-		OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
+		REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
 
 		wait = 1000;
 
 		while (ath9k_hw_numtxpending(ah, q)) {
 			if ((--wait) == 0) {
-				HDPRINTF(ah, HAL_DBG_TX,
+				DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
 					"%s: Failed to stop Tx DMA in 100 "
 					"msec after killing last frame\n",
 					__func__);
@@ -8610,7 +8573,7 @@ enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
 			udelay(100);
 		}
 
-		OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
+		REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
 	}
 
 	REG_WRITE(ah, AR_Q_TXD, 0);
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/hw.h b/package/ath9k/src/drivers/net/wireless/ath9k/hw.h
index 089aecdf40..1a77ed3b1b 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/hw.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/hw.h
@@ -711,7 +711,7 @@ struct ath_hal_5416 {
 	u_int32_t ah_txUrnInterruptMask;
 	struct hal_tx_queue_info ah_txq[HAL_NUM_TX_QUEUES];
 	enum hal_power_mode ah_powerMode;
-	enum hal_bool ah_chipFullSleep;
+	bool ah_chipFullSleep;
 	u_int32_t ah_atimWindow;
 	enum hal_ant_setting ah_diversityControl;
 	u_int16_t ah_antennaSwitchSwap;
@@ -754,7 +754,7 @@ struct ath_hal_5416 {
 	u_int32_t ah_tx6PowerInHalfDbm;
 	u_int32_t ah_staId1Defaults;
 	u_int32_t ah_miscMode;
-	enum hal_bool ah_tpcEnabled;
+	bool ah_tpcEnabled;
 	u_int32_t ah_beaconInterval;
 	enum {
 		AUTO_32KHZ,
@@ -780,9 +780,9 @@ struct ath_hal_5416 {
 	u_int32_t ah_gpioSelect;
 	u_int32_t ah_polarity;
 	u_int32_t ah_gpioBit;
-	enum hal_bool ah_eepEnabled;
+	bool ah_eepEnabled;
 	u_int32_t ah_procPhyErr;
-	enum hal_bool ah_hasHwPhyCounters;
+	bool ah_hasHwPhyCounters;
 	u_int32_t ah_aniPeriod;
 	struct ar5416AniState *ah_curani;
 	struct ar5416AniState ah_ani[255];
@@ -792,7 +792,7 @@ struct ath_hal_5416 {
 	int ah_firpwr[5];
 	u_int16_t ah_ratesArray[16];
 	u_int32_t ah_intrTxqs;
-	enum hal_bool ah_intrMitigation;
+	bool ah_intrMitigation;
 	u_int32_t ah_cycleCount;
 	u_int32_t ah_ctlBusy;
 	u_int32_t ah_extBusy;
@@ -899,8 +899,8 @@ struct ath_hal_5416 {
 #define HAL_ANI_CCK_TRIG_HIGH           200
 #define HAL_ANI_CCK_TRIG_LOW            100
 #define HAL_ANI_NOISE_IMMUNE_LVL        4
-#define HAL_ANI_USE_OFDM_WEAK_SIG       AH_TRUE
-#define HAL_ANI_CCK_WEAK_SIG_THR        AH_FALSE
+#define HAL_ANI_USE_OFDM_WEAK_SIG       true
+#define HAL_ANI_CCK_WEAK_SIG_THR        false
 #define HAL_ANI_SPUR_IMMUNE_LVL         7
 #define HAL_ANI_FIRSTEP_LVL             0
 #define HAL_ANI_RSSI_THR_HIGH           40
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/main.c b/package/ath9k/src/drivers/net/wireless/ath9k/main.c
index 670a5165a7..7ef0d58a31 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/main.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/main.c
@@ -108,7 +108,7 @@ static int ath_setkey_tkip(struct ath_softc *sc,
 	memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 	if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 		/* Txmic entry failed. No need to proceed further */
-		DPRINTF(sc, ATH_DEBUG_KEYCACHE,
+		DPRINTF(sc, ATH_DBG_KEYCACHE,
 			"%s Setting TX MIC Key Failed\n", __func__);
 		return 0;
 	}
@@ -279,65 +279,6 @@ static void ath9k_rx_prepare(struct ath_softc *sc,
 	rx_status->flag |= RX_FLAG_TSFT;
 }
 
-/*
- * Update all associated nodes and VAPs
- *
- * Called when local channel width changed.  e.g. if AP mode,
- * update all associated STAs when the AP's channel width changes.
- */
-static void cwm_rate_updateallnodes(struct ath_softc *sc)
-{
-	int flags = 0, error;
-	struct ieee80211_vif *vif;
-	enum ieee80211_if_types opmode;
-	struct ieee80211_hw *hw = sc->hw;
-
-	if (sc->sc_vaps[0]) {
-		vif = sc->sc_vaps[0]->av_if_data;
-		opmode = vif->type;
-		switch (opmode) {
-		case IEEE80211_IF_TYPE_STA:
-			/* sync with next received beacon */
-			flags |= ATH_IF_BEACON_SYNC;
-			if (hw->conf.ht_conf.ht_supported)
-				flags |= ATH_IF_HT;
-			error = ath_vap_up(sc, 0,
-			   /* sc->sc_vaps[i]->av_btxctl->if_id,  FIX ME if_id */
-			   /* sc->sc_vaps[i]->bssid, FIX ME bssid */
-					   sc->sc_curbssid,
-					   sc->sc_curaid,
-					   flags);
-			if (error)/* FIX ME if_id */
-				DPRINTF(sc, ATH_DEBUG_CWM,
-					"%s: Unable to up vap: "
-					"%d\n", __func__, 0);
-			else
-				DPRINTF(sc, ATH_DEBUG_CWM,
-					"%s: VAP up for id: "
-					"%d\n", __func__, 0);
-			break;
-		case IEEE80211_IF_TYPE_IBSS:
-		case IEEE80211_IF_TYPE_AP:
-			/* FIXME */
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-/* Action: switch MAC from 40 to 20  (OR) 20 to 40 based on ch_width arg */
-static void cwm_action_mac_change_chwidth(struct ath_softc *sc,
-				   enum hal_ht_macmode ch_width)
-{
-	ath_set_macmode(sc, ch_width);
-
-	/* notify rate control of new mode (select new rate table) */
-	cwm_rate_updateallnodes(sc);
-
-	/* XXX: all virtual APs - send ch width action management frame */
-}
-
 static u_int8_t parse_mpdudensity(u_int8_t mpdudensity)
 {
 	/*
@@ -380,7 +321,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
 	struct hal_channel hchan;
 	int error = 0;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Starting driver with "
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
 		"initial channel: %d MHz\n", __func__, curchan->center_freq);
 
 	/* setup initial channel */
@@ -391,7 +332,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
 	/* open ath_dev */
 	error = ath_open(sc, &hchan);
 	if (error) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unable to complete ath_open\n", __func__);
 		return error;
 	}
@@ -416,12 +357,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
 		memmove(skb->data, skb->data + padsize, hdrlen);
 	}
 
-	DPRINTF(sc, ATH_DEBUG_XMIT, "%s: transmitting packet, skb: %p\n",
+	DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
 		__func__,
 		skb);
 
 	if (ath_tx_start(sc, skb) != 0) {
-		DPRINTF(sc, ATH_DEBUG_XMIT, "%s: TX failed\n", __func__);
+		DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
 		dev_kfree_skb_any(skb);
 		/* FIXME: Check for proper return value from ATH_DEV */
 		return 0;
@@ -430,26 +371,16 @@ static int ath9k_tx(struct ieee80211_hw *hw,
 	return 0;
 }
 
-static int ath9k_beacon_update(struct ieee80211_hw *hw,
-			       struct sk_buff *skb)
-
-{
-	struct ath_softc *sc = hw->priv;
-
-	DPRINTF(sc, ATH_DEBUG_BEACON, "%s: Update Beacon\n", __func__);
-	return ath9k_tx(hw, skb);
-}
-
 static void ath9k_stop(struct ieee80211_hw *hw)
 {
 	struct ath_softc *sc = hw->priv;
 	int error;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Driver halt\n", __func__);
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
 
 	error = ath_suspend(sc);
 	if (error)
-		DPRINTF(sc, ATH_DEBUG_CONFIG,
+		DPRINTF(sc, ATH_DBG_CONFIG,
 			"%s: Device is no longer present\n", __func__);
 
 	ieee80211_stop_queues(hw);
@@ -464,50 +395,74 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
 	/* Support only vap for now */
 
 	if (sc->sc_nvaps)
-		return -1;
+		return -ENOBUFS;
 
 	switch (conf->type) {
 	case IEEE80211_IF_TYPE_STA:
 		ic_opmode = HAL_M_STA;
-	default:
 		break;
+	case IEEE80211_IF_TYPE_IBSS:
+		ic_opmode = HAL_M_IBSS;
+		break;
+	default:
+		DPRINTF(sc, ATH_DBG_FATAL,
+			"%s: Only STA and IBSS are supported currently\n",
+			__func__);
+		return -EOPNOTSUPP;
 	}
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Attach a VAP of type: %d\n",
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
 		__func__,
 		ic_opmode);
 
-	error = ath_vap_attach(sc, 0, conf->vif, ic_opmode, ic_opmode, 0);
+	error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
 	if (error) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unable to attach vap, error: %d\n",
 			__func__, error);
-		goto bad;
+		return error;
 	}
 
 	return 0;
-bad:
-	return -1;
 }
 
 static void ath9k_remove_interface(struct ieee80211_hw *hw,
 				   struct ieee80211_if_init_conf *conf)
 {
 	struct ath_softc *sc = hw->priv;
-	int error, flags = 0;
+	struct ath_vap *avp;
+	int error;
+
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
+
+	avp = sc->sc_vaps[0];
+	if (avp == NULL) {
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
+			__func__);
+		return;
+	}
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Detach VAP\n", __func__);
+#ifdef CONFIG_SLOW_ANT_DIV
+	ath_slow_ant_div_stop(&sc->sc_antdiv);
+#endif
 
-	flags |= ATH_IF_HW_OFF;
+	/* Update ratectrl */
+	ath_rate_newstate(sc, avp, 0);
 
-	error = ath_vap_down(sc, 0, flags);
-	if (error)
-		DPRINTF(sc, ATH_DEBUG_FATAL,
-			"%s: Unable to down vap, error: %d\n", __func__, error);
+	/* Reclaim beacon resources */
+	if (sc->sc_opmode == HAL_M_HOSTAP || sc->sc_opmode == HAL_M_IBSS) {
+		ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
+		ath_beacon_return(sc, avp);
+	}
+
+	/* Set interrupt mask */
+	sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
+	ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~HAL_INT_GLOBAL);
+	sc->sc_beacons = 0;
 
 	error = ath_vap_detach(sc, 0);
 	if (error)
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unable to detach vap, error: %d\n",
 			__func__, error);
 }
@@ -519,7 +474,7 @@ static int ath9k_config(struct ieee80211_hw *hw,
 	struct ieee80211_channel *curchan = hw->conf.channel;
 	struct hal_channel hchan;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Set channel: %d MHz\n",
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
 		__func__,
 		curchan->center_freq);
 
@@ -529,7 +484,7 @@ static int ath9k_config(struct ieee80211_hw *hw,
 
 	/* set h/w channel */
 	if (ath_set_channel(sc, &hchan) < 0)
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: Unable to set channel\n",
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
 			__func__);
 
 	return 0;
@@ -540,42 +495,102 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
 				  struct ieee80211_if_conf *conf)
 {
 	struct ath_softc *sc = hw->priv;
-	int error = 0, flags = 0;
-	struct sk_buff *beacon;
+	struct ath_vap *avp;
+	u_int32_t rfilt = 0;
+	int error, i;
+	DECLARE_MAC_BUF(mac);
 
-	if (!conf->bssid)
-		return 0;
+	avp = sc->sc_vaps[0];
+	if (avp == NULL) {
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
+			__func__);
+		return -EINVAL;
+	}
 
-	switch (vif->type) {
-	case IEEE80211_IF_TYPE_STA:
-		/* XXX: Handle (conf->changed & IEEE80211_IFCC_SSID) */
-		flags |= ATH_IF_HW_ON;
-		/* sync with next received beacon */
-		flags |= ATH_IF_BEACON_SYNC;
-
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Bring up VAP: %d\n",
-			__func__, 0);
-
-		error = ath_vap_up(sc, 0, conf->bssid, 0, flags);
-		if (error) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
-			"%s: Unable to bring up VAP: %d, error: %d\n",
-			__func__, 0, error);
-			return -1;
-		}
+	if ((conf->changed & IEEE80211_IFCC_BSSID) &&
+	    !is_zero_ether_addr(conf->bssid)) {
+		switch (vif->type) {
+		case IEEE80211_IF_TYPE_STA:
+		case IEEE80211_IF_TYPE_IBSS:
+			/* Update ratectrl about the new state */
+			ath_rate_newstate(sc, avp, 0);
+
+			/* Set rx filter */
+			rfilt = ath_calcrxfilter(sc);
+			ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
+
+			/* Set BSSID */
+			memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
+			sc->sc_curaid = 0;
+			ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
+					       sc->sc_curaid);
+
+			/* Set aggregation protection mode parameters */
+			sc->sc_config.ath_aggr_prot = 0;
+
+			/*
+			 * Reset our TSF so that its value is lower than the
+			 * beacon that we are trying to catch.
+			 * Only then hw will update its TSF register with the
+			 * new beacon. Reset the TSF before setting the BSSID
+			 * to avoid allowing in any frames that would update
+			 * our TSF only to have us clear it
+			 * immediately thereafter.
+			 */
+			ath9k_hw_reset_tsf(sc->sc_ah);
+
+			/* Disable BMISS interrupt when we're not associated */
+			ath9k_hw_set_interrupts(sc->sc_ah,
+						sc->sc_imask &
+						~(HAL_INT_SWBA | HAL_INT_BMISS));
+			sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
+
+			DPRINTF(sc, ATH_DBG_CONFIG,
+				"%s: RX filter 0x%x bssid %s aid 0x%x\n",
+				__func__, rfilt,
+				print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
+
+			/* need to reconfigure the beacon */
+			sc->sc_beacons = 0;
 
-		break;
-	case IEEE80211_IF_TYPE_IBSS:
-		if (!(conf->changed & IEEE80211_IFCC_BEACON))
 			break;
-		beacon = ieee80211_beacon_get(hw, vif);
-		if (!beacon)
-			return -ENOMEM;
-		ath9k_beacon_update(hw, beacon);
-	default:
-		break;
+		default:
+			break;
+		}
+	}
+
+	if ((conf->changed & IEEE80211_IFCC_BEACON) &&
+	    (vif->type == IEEE80211_IF_TYPE_IBSS)) {
+		/*
+		 * Allocate and setup the beacon frame.
+		 *
+		 * Stop any previous beacon DMA.  This may be
+		 * necessary, for example, when an ibss merge
+		 * causes reconfiguration; we may be called
+		 * with beacon transmission active.
+		 */
+		ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
+
+		error = ath_beacon_alloc(sc, 0);
+		if (error != 0)
+			return error;
+
+		ath_beacon_sync(sc, 0);
+	}
+
+	/* Check for WLAN_CAPABILITY_PRIVACY ? */
+	if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
+		for (i = 0; i < IEEE80211_WEP_NKID; i++)
+			if (ath9k_hw_keyisvalid(sc->sc_ah, (u_int16_t)i))
+				ath9k_hw_keysetmac(sc->sc_ah,
+						   (u_int16_t)i,
+						   sc->sc_curbssid);
 	}
 
+	/* Only legacy IBSS for now */
+	if (vif->type == IEEE80211_IF_TYPE_IBSS)
+		ath_update_chainmask(sc, 0);
+
 	return 0;
 }
 
@@ -627,7 +642,7 @@ static void ath9k_sta_notify(struct ieee80211_hw *hw,
 		spin_lock_irqsave(&sc->node_lock, flags);
 		if (!an) {
 			ath_node_attach(sc, (u8 *)addr, 0);
-			DPRINTF(sc, ATH_DEBUG_NODE, "%s: Attach a node: %s\n",
+			DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %s\n",
 				__func__,
 				print_mac(mac, addr));
 		} else {
@@ -637,12 +652,12 @@ static void ath9k_sta_notify(struct ieee80211_hw *hw,
 		break;
 	case STA_NOTIFY_REMOVE:
 		if (!an)
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: Removal of a non-existent node\n",
 				__func__);
 		else {
 			ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
-			DPRINTF(sc, ATH_DEBUG_NODE, "%s: Put a node: %s\n",
+			DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %s\n",
 				__func__,
 				print_mac(mac, addr));
 		}
@@ -669,7 +684,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
 	qi.tqi_burstTime = params->txop;
 	qnum = ath_get_hal_qnum(queue, sc);
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG,
+	DPRINTF(sc, ATH_DBG_CONFIG,
 		"%s: Configure tx [queue/halq] [%d/%d],  "
 		"aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
 		__func__,
@@ -682,7 +697,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
 
 	ret = ath_txq_update(sc, qnum, &qi);
 	if (ret)
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: TXQ Update failed\n", __func__);
 
 	return ret;
@@ -697,7 +712,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
 	struct ath_softc *sc = hw->priv;
 	int ret = 0;
 
-	DPRINTF(sc, ATH_DEBUG_KEYCACHE, " %s: Set HW Key\n", __func__);
+	DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
 
 	switch (cmd) {
 	case SET_KEY:
@@ -741,7 +756,7 @@ static void ath9k_ht_conf(struct ath_softc *sc,
 		else
 			ht_info->tx_chan_width = HAL_HT_MACMODE_20;
 
-		cwm_action_mac_change_chwidth(sc, ht_info->tx_chan_width);
+		ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
 		ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 					bss_conf->ht_conf->ampdu_factor);
 		ht_info->mpdudensity =
@@ -758,16 +773,50 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
 	struct ieee80211_hw *hw = sc->hw;
 	struct ieee80211_channel *curchan = hw->conf.channel;
 	struct hal_channel hchan;
+	struct ath_vap *avp;
+	DECLARE_MAC_BUF(mac);
 
 	if (bss_conf->assoc) {
-		/* FIXME : Do we need any other info
-		 * which is part of association */
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Bss Info ASSOC %d\n",
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
 			__func__,
 			bss_conf->aid);
-		sc->sc_curaid = bss_conf->aid;
 
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Set channel: %d MHz\n",
+		avp = sc->sc_vaps[0];
+		if (avp == NULL) {
+			DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
+				__func__);
+			return;
+		}
+
+		/* Update ratectrl about the new state */
+		ath_rate_newstate(sc, avp, 1);
+
+		/* New association, store aid */
+		if (avp->av_opmode == HAL_M_STA) {
+			sc->sc_curaid = bss_conf->aid;
+			ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
+					       sc->sc_curaid);
+		}
+
+		/* Configure the beacon */
+		ath_beacon_config(sc, 0);
+		sc->sc_beacons = 1;
+
+		/* Reset rssi stats */
+		sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
+		sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
+		sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
+		sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
+
+		/* Update chainmask */
+		ath_update_chainmask(sc, bss_conf->assoc_ht);
+
+		DPRINTF(sc, ATH_DBG_CONFIG,
+			"%s: bssid %s aid 0x%x\n",
+			__func__,
+			print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
+
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
 			__func__,
 			curchan->center_freq);
 
@@ -776,11 +825,11 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
 
 		/* set h/w channel */
 		if (ath_set_channel(sc, &hchan) < 0)
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: Unable to set channel\n",
 				__func__);
 	} else {
-		DPRINTF(sc, ATH_DEBUG_CONFIG,
+		DPRINTF(sc, ATH_DBG_CONFIG,
 		"%s: Bss Info DISSOC\n", __func__);
 		sc->sc_curaid = 0;
 	}
@@ -794,7 +843,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
 	struct ath_softc *sc = hw->priv;
 
 	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
 			__func__,
 			bss_conf->use_short_preamble);
 		if (bss_conf->use_short_preamble)
@@ -804,7 +853,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
 	}
 
 	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
 			__func__,
 			bss_conf->use_cts_prot);
 		if (bss_conf->use_cts_prot &&
@@ -815,14 +864,14 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
 	}
 
 	if (changed & BSS_CHANGED_HT) {
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed HT %d\n",
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
 			__func__,
 			bss_conf->assoc_ht);
 		ath9k_ht_conf(sc, bss_conf);
 	}
 
 	if (changed & BSS_CHANGED_ASSOC) {
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: BSS Changed ASSOC %d\n",
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
 			__func__,
 			bss_conf->assoc);
 		ath9k_bss_assoc_info(sc, bss_conf);
@@ -861,21 +910,21 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
 	case IEEE80211_AMPDU_RX_START:
 		ret = ath_rx_aggr_start(sc, addr, tid, ssn);
 		if (ret < 0)
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: Unable to start RX aggregation\n",
 				__func__);
 		break;
 	case IEEE80211_AMPDU_RX_STOP:
 		ret = ath_rx_aggr_stop(sc, addr, tid);
 		if (ret < 0)
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: Unable to stop RX aggregation\n",
 				__func__);
 		break;
 	case IEEE80211_AMPDU_TX_START:
 		ret = ath_tx_aggr_start(sc, addr, tid, ssn);
 		if (ret < 0)
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: Unable to start TX aggregation\n",
 				__func__);
 		else
@@ -884,14 +933,14 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
 	case IEEE80211_AMPDU_TX_STOP:
 		ret = ath_tx_aggr_stop(sc, addr, tid);
 		if (ret < 0)
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: Unable to stop TX aggregation\n",
 				__func__);
 
 		ieee80211_stop_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
 		break;
 	default:
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unknown AMPDU action\n", __func__);
 	}
 
@@ -1024,7 +1073,7 @@ void ath_setup_channel_list(struct ath_softc *sc,
 					flags;
 				sc->sbands[IEEE80211_BAND_2GHZ].n_channels++;
 				a++;
-				DPRINTF(sc, ATH_DEBUG_CONFIG,
+				DPRINTF(sc, ATH_DBG_CONFIG,
 					"%s: 2MHz channel: %d, "
 					"channelFlags: 0x%x\n",
 					__func__,
@@ -1051,7 +1100,7 @@ void ath_setup_channel_list(struct ath_softc *sc,
 					flags = flags;
 				sc->sbands[IEEE80211_BAND_5GHZ].n_channels++;
 				b++;
-				DPRINTF(sc, ATH_DEBUG_CONFIG,
+				DPRINTF(sc, ATH_DBG_CONFIG,
 					"%s: 5MHz channel: %d, "
 					"channelFlags: 0x%x\n",
 					__func__,
@@ -1076,14 +1125,6 @@ void ath_get_beaconconfig(struct ath_softc *sc,
 	conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
 }
 
-struct sk_buff *ath_get_beacon(struct ath_softc *sc,
-			       int if_id,
-			       struct ath_beacon_offset *bo,
-			       struct ath_tx_control *txctl)
-{
-	return NULL;
-}
-
 int ath_update_beacon(struct ath_softc *sc,
 		      int if_id,
 		      struct ath_beacon_offset *bo,
@@ -1099,7 +1140,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 	struct ieee80211_hw *hw = sc->hw;
 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
 
-	DPRINTF(sc, ATH_DEBUG_XMIT,
+	DPRINTF(sc, ATH_DBG_XMIT,
 		"%s: TX complete: skb: %p\n", __func__, skb);
 
 	if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
@@ -1225,7 +1266,7 @@ void ath_setup_rate(struct ath_softc *sc,
 		maxrates = rt->rateCount;
 
 	if ((band_2ghz->n_bitrates != 0) && (band_5ghz->n_bitrates != 0)) {
-		DPRINTF(sc, ATH_DEBUG_CONFIG,
+		DPRINTF(sc, ATH_DBG_CONFIG,
 			"%s: Rates already setup\n", __func__);
 		return;
 	}
@@ -1252,7 +1293,7 @@ void ath_setup_rate(struct ath_softc *sc,
 
 	if (band_2ghz->n_bitrates) {
 		for (i = 0; i < band_2ghz->n_bitrates; i++) {
-			DPRINTF(sc, ATH_DEBUG_CONFIG,
+			DPRINTF(sc, ATH_DBG_CONFIG,
 				"%s: 2GHz Rate: %2dMbps, ratecode: %2d\n",
 				__func__,
 				rates_2ghz[i].bitrate / 10,
@@ -1260,7 +1301,7 @@ void ath_setup_rate(struct ath_softc *sc,
 		}
 	} else if (band_5ghz->n_bitrates) {
 		for (i = 0; i < band_5ghz->n_bitrates; i++) {
-			DPRINTF(sc, ATH_DEBUG_CONFIG,
+			DPRINTF(sc, ATH_DBG_CONFIG,
 				"%s: 5Ghz Rate: %2dMbps, ratecode: %2d\n",
 				__func__,
 				rates_5ghz[i].bitrate / 10,
@@ -1273,7 +1314,7 @@ static int ath_detach(struct ath_softc *sc)
 {
 	struct ieee80211_hw *hw = sc->hw;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Detach ATH hw\n", __func__);
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
 
 	/* Unregister hw */
 
@@ -1300,7 +1341,7 @@ static int ath_attach(u_int16_t devid,
 	struct ieee80211_hw *hw = sc->hw;
 	int error = 0;
 
-	DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: Attach ATH hw\n", __func__);
+	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
 
 	error = ath_init(devid, sc);
 	if (error != 0)
@@ -1323,7 +1364,7 @@ static int ath_attach(u_int16_t devid,
 		sc->rates[IEEE80211_BAND_2GHZ];
 	sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
 
-	if (sc->sc_hashtsupport)
+	if (sc->sc_ah->ah_caps.halHTSupport)
 		/* Setup HT capabilities for 2.4Ghz*/
 		setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
 
@@ -1338,7 +1379,7 @@ static int ath_attach(u_int16_t devid,
 		sc->sbands[IEEE80211_BAND_5GHZ].band =
 			IEEE80211_BAND_5GHZ;
 
-		if (sc->sc_hashtsupport)
+		if (sc->sc_ah->ah_caps.halHTSupport)
 			/* Setup HT capabilities for 5Ghz*/
 			setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
 
@@ -1355,7 +1396,7 @@ static int ath_attach(u_int16_t devid,
 	hw->rate_control_algorithm = "ath9k_rate_control";
 	error = ath_rate_control_register();
 	if (error != 0) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unable to register rate control "
 			"algorithm:%d\n", __func__, error);
 		ath_rate_control_unregister();
@@ -1385,26 +1426,6 @@ bad:
 	return error;
 }
 
-static irqreturn_t ath_isr(int irq, void *dev_id)
-{
-	struct ath_softc *sc = dev_id;
-	int sched;
-
-	/* always acknowledge the interrupt */
-	sched = ath_intr(sc);
-
-	switch (sched) {
-	case ATH_ISR_NOSCHED:
-		return IRQ_HANDLED;
-	case ATH_ISR_NOTMINE:
-		return IRQ_NONE;
-	default:
-		tasklet_schedule(&sc->intr_tq);
-		return IRQ_HANDLED;
-
-	}
-}
-
 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	void __iomem *mem;
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/phy.c b/package/ath9k/src/drivers/net/wireless/ath9k/phy.c
index 8baecf1a57..6751bedbff 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/phy.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/phy.c
@@ -14,7 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "ath9k.h"
+#include "core.h"
 #include "hw.h"
 #include "reg.h"
 #include "phy.h"
@@ -28,7 +28,7 @@ ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
 	REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
 }
 
-enum hal_bool
+bool
 ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 {
 	u_int32_t channelSel = 0;
@@ -51,10 +51,10 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 			channelSel = ((freq - 704) * 2 - 3040) / 10;
 			bModeSynth = 1;
 		} else {
-			HDPRINTF(ah, HAL_DBG_CHANNEL,
+			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 				 "%s: invalid channel %u MHz\n", __func__,
 				 freq);
-			return AH_FALSE;
+			return false;
 		}
 
 		channelSel = (channelSel << 2) & 0xff;
@@ -85,9 +85,9 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 		channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
 		aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 	} else {
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u MHz\n", __func__, freq);
-		return AH_FALSE;
+		return false;
 	}
 
 	reg32 =
@@ -100,10 +100,10 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 
 	AH5416(ah)->ah_curchanRadIndex = -1;
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool
+bool
 ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 			    struct hal_channel_internal *chan)
 {
@@ -150,8 +150,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 			refDivA = 1;
 			channelSel = (freq * 0x8000) / 15;
 
-			OS_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
-					 AR_AN_SYNTH9_REFDIVA, refDivA);
+			REG_RMW_FIELD(ah, AR_AN_SYNTH9,
+				      AR_AN_SYNTH9_REFDIVA, refDivA);
 		}
 		if (!fracMode) {
 			ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
@@ -171,7 +171,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 
 	AH5416(ah)->ah_curchanRadIndex = -1;
 
-	return AH_TRUE;
+	return true;
 }
 
 static void
@@ -201,7 +201,7 @@ ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
 	}
 }
 
-enum hal_bool
+bool
 ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
 		     u_int16_t modesIndex)
 {
@@ -213,7 +213,7 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
 	int regWrites = 0;
 
 	if (AR_SREV_9280_10_OR_LATER(ah))
-		return AH_TRUE;
+		return true;
 
 	eepMinorRev = ath9k_hw_get_eeprom(ahp, EEP_MINOR_REV);
 
@@ -266,7 +266,7 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
 	REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data,
 			   regWrites);
 
-	return AH_TRUE;
+	return true;
 }
 
 void
@@ -312,11 +312,11 @@ ath9k_hw_rfdetach(struct ath_hal *ah)
 	}
 }
 
-enum hal_bool
+bool
 ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
 			       struct hal_channel *chans, u_int32_t nchans)
 {
-	enum hal_bool retVal = AH_TRUE;
+	bool retVal = true;
 	int i;
 
 	for (i = 0; i < nchans; i++) {
@@ -327,7 +327,7 @@ ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
 }
 
 
-enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
+bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 
@@ -362,11 +362,11 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 		    || ahp->ah_analogBank6Data == NULL
 		    || ahp->ah_analogBank6TPCData == NULL
 		    || ahp->ah_analogBank7Data == NULL) {
-			HDPRINTF(ah, HAL_DBG_MALLOC,
+			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate RF banks\n",
 				 __func__);
 			*status = HAL_ENOMEM;
-			return AH_FALSE;
+			return false;
 		}
 
 		ahp->ah_addac5416_21 =
@@ -374,26 +374,26 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 			     ahp->ah_iniAddac.ia_rows *
 			     ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
 		if (ahp->ah_addac5416_21 == NULL) {
-			HDPRINTF(ah, HAL_DBG_MALLOC,
+			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate ah_addac5416_21\n",
 				 __func__);
 			*status = HAL_ENOMEM;
-			return AH_FALSE;
+			return false;
 		}
 
 		ahp->ah_bank6Temp =
 		    kzalloc((sizeof(u_int32_t) *
 			     ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 		if (ahp->ah_bank6Temp == NULL) {
-			HDPRINTF(ah, HAL_DBG_MALLOC,
+			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate ah_bank6Temp\n",
 				 __func__);
 			*status = HAL_ENOMEM;
-			return AH_FALSE;
+			return false;
 		}
 	}
 
-	return AH_TRUE;
+	return true;
 }
 
 void
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/phy.h b/package/ath9k/src/drivers/net/wireless/ath9k/phy.h
index 6481944cae..6c05257a03 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/phy.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/phy.h
@@ -17,19 +17,19 @@
 #ifndef PHY_H
 #define PHY_H
 
-enum hal_bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
+bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 					  struct hal_channel_internal
 					  *chan);
-enum hal_bool ath9k_hw_set_channel(struct ath_hal *ah,
+bool ath9k_hw_set_channel(struct ath_hal *ah,
 				   struct hal_channel_internal *chan);
 void ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex,
 			 u_int freqIndex, int regWrites);
-enum hal_bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
+bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
 				   struct hal_channel_internal *chan,
 				   u_int16_t modesIndex);
 void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
 				   struct hal_channel *chan);
-enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah,
+bool ath9k_hw_init_rf(struct ath_hal *ah,
 			       enum hal_status *status);
 
 #define AR_PHY_BASE     0x9800
@@ -518,7 +518,7 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah,
 		int r;							\
 		for (r = 0; r < ((iniarray)->ia_rows); r++) {		\
 			REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
-			HDPRINTF(ah, HAL_DBG_CHANNEL, \
+			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, \
 				"RF 0x%x V 0x%x\n", \
 				INI_RA((iniarray), r, 0), (regData)[r]); \
 			DO_DELAY(regWr);				\
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/rc.c b/package/ath9k/src/drivers/net/wireless/ath9k/rc.c
index ccd599af2a..22b6550c53 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/rc.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/rc.c
@@ -1149,7 +1149,7 @@ void ath_rate_findrate(struct ath_softc *sc,
 {
 	struct ath_vap         *avp = ath_rc_priv->avp;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	if (!num_rates || !num_tries)
 		return;
 
@@ -1652,7 +1652,7 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
 
 	avp = rc_priv->avp;
 	if ((avp->av_config.av_fixed_rateset != IEEE80211_FIXED_RATE_NONE)
-			|| info_priv->tx.ts_status & HAL_TXERR_FILT)
+			|| info_priv->tx.ts_status & ATH9K_TXERR_FILT)
 		return;
 
 	if (info_priv->tx.ts_rssi > 0) {
@@ -1667,14 +1667,14 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
 	 * times. This affects how ratectrl updates PER for the failed rate.
 	 */
 	if (info_priv->tx.ts_flags &
-		(HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN) &&
+		(ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) &&
 		((sc->sc_ah->ah_txTrigLevel) >= tx_triglevel_max)) {
 		tx_status = 1;
 		is_underrun = 1;
 	}
 
-	if ((info_priv->tx.ts_status & HAL_TXERR_XRETRY) ||
-			(info_priv->tx.ts_status & HAL_TXERR_FIFO))
+	if ((info_priv->tx.ts_status & ATH9K_TXERR_XRETRY) ||
+			(info_priv->tx.ts_status & ATH9K_TXERR_FIFO))
 		tx_status = 1;
 
 	ath_rc_update(sc, rc_priv, info_priv, final_ts_idx, tx_status,
@@ -1822,7 +1822,7 @@ static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta)
 	struct ath_rate_node *rc_priv = sta->rate_ctrl_priv;
 	int i, j = 0;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	sband =  local->hw.wiphy->bands[local->hw.conf.channel->band];
 	for (i = 0; i < sband->n_bitrates; i++) {
 		if (sta->supp_rates[local->hw.conf.channel->band] & BIT(i)) {
@@ -1920,7 +1920,7 @@ static void ath_tx_aggr_resp(struct ath_softc *sc,
 		txtid->addba_exchangeinprogress = 0;
 		txtid->baw_size = buffersize;
 
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Resuming tid, buffersize: %d\n",
 			__func__,
 			buffersize);
@@ -1949,7 +1949,7 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 	u8 *qc, tid;
 	DECLARE_MAC_BUF(mac);
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s\n", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
 
 	/* allocate driver private area of tx_info */
 	tx_info->driver_data[0] = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
@@ -1974,8 +1974,8 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 			  ATH_RC_PROBE_ALLOWED,
 			  tx_info_priv->rcs,
 			  &is_probe,
-			  AH_FALSE);
-	if (is_probe == AH_TRUE)
+			  false);
+	if (is_probe)
 		sel->probe_idx = ((struct ath_tx_ratectrl *)
 			sta->rate_ctrl_priv)->probe_rate;
 
@@ -1999,7 +1999,7 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 			spin_unlock_bh(&sc->node_lock);
 
 			if (!an) {
-				DPRINTF(sc, ATH_DEBUG_AGGR,
+				DPRINTF(sc, ATH_DBG_AGGR,
 					"%s: Node not found to "
 					"init/chk TX aggr\n", __func__);
 				return;
@@ -2010,13 +2010,13 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 				ret = ieee80211_start_tx_ba_session(hw,
 					hdr->addr1, tid);
 				if (ret)
-					DPRINTF(sc, ATH_DEBUG_AGGR,
+					DPRINTF(sc, ATH_DBG_AGGR,
 						"%s: Unable to start tx "
 						"aggr for: %s\n",
 						__func__,
 						print_mac(mac, hdr->addr1));
 				else
-					DPRINTF(sc, ATH_DEBUG_AGGR,
+					DPRINTF(sc, ATH_DBG_AGGR,
 						"%s: Started tx aggr for: %s\n",
 						__func__,
 						print_mac(mac, hdr->addr1));
@@ -2034,21 +2034,15 @@ static void ath_rate_init(void *priv, void *priv_sta,
 	struct ieee80211_hw *hw = local_to_hw(local);
 	struct ieee80211_conf *conf = &local->hw.conf;
 	struct ath_softc *sc = hw->priv;
-	struct hal_channel hchan;
 	int i, j = 0;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
 
 	sband = local->hw.wiphy->bands[local->hw.conf.channel->band];
 	sta->txrate_idx = rate_lowest_index(local, sband, sta);
 
-	hchan.channel = conf->channel->center_freq;
-	hchan.channelFlags = ath_chan2flags(conf->channel, sc);
-	if (ath_set_channel(sc, &hchan) < 0)
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: Unable to set channel\n",
-			__func__);
 	ath_setup_rates(local, sta);
-	if (conf->flags&IEEE80211_CONF_SUPPORT_HT_MODE) {
+	if (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) {
 		for (i = 0; i < MCS_SET_SIZE; i++) {
 			if (conf->ht_conf.supp_mcs_set[i/8] & (1<<(i%8)))
 				((struct ath_rate_node *)
@@ -2071,7 +2065,7 @@ static void *ath_rate_alloc(struct ieee80211_local *local)
 	struct ieee80211_hw *hw = local_to_hw(local);
 	struct ath_softc *sc = hw->priv;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	return local->hw.priv;
 }
 
@@ -2086,10 +2080,10 @@ static void *ath_rate_alloc_sta(void *priv, gfp_t gfp)
 	struct ath_vap *avp = sc->sc_vaps[0];
 	struct ath_rate_node *rate_priv;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	rate_priv = ath_rate_node_alloc(avp, sc->sc_rc, gfp);
 	if (!rate_priv) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s:Unable to allocate"
+		DPRINTF(sc, ATH_DBG_FATAL, "%s:Unable to allocate"
 				"private rate control structure", __func__);
 		return NULL;
 	}
@@ -2102,7 +2096,7 @@ static void ath_rate_free_sta(void *priv, void *priv_sta)
 	struct ath_rate_node *rate_priv = priv_sta;
 	struct ath_softc *sc = priv;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	ath_rate_node_free(rate_priv);
 }
 
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/recv.c b/package/ath9k/src/drivers/net/wireless/ath9k/recv.c
index f16b356bd9..6aefe59f42 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/recv.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/recv.c
@@ -80,7 +80,7 @@ static int ath_bar_rx(struct ath_softc *sc,
 	/* look at BAR contents	 */
 
 	bar = (struct ieee80211_bar *)skb->data;
-	tidno = (bar->control & IEEE80211_BAR_CTL_TID_M)
+	tidno = (le16_to_cpu(bar->control) & IEEE80211_BAR_CTL_TID_M)
 		>> IEEE80211_BAR_CTL_TID_S;
 	seqno = le16_to_cpu(bar->start_seq_num) >> IEEE80211_SEQ_SEQ_SHIFT;
 
@@ -385,60 +385,6 @@ static void ath_rx_flush_tid(struct ath_softc *sc,
 	spin_unlock_bh(&rxtid->tidlock);
 }
 
-static u_int8_t ath_rx_detect_antenna(struct ath_softc *sc,
-	struct ath_rx_status *rxstat)
-{
-#define ATH_RX_CHAINMASK_CLR(_chainmask, _chain) \
-	((_chainmask) &= ~(1 << (_chain)))
-	u_int8_t rx_chainmask = sc->sc_rx_chainmask;
-	int rssiRef, detectThresh, detectDelta;
-
-	if (IS_CHAN_5GHZ(&sc->sc_curchan)) {
-		detectThresh = sc->sc_rxchaindetect_thresh5GHz;
-		detectDelta = sc->sc_rxchaindetect_delta5GHz;
-	} else {
-		detectThresh = sc->sc_rxchaindetect_thresh2GHz;
-		detectDelta = sc->sc_rxchaindetect_delta2GHz;
-	}
-
-	switch (sc->sc_rxchaindetect_ref) {
-	case 0:
-		rssiRef = rxstat->rs_rssi;
-		if (rssiRef < detectThresh)
-			return 0;
-
-		if (rssiRef - rxstat->rs_rssi_ctl1 > detectDelta)
-			ATH_RX_CHAINMASK_CLR(rx_chainmask, 1);
-
-		if (rssiRef - rxstat->rs_rssi_ctl2 > detectDelta)
-			ATH_RX_CHAINMASK_CLR(rx_chainmask, 2);
-
-		break;
-	case 1:
-		rssiRef = rxstat->rs_rssi_ctl1;
-		if (rssiRef < detectThresh)
-			return 0;
-
-		if (rssiRef - rxstat->rs_rssi_ctl2 > detectDelta)
-			ATH_RX_CHAINMASK_CLR(rx_chainmask, 2);
-
-		break;
-	case 2:
-		rssiRef = rxstat->rs_rssi_ctl2;
-		if (rssiRef < detectThresh)
-			return 0;
-
-		if (rssiRef - rxstat->rs_rssi_ctl1 > detectDelta)
-			ATH_RX_CHAINMASK_CLR(rx_chainmask, 1);
-
-		break;
-	}
-
-	return rx_chainmask;
-#undef IS_CHAN_5GHZ
-#undef ATH_RX_CHAINMASK_CLR
-}
-
 static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
 	u_int32_t len)
 {
@@ -457,7 +403,7 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
 		if (off != 0)
 			skb_reserve(skb, sc->sc_cachelsz - off);
 	} else {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: skbuff alloc of size %u failed\n",
 			__func__, len);
 		return NULL;
@@ -532,7 +478,7 @@ static void ath_opmode_init(struct ath_softc *sc)
 	ath9k_hw_setrxfilter(ah, rfilt);
 
 	/* configure bssid mask */
-	if (sc->sc_hasbmask)
+	if (ah->ah_caps.halBssIdMaskSupport)
 		ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
 
 	/* configure operational mode */
@@ -545,7 +491,7 @@ static void ath_opmode_init(struct ath_softc *sc)
 	mfilt[0] = mfilt[1] = ~0;
 
 	ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
-	DPRINTF(sc, ATH_DEBUG_RECV ,
+	DPRINTF(sc, ATH_DBG_CONFIG ,
 		"%s: RX filter 0x%x, MC filter %08x:%08x\n",
 		__func__, rfilt, mfilt[0], mfilt[1]);
 }
@@ -571,7 +517,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
 					   min(sc->sc_cachelsz,
 					       (u_int16_t)64));
 
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
 			__func__, sc->sc_cachelsz, sc->sc_rxbufsize);
 
 		/* Initialize rx descriptors */
@@ -579,7 +525,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
 		error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
 					  "rx", nbufs, 1);
 		if (error != 0) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: failed to allocate rx descriptors: %d\n",
 				__func__, error);
 			break;
@@ -669,7 +615,7 @@ u_int32_t ath_calcrxfilter(struct ath_softc *sc)
 	}
 
 	if (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS ||
-	    sc->sc_nostabeacons || sc->sc_scanning)
+	    sc->sc_scanning)
 		rfilt |= HAL_RX_FILTER_BEACON;
 
 	/* If in HOSTAP mode, want to enable reception of PSPOLL frames
@@ -728,11 +674,11 @@ start_recv:
 
 /* Disable the receive h/w in preparation for a reset. */
 
-enum hal_bool ath_stoprecv(struct ath_softc *sc)
+bool ath_stoprecv(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	u_int64_t tsf;
-	enum hal_bool stopped;
+	bool stopped;
 
 	ath9k_hw_stoppcurecv(ah);	/* disable PCU */
 	ath9k_hw_setrxfilter(ah, 0);	/* clear recv filter */
@@ -798,12 +744,10 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 	struct ath_hal *ah = sc->sc_ah;
 	int type, rx_processed = 0;
 	u_int phyerr;
-	u_int8_t rxchainmask, chainreset = 0;
+	u_int8_t chainreset = 0;
 	enum hal_status retval;
 	__le16 fc;
 
-	DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s\n", __func__);
-
 	do {
 		/* If handling rx interrupt and flush is in progress => exit */
 		if (sc->sc_rxflush && (flush == 0))
@@ -961,14 +905,14 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 #endif
 			/* fall thru for monitor mode handling... */
 		} else if (ds->ds_rxstat.rs_status != 0) {
-			if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
+			if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
 				rx_status.flags |= ATH_RX_FCS_ERROR;
-			if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
+			if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) {
 				phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
 				goto rx_next;
 			}
 
-			if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
+			if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
 				/*
 				 * Decrypt error. We only mark packet status
 				 * here and always push up the frame up to let
@@ -977,7 +921,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 				 * error. This let us keep statistics there.
 				 */
 				rx_status.flags |= ATH_RX_DECRYPT_ERROR;
-			} else if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
+			} else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
 				/*
 				 * Demic error. We only mark frame status here
 				 * and always push up the frame up to let
@@ -992,7 +936,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 					 * Remove these mic errors.
 					 */
 					ds->ds_rxstat.rs_status &=
-						~HAL_RXERR_MIC;
+						~ATH9K_RXERR_MIC;
 				else
 					rx_status.flags |= ATH_RX_MIC_ERROR;
 			}
@@ -1003,12 +947,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 			 */
 			if (sc->sc_opmode == HAL_M_MONITOR) {
 				if (ds->ds_rxstat.rs_status &
-				    ~(HAL_RXERR_DECRYPT | HAL_RXERR_MIC |
-					HAL_RXERR_CRC))
+				    ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
+					ATH9K_RXERR_CRC))
 					goto rx_next;
 			} else {
 				if (ds->ds_rxstat.rs_status &
-				    ~(HAL_RXERR_DECRYPT | HAL_RXERR_MIC)) {
+				    ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
 					goto rx_next;
 				}
 			}
@@ -1026,7 +970,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 		 * to receive another frame.
 		 */
 		skb_put(skb, ds->ds_rxstat.rs_datalen);
-		skb->protocol = ETH_P_CONTROL;
+		skb->protocol = cpu_to_be16(ETH_P_CONTROL);
 		rx_status.tsf = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
 		rx_status.rateieee =
 			sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate;
@@ -1037,12 +981,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 		/* HT rate */
 		if (rx_status.ratecode & 0x80) {
 			/* TODO - add table to avoid division */
-			if (ds->ds_rxstat.rs_flags & HAL_RX_2040) {
+			if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
 				rx_status.flags |= ATH_RX_40MHZ;
 				rx_status.rateKbps =
 					(rx_status.rateKbps * 27) / 13;
 			}
-			if (ds->ds_rxstat.rs_flags & HAL_RX_GI)
+			if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
 				rx_status.rateKbps =
 					(rx_status.rateKbps * 10) / 9;
 			else
@@ -1074,7 +1018,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 				 PCI_DMA_FROMDEVICE);
 
 		/* XXX: Ah! make me more readable, use a helper */
-		if (sc->sc_hashtsupport) {
+		if (ah->ah_caps.halHTSupport) {
 			if (ds->ds_rxstat.rs_moreaggr == 0) {
 				rx_status.rssictl[0] =
 					ds->ds_rxstat.rs_rssi_ctl0;
@@ -1083,7 +1027,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 				rx_status.rssictl[2] =
 					ds->ds_rxstat.rs_rssi_ctl2;
 				rx_status.rssi = ds->ds_rxstat.rs_rssi;
-				if (ds->ds_rxstat.rs_flags & HAL_RX_2040) {
+				if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
 					rx_status.rssiextn[0] =
 						ds->ds_rxstat.rs_rssi_ext0;
 					rx_status.rssiextn[1] =
@@ -1110,41 +1054,20 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 		type = ath_rx_indicate(sc, skb,
 			&rx_status, ds->ds_rxstat.rs_keyix);
 
-		if (sc->sc_diversity) {
-			/*
-			 * When using hardware fast diversity, change the
-			 * default rx antenna if rx diversity chooses the
-			 * other antenna 3 times in a row.
-			 */
-			if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
-				if (++sc->sc_rxotherant >= 3)
-					ath_setdefantenna(sc,
-						  ds->ds_rxstat.rs_antenna);
-			} else {
-				sc->sc_rxotherant = 0;
-			}
-		}
 		/*
-		 * redo antenna detection for Lenovo devices
+		 * change the default rx antenna if rx diversity chooses the
+		 * other antenna 3 times in a row.
 		 */
-		if (sc->sc_rx_chainmask_detect && sc->sc_rx_chainmask_start) {
-			rxchainmask = ath_rx_detect_antenna(sc, &ds->ds_rxstat);
-			if (rxchainmask) {
-				sc->sc_rx_chainmask_detect = 0;
-				sc->sc_rx_chainmask_start  = 0;
-				if (sc->sc_rx_chainmask != rxchainmask) {
-					sc->sc_rx_chainmask = rxchainmask;
-
-					/* we have to do an reset to
-					 * change chain mask */
-					chainreset = 1;
-				}
-			}
+		if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
+			if (++sc->sc_rxotherant >= 3)
+				ath_setdefantenna(sc,
+						ds->ds_rxstat.rs_antenna);
+		} else {
+			sc->sc_rxotherant = 0;
 		}
 
 #ifdef CONFIG_SLOW_ANT_DIV
-		if (sc->sc_slowAntDiv &&
-		    (rx_status.flags & ATH_RX_RSSI_VALID) &&
+		if ((rx_status.flags & ATH_RX_RSSI_VALID) &&
 		    ieee80211_is_beacon(fc)) {
 			ath_slow_ant_div(&sc->sc_antdiv, hdr, &ds->ds_rxstat);
 		}
@@ -1162,7 +1085,7 @@ rx_next:
 	} while (TRUE);
 
 	if (chainreset) {
-		DPRINTF(sc, ATH_DEBUG_CONFIG,
+		DPRINTF(sc, ATH_DBG_CONFIG,
 			"%s: Reset rx chain mask. "
 			"Do internal reset\n", __func__);
 		ASSERT(flush == 0);
@@ -1191,7 +1114,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 	spin_unlock_bh(&sc->node_lock);
 
 	if (!an) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Node not found to initialize RX aggregation\n",
 			__func__);
 		return -1;
@@ -1216,7 +1139,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 		rxtid->seq_next = *ssn;
 
 		/* Allocate the receive buffers for this TID */
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Allcating rxbuffer for TID %d\n", __func__, tid);
 
 		if (rxtid->rxbuf == NULL) {
@@ -1231,7 +1154,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 				sizeof(struct ath_rxbuf), GFP_ATOMIC);
 		}
 		if (rxtid->rxbuf == NULL) {
-			DPRINTF(sc, ATH_DEBUG_AGGR,
+			DPRINTF(sc, ATH_DBG_AGGR,
 				"%s: Unable to allocate RX buffer, "
 				"refusing ADDBA\n", __func__);
 		} else {
@@ -1239,7 +1162,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 			 * pointers are null) */
 			memzero(rxtid->rxbuf, ATH_TID_MAX_BUFS *
 				sizeof(struct ath_rxbuf));
-			DPRINTF(sc, ATH_DEBUG_AGGR,
+			DPRINTF(sc, ATH_DBG_AGGR,
 				"%s: Allocated @%p\n", __func__, rxtid->rxbuf);
 
 			/* Allow aggregation reception */
@@ -1264,7 +1187,7 @@ int ath_rx_aggr_stop(struct ath_softc *sc,
 	spin_unlock_bh(&sc->node_lock);
 
 	if (!an) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: RX aggr stop for non-existent node\n", __func__);
 		return -1;
 	}
@@ -1290,7 +1213,7 @@ void ath_rx_aggr_teardown(struct ath_softc *sc,
 	/* De-allocate the receive buffer array allocated when addba started */
 
 	if (rxtid->rxbuf) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Deallocating TID %d rxbuff @%p\n",
 			__func__, tid, rxtid->rxbuf);
 		kfree(rxtid->rxbuf);
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/regd.c b/package/ath9k/src/drivers/net/wireless/ath9k/regd.c
index 519cae8775..8a99365abe 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/regd.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/regd.c
@@ -16,7 +16,7 @@
 
 #include <linux/kernel.h>
 #include <linux/slab.h>
-#include "ath9k.h"
+#include "core.h"
 #include "regd.h"
 #include "regd_common.h"
 
@@ -50,18 +50,18 @@ static u_int16_t ath9k_regd_get_eepromRD(struct ath_hal *ah)
 	return ah->ah_currentRD & ~WORLDWIDE_ROAMING_FLAG;
 }
 
-static enum hal_bool ath9k_regd_is_chan_bm_zero(u_int64_t *bitmask)
+static bool ath9k_regd_is_chan_bm_zero(u_int64_t *bitmask)
 {
 	int i;
 
 	for (i = 0; i < BMLEN; i++) {
 		if (bitmask[i] != 0)
-			return AH_FALSE;
+			return false;
 	}
-	return AH_TRUE;
+	return true;
 }
 
-static enum hal_bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
+static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
 {
 	u_int16_t rd = ath9k_regd_get_eepromRD(ah);
 	int i;
@@ -70,52 +70,49 @@ static enum hal_bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
 		u_int16_t cc = rd & ~COUNTRY_ERD_FLAG;
 		for (i = 0; i < ARRAY_SIZE(allCountries); i++)
 			if (allCountries[i].countryCode == cc)
-				return AH_TRUE;
+				return true;
 	} else {
 		for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++)
 			if (regDomainPairs[i].regDmnEnum == rd)
-				return AH_TRUE;
+				return true;
 	}
-	HDPRINTF(ah, HAL_DBG_REGULATORY,
+	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 		 "%s: invalid regulatory domain/country code 0x%x\n",
 		 __func__, rd);
-	return AH_FALSE;
+	return false;
 }
 
-static enum hal_bool ath9k_regd_is_fcc_midband_supported(struct ath_hal
-							 *ah)
+static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
 {
 	u_int32_t regcap;
 
 	regcap = ah->ah_caps.halRegCap;
 
 	if (regcap & AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND)
-		return AH_TRUE;
+		return true;
 	else
-		return AH_FALSE;
+		return false;
 }
 
-static enum hal_bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
-					       u_int16_t cc)
+static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
+				      u_int16_t cc)
 {
 	u_int16_t rd;
 	int i;
 
 	if (cc == CTRY_DEFAULT)
-		return AH_TRUE;
-#ifdef AH_DEBUG_COUNTRY
+		return true;
 	if (cc == CTRY_DEBUG)
-		return AH_TRUE;
-#endif
+		return true;
+
 	rd = ath9k_regd_get_eepromRD(ah);
-	HDPRINTF(ah, HAL_DBG_REGULATORY, "%s: EEPROM regdomain 0x%x\n",
+	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: EEPROM regdomain 0x%x\n",
 		 __func__, rd);
 
 	if (rd & COUNTRY_ERD_FLAG) {
-
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
-			 "%s: EEPROM setting is country code %u\n",
-			 __func__, rd & ~COUNTRY_ERD_FLAG);
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: EEPROM setting is country code %u\n",
+			__func__, rd & ~COUNTRY_ERD_FLAG);
 		return cc == (rd & ~COUNTRY_ERD_FLAG);
 	}
 
@@ -123,14 +120,14 @@ static enum hal_bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
 		if (cc == allCountries[i].countryCode) {
 #ifdef AH_SUPPORT_11D
 			if ((rd & WORLD_SKU_MASK) == WORLD_SKU_PREFIX)
-				return AH_TRUE;
+				return true;
 #endif
 			if (allCountries[i].regDmnEnum == rd ||
 			    rd == DEBUG_REG_DMN || rd == NO_ENUMRD)
-				return AH_TRUE;
+				return true;
 		}
 	}
-	return AH_FALSE;
+	return false;
 }
 
 static u_int
@@ -175,7 +172,7 @@ ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
 	return modesAvail;
 }
 
-enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
+bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
 {
 	u_int16_t rd;
 
@@ -184,18 +181,18 @@ enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
 	switch (rd) {
 	case FCC4_FCCA:
 	case (CTRY_UNITED_STATES_FCC49 | COUNTRY_ERD_FLAG):
-		return AH_TRUE;
+		return true;
 	case DEBUG_REG_DMN:
 	case NO_ENUMRD:
 		if (ah->ah_countryCode == CTRY_UNITED_STATES_FCC49)
-			return AH_TRUE;
+			return true;
 		break;
 	}
-	return AH_FALSE;
+	return false;
 }
 
-static struct country_code_to_enum_rd *ath9k_regd_find_country(u_int16_t
-							       countryCode)
+static struct country_code_to_enum_rd*
+ath9k_regd_find_country(u_int16_t countryCode)
 {
 	int i;
 
@@ -231,8 +228,8 @@ static u_int16_t ath9k_regd_get_default_country(struct ath_hal *ah)
 	return CTRY_DEFAULT;
 }
 
-static enum hal_bool ath9k_regd_is_valid_reg_domain(int regDmn,
-						    struct regDomain *rd)
+static bool ath9k_regd_is_valid_reg_domain(int regDmn,
+					   struct regDomain *rd)
 {
 	int i;
 
@@ -242,26 +239,26 @@ static enum hal_bool ath9k_regd_is_valid_reg_domain(int regDmn,
 				memcpy(rd, &regDomains[i],
 				       sizeof(struct regDomain));
 			}
-			return AH_TRUE;
+			return true;
 		}
 	}
-	return AH_FALSE;
+	return false;
 }
 
-static enum hal_bool ath9k_regd_is_valid_reg_domainPair(int regDmnPair)
+static bool ath9k_regd_is_valid_reg_domainPair(int regDmnPair)
 {
 	int i;
 
 	if (regDmnPair == NO_ENUMRD)
-		return AH_FALSE;
+		return false;
 	for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) {
 		if (regDomainPairs[i].regDmnEnum == regDmnPair)
-			return AH_TRUE;
+			return true;
 	}
-	return AH_FALSE;
+	return false;
 }
 
-static enum hal_bool
+static bool
 ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 			       u_int16_t channelFlag, struct regDomain *rd)
 {
@@ -284,7 +281,6 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 	}
 
 	if ((regDmn & MULTI_DOMAIN_MASK) == 0) {
-
 		for (i = 0, found = 0;
 		     (i < ARRAY_SIZE(regDomainPairs)) && (!found); i++) {
 			if (regDomainPairs[i].regDmnEnum == regDmn) {
@@ -293,10 +289,10 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 			}
 		}
 		if (!found) {
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
-				 "%s: Failed to find reg domain pair %u\n",
-				 __func__, regDmn);
-			return AH_FALSE;
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+				"%s: Failed to find reg domain pair %u\n",
+				__func__, regDmn);
+			return false;
 		}
 		if (!(channelFlag & CHANNEL_2GHZ)) {
 			regDmn = regPair->regDmn5GHz;
@@ -310,10 +306,10 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 
 	found = ath9k_regd_is_valid_reg_domain(regDmn, rd);
 	if (!found) {
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
-			 "%s: Failed to find unitary reg domain %u\n",
-			 __func__, regDmn);
-		return AH_FALSE;
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: Failed to find unitary reg domain %u\n",
+			__func__, regDmn);
+		return false;
 	} else {
 		rd->pscan &= regPair->pscanMask;
 		if (((regOrg & MULTI_DOMAIN_MASK) == 0) &&
@@ -323,11 +319,11 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 
 		rd->flags &= (channelFlag & CHANNEL_2GHZ) ?
 		    REG_DOMAIN_2GHZ_MASK : REG_DOMAIN_5GHZ_MASK;
-		return AH_TRUE;
+		return true;
 	}
 }
 
-static enum hal_bool ath9k_regd_is_bit_set(int bit, u_int64_t *bitmask)
+static bool ath9k_regd_is_bit_set(int bit, u_int64_t *bitmask)
 {
 	int byteOffset, bitnum;
 	u_int64_t val;
@@ -336,9 +332,9 @@ static enum hal_bool ath9k_regd_is_bit_set(int bit, u_int64_t *bitmask)
 	bitnum = bit - byteOffset * 64;
 	val = ((u_int64_t) 1) << bitnum;
 	if (bitmask[byteOffset] & val)
-		return AH_TRUE;
+		return true;
 	else
-		return AH_FALSE;
+		return false;
 }
 
 static void
@@ -367,11 +363,11 @@ ath9k_regd_add_reg_classid(u_int8_t *regclassids, u_int maxregids,
 	return;
 }
 
-static enum hal_bool
+static bool
 ath9k_regd_get_eeprom_reg_ext_bits(struct ath_hal *ah,
 				   enum reg_ext_bitmap bit)
 {
-	return (ah->ah_currentRDExt & (1 << bit)) ? AH_TRUE : AH_FALSE;
+	return (ah->ah_currentRDExt & (1 << bit)) ? true : false;
 }
 
 #ifdef ATH_NF_PER_CHAN
@@ -397,13 +393,193 @@ static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
 }
 #endif
 
-enum hal_bool
+static bool
+ath9k_regd_add_channel(struct ath_hal *ah,
+		       u_int16_t c,
+		       u_int16_t c_lo,
+		       u_int16_t c_hi,
+		       u_int16_t maxChan,
+		       u_int8_t ctl,
+		       int pos,
+		       struct regDomain rd5GHz,
+		       struct RegDmnFreqBand *fband,
+		       struct regDomain *rd,
+		       const struct cmode *cm,
+		       struct hal_channel_internal *ichans,
+		       bool enableExtendedChannels)
+{
+	struct hal_channel_internal icv;
+
+	if (!(c_lo <= c && c <= c_hi)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: c %u out of range [%u..%u]\n",
+			__func__, c, c_lo, c_hi);
+		return false;
+	}
+	if ((fband->channelBW == CHANNEL_HALF_BW) &&
+	    !ah->ah_caps.halChanHalfRate) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: Skipping %u half rate channel\n",
+			__func__, c);
+		return false;
+	}
+
+	if ((fband->channelBW == CHANNEL_QUARTER_BW) &&
+	    !ah->ah_caps.halChanQuarterRate) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: Skipping %u quarter rate channel\n",
+			__func__, c);
+		return false;
+	}
+
+	if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: c %u > maxChan %u\n",
+			__func__, c, maxChan);
+		return false;
+	}
+
+	if ((fband->usePassScan & IS_ECM_CHAN) && !enableExtendedChannels) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping ecm channel\n");
+		return false;
+	}
+
+	if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == HAL_M_HOSTAP)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HOSTAP channel\n");
+		return false;
+	}
+
+	if (IS_HT40_MODE(cm->mode) &&
+	    !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_FCC_DFS_HT40)) &&
+	    (fband->useDfs) &&
+	    (rd->conformanceTestLimit != MKK)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HT40 channel (en_fcc_dfs_ht40 = 0)\n");
+		return false;
+	}
+
+	if (IS_HT40_MODE(cm->mode) &&
+	    !(ath9k_regd_get_eeprom_reg_ext_bits(ah,
+						 REG_EXT_JAPAN_NONDFS_HT40)) &&
+	    !(fband->useDfs) && (rd->conformanceTestLimit == MKK)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HT40 channel (en_jap_ht40 = 0)\n");
+		return false;
+	}
+
+	if (IS_HT40_MODE(cm->mode) &&
+	    !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_JAPAN_DFS_HT40)) &&
+	    (fband->useDfs) &&
+	    (rd->conformanceTestLimit == MKK)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HT40 channel (en_jap_dfs_ht40 = 0)\n");
+		return false;
+	}
+
+	memset(&icv, 0, sizeof(icv));
+	icv.channel = c;
+	icv.channelFlags = cm->flags;
+
+	switch (fband->channelBW) {
+	case CHANNEL_HALF_BW:
+		icv.channelFlags |= CHANNEL_HALF;
+		break;
+	case CHANNEL_QUARTER_BW:
+		icv.channelFlags |= CHANNEL_QUARTER;
+		break;
+	}
+
+	icv.maxRegTxPower = fband->powerDfs;
+	icv.antennaMax = fband->antennaMax;
+	icv.regDmnFlags = rd->flags;
+	icv.conformanceTestLimit = ctl;
+	if (fband->usePassScan & rd->pscan)
+		icv.channelFlags |= CHANNEL_PASSIVE;
+	else
+		icv.channelFlags &= ~CHANNEL_PASSIVE;
+	if (fband->useDfs & rd->dfsMask)
+		icv.privFlags = CHANNEL_DFS;
+	else
+		icv.privFlags = 0;
+	if (rd->flags & LIMIT_FRAME_4MS)
+		icv.privFlags |= CHANNEL_4MS_LIMIT;
+	if (icv.privFlags & CHANNEL_DFS)
+		icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+	if (icv.regDmnFlags & ADHOC_PER_11D)
+		icv.privFlags |= CHANNEL_PER_11D_ADHOC;
+
+	if (icv.channelFlags & CHANNEL_PASSIVE) {
+		if ((icv.channel < 2412) || (icv.channel > 2462)) {
+			if (rd5GHz.regDmnEnum == MKK1 ||
+			    rd5GHz.regDmnEnum == MKK2) {
+				u_int32_t regcap = ah->ah_caps.halRegCap;
+				if (!(regcap &
+				      (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
+				       AR_EEPROM_EEREGCAP_EN_KK_U2 |
+				       AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) &&
+				    isUNII1OddChan(icv.channel)) {
+					icv.channelFlags &= ~CHANNEL_PASSIVE;
+				} else {
+					icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+				}
+			} else {
+				icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+			}
+		}
+	}
+
+	if (cm->mode & (ATH9K_MODE_SEL_11A |
+			ATH9K_MODE_SEL_11NA_HT20 |
+			ATH9K_MODE_SEL_11NA_HT40PLUS |
+			ATH9K_MODE_SEL_11NA_HT40MINUS)) {
+		if (icv.regDmnFlags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A))
+			icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+	}
+
+	memcpy(&ichans[pos], &icv,
+	       sizeof(struct hal_channel_internal));
+
+	return true;
+}
+
+static bool ath9k_regd_japan_check(struct ath_hal *ah,
+				   int b,
+				   struct regDomain *rd5GHz)
+{
+	bool skipband = false;
+	int i;
+	u_int32_t regcap;
+
+	for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
+		if (j_bandcheck[i].freqbandbit == b) {
+			regcap = ah->ah_caps.halRegCap;
+			if ((j_bandcheck[i].eepromflagtocheck & regcap) == 0) {
+				skipband = true;
+			} else if ((regcap & AR_EEPROM_EEREGCAP_EN_KK_U2) ||
+				  (regcap & AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) {
+				rd5GHz->dfsMask |= DFS_MKK4;
+				rd5GHz->pscan |= PSCAN_MKK3;
+			}
+			break;
+		}
+	}
+
+	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+		"%s: Skipping %d freq band\n",
+		__func__, j_bandcheck[i].freqbandbit);
+
+	return skipband;
+}
+
+bool
 ath9k_regd_init_channels(struct ath_hal *ah,
 			 struct hal_channel *chans, u_int maxchans,
 			 u_int *nchans, u_int8_t *regclassids,
 			 u_int maxregids, u_int *nregids, u_int16_t cc,
-			 u_int32_t modeSelect, enum hal_bool enableOutdoor,
-			 enum hal_bool enableExtendedChannels)
+			 u_int32_t modeSelect, bool enableOutdoor,
+			 bool enableExtendedChannels)
 {
 	u_int modesAvail;
 	u_int16_t maxChan = 7000;
@@ -413,41 +589,36 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 	struct hal_channel_internal *ichans = &ah->ah_channels[0];
 	int next = 0, b;
 	u_int8_t ctl;
-	int is_quarterchan_cap, is_halfchan_cap;
 	int regdmn;
 	u_int16_t chanSep;
 
-	HDPRINTF(ah, HAL_DBG_REGULATORY, "%s: cc %u mode 0x%x%s%s\n",
+	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: cc %u mode 0x%x%s%s\n",
 		 __func__, cc, modeSelect,
 		 enableOutdoor ? " Enable outdoor" : " ",
 		 enableExtendedChannels ? " Enable ecm" : "");
 
 	if (!ath9k_regd_is_ccode_valid(ah, cc)) {
-
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
-			 "%s: invalid country code %d\n", __func__, cc);
-		return AH_FALSE;
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: invalid country code %d\n", __func__, cc);
+		return false;
 	}
 
 	if (!ath9k_regd_is_eeprom_valid(ah)) {
-
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
-			 "%s: invalid EEPROM contents\n", __func__);
-		return AH_FALSE;
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: invalid EEPROM contents\n", __func__);
+		return false;
 	}
 
 	ah->ah_countryCode = ath9k_regd_get_default_country(ah);
 
 	if (ah->ah_countryCode == CTRY_DEFAULT) {
-
 		ah->ah_countryCode = cc & COUNTRY_CODE_MASK;
-
 		if ((ah->ah_countryCode == CTRY_DEFAULT) &&
 		    (ath9k_regd_get_eepromRD(ah) == CTRY_DEFAULT)) {
-
 			ah->ah_countryCode = CTRY_UNITED_STATES;
 		}
 	}
+
 #ifdef AH_SUPPORT_11D
 	if (ah->ah_countryCode == CTRY_DEFAULT) {
 		regdmn = ath9k_regd_get_eepromRD(ah);
@@ -455,22 +626,19 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 	} else {
 #endif
 		country = ath9k_regd_find_country(ah->ah_countryCode);
-
 		if (country == NULL) {
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
-				 "Country is NULL!!!!, cc= %d\n",
-				 ah->ah_countryCode);
-			return AH_FALSE;
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+				"Country is NULL!!!!, cc= %d\n",
+				ah->ah_countryCode);
+			return false;
 		} else {
 			regdmn = country->regDmnEnum;
 #ifdef AH_SUPPORT_11D
-			if (((ath9k_regd_get_eepromRD(ah) & WORLD_SKU_MASK)
-			     == WORLD_SKU_PREFIX)
-			    && (cc == CTRY_UNITED_STATES)) {
+			if (((ath9k_regd_get_eepromRD(ah) &
+			      WORLD_SKU_MASK) == WORLD_SKU_PREFIX) &&
+			    (cc == CTRY_UNITED_STATES)) {
 				if (!isWwrSKU_NoMidband(ah)
-				    &&
-				    ath9k_regd_is_fcc_midband_supported
-				    (ah))
+				    && ath9k_regd_is_fcc_midband_supported(ah))
 					regdmn = FCC3_FCCA;
 				else
 					regdmn = FCC1_FCCA;
@@ -480,36 +648,39 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 #ifdef AH_SUPPORT_11D
 	}
 #endif
-
-	if (!ath9k_regd_get_wmode_regdomain
-	    (ah, regdmn, ~CHANNEL_2GHZ, &rd5GHz)) {
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
+	if (!ath9k_regd_get_wmode_regdomain(ah,
+					    regdmn,
+					    ~CHANNEL_2GHZ,
+					    &rd5GHz)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 			"%s: couldn't find unitary "
 			"5GHz reg domain for country %u\n",
-			 __func__, ah->ah_countryCode);
-		return AH_FALSE;
+			__func__, ah->ah_countryCode);
+		return false;
 	}
-	if (!ath9k_regd_get_wmode_regdomain
-	    (ah, regdmn, CHANNEL_2GHZ, &rd2GHz)) {
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
+	if (!ath9k_regd_get_wmode_regdomain(ah,
+					    regdmn,
+					    CHANNEL_2GHZ,
+					    &rd2GHz)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 			"%s: couldn't find unitary 2GHz "
 			"reg domain for country %u\n",
-			 __func__, ah->ah_countryCode);
-		return AH_FALSE;
+			__func__, ah->ah_countryCode);
+		return false;
 	}
 
-	if (!isWwrSKU(ah)
-	    && ((rd5GHz.regDmnEnum == FCC1)
-		|| (rd5GHz.regDmnEnum == FCC2))) {
+	if (!isWwrSKU(ah) && ((rd5GHz.regDmnEnum == FCC1) ||
+			      (rd5GHz.regDmnEnum == FCC2))) {
 		if (ath9k_regd_is_fcc_midband_supported(ah)) {
-
-			if (!ath9k_regd_get_wmode_regdomain
-			    (ah, FCC3_FCCA, ~CHANNEL_2GHZ, &rd5GHz)) {
-				HDPRINTF(ah, HAL_DBG_REGULATORY,
+			if (!ath9k_regd_get_wmode_regdomain(ah,
+							    FCC3_FCCA,
+							    ~CHANNEL_2GHZ,
+							    &rd5GHz)) {
+				DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 					"%s: couldn't find unitary 5GHz "
 					"reg domain for country %u\n",
-					 __func__, ah->ah_countryCode);
-				return AH_FALSE;
+					__func__, ah->ah_countryCode);
+				return false;
 			}
 		}
 	}
@@ -517,9 +688,7 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 	if (country == NULL) {
 		modesAvail = ah->ah_caps.halWirelessModes;
 	} else {
-		modesAvail =
-		    ath9k_regd_get_wmodes_nreg(ah, country, &rd5GHz);
-
+		modesAvail = ath9k_regd_get_wmodes_nreg(ah, country, &rd5GHz);
 		if (!enableOutdoor)
 			maxChan = country->outdoorChanStart;
 	}
@@ -529,8 +698,6 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 	if (maxchans > ARRAY_SIZE(ah->ah_channels))
 		maxchans = ARRAY_SIZE(ah->ah_channels);
 
-	is_halfchan_cap = ah->ah_caps.halChanHalfRate;
-	is_quarterchan_cap = ah->ah_caps.halChanQuarterRate;
 	for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) {
 		u_int16_t c, c_hi, c_lo;
 		u_int64_t *channelBM = NULL;
@@ -539,26 +706,26 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 		int8_t low_adj = 0, hi_adj = 0;
 
 		if ((cm->mode & modeSelect) == 0) {
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
-				 "%s: skip mode 0x%x flags 0x%x\n",
-				 __func__, cm->mode, cm->flags);
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+				"%s: skip mode 0x%x flags 0x%x\n",
+				__func__, cm->mode, cm->flags);
 			continue;
 		}
 		if ((cm->mode & modesAvail) == 0) {
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
-				 "%s: !avail mode 0x%x (0x%x) flags 0x%x\n",
-				 __func__, modesAvail, cm->mode,
-				 cm->flags);
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+				"%s: !avail mode 0x%x (0x%x) flags 0x%x\n",
+				__func__, modesAvail, cm->mode,
+				cm->flags);
 			continue;
 		}
 		if (!ath9k_get_channel_edges(ah, cm->flags, &c_lo, &c_hi)) {
-
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 				"%s: channels 0x%x not supported "
 				"by hardware\n",
-				 __func__, cm->flags);
+				__func__, cm->flags);
 			continue;
 		}
+
 		switch (cm->mode) {
 		case ATH9K_MODE_SEL_11A:
 		case ATH9K_MODE_SEL_11NA_HT20:
@@ -585,15 +752,15 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 			ctl = rd->conformanceTestLimit | CTL_11G;
 			break;
 		default:
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
-				 "%s: Unkonwn HAL mode 0x%x\n", __func__,
-				 cm->mode);
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+				"%s: Unknown HAL mode 0x%x\n", __func__,
+				cm->mode);
 			continue;
 		}
+
 		if (ath9k_regd_is_chan_bm_zero(channelBM))
 			continue;
 
-
 		if ((cm->mode == ATH9K_MODE_SEL_11NA_HT40PLUS) ||
 		    (cm->mode == ATH9K_MODE_SEL_11NG_HT40PLUS)) {
 			hi_adj = -20;
@@ -608,57 +775,12 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 		for (b = 0; b < 64 * BMLEN; b++) {
 			if (ath9k_regd_is_bit_set(b, channelBM)) {
 				fband = &freqs[b];
-
-
 				if (rd5GHz.regDmnEnum == MKK1
 				    || rd5GHz.regDmnEnum == MKK2) {
-					int i, skipband = 0;
-					u_int32_t regcap;
-
-					for (i = 0;
-					     i < ARRAY_SIZE(j_bandcheck);
-					     i++) {
-						if (j_bandcheck[i].
-						    freqbandbit == b) {
-							regcap =
-							    ah->ah_caps.
-							    halRegCap;
-							if ((j_bandcheck
-							     [i].
-							     eepromflagtocheck
-							     & regcap) ==
-							    0) {
-								skipband =
-								    1;
-							} else
-							    if ((regcap &
-								 AR_EEPROM_EEREGCAP_EN_KK_U2)
-								|| (regcap
-								    &
-								    AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) {
-
-								rd5GHz.
-								    dfsMask
-								    |=
-								    DFS_MKK4;
-								rd5GHz.
-								    pscan
-								    |=
-								    PSCAN_MKK3;
-							}
-							break;
-						}
-					}
-					if (skipband) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							 "%s: Skipping %d "
-							"freq band.\n",
-							 __func__,
-							 j_bandcheck[i].
-							 freqbandbit);
+					if (ath9k_regd_japan_check(ah,
+								   b,
+								   &rd5GHz))
 						continue;
-					}
 				}
 
 				ath9k_regd_add_reg_classid(regclassids,
@@ -667,12 +789,8 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 							   fband->
 							   regClassId);
 
-				if (IS_HT40_MODE(cm->mode)
-				    && (rd == &rd5GHz)) {
-
+				if (IS_HT40_MODE(cm->mode) && (rd == &rd5GHz)) {
 					chanSep = 40;
-
-
 					if (fband->lowChannel == 5280)
 						low_adj += 20;
 
@@ -682,263 +800,59 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 					chanSep = fband->channelSep;
 
 				for (c = fband->lowChannel + low_adj;
-				     ((c <= (fband->highChannel + hi_adj))
-				      && (c >=
-					  (fband->lowChannel + low_adj)));
+				     ((c <= (fband->highChannel + hi_adj)) &&
+				      (c >= (fband->lowChannel + low_adj)));
 				     c += chanSep) {
-					struct hal_channel_internal icv;
-
-					if (!(c_lo <= c && c <= c_hi)) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"%s: c %u out of "
-							"range [%u..%u]\n",
-							 __func__, c, c_lo,
-							 c_hi);
-						continue;
-					}
-					if ((fband->channelBW ==
-					     CHANNEL_HALF_BW) &&
-					    !is_halfchan_cap) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							 "%s: Skipping %u half "
-							"rate channel\n",
-							 __func__, c);
-						continue;
-					}
-
-					if ((fband->channelBW ==
-					     CHANNEL_QUARTER_BW) &&
-					    !is_quarterchan_cap) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"%s: Skipping %u "
-							"quarter rate "
-							"channel\n",
-							 __func__, c);
-						continue;
-					}
-
-					if (((c + fband->channelSep) / 2) >
-					    (maxChan + HALF_MAXCHANBW)) {
-						HDPRINTF(ah,
-							HAL_DBG_REGULATORY,
-							"%s: c %u > "
-							"maxChan %u\n",
-							__func__, c,
-							 maxChan);
-						continue;
-					}
 					if (next >= maxchans) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"%s: too many "
-							"channels for channel "
-							"table\n",
-							 __func__);
+						DPRINTF(ah->ah_sc,
+							ATH_DBG_REGULATORY,
+							"%s: too many channels "
+							"for channel table\n",
+							__func__);
 						goto done;
 					}
-					if ((fband->
-					     usePassScan & IS_ECM_CHAN)
-					    && !enableExtendedChannels) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"Skipping ecm "
-							"channel\n");
-						continue;
-					}
-					if ((rd->flags & NO_HOSTAP) &&
-					    (ah->ah_opmode ==
-					     HAL_M_HOSTAP)) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"Skipping HOSTAP "
-							"channel\n");
-						continue;
-					}
-					if (IS_HT40_MODE(cm->mode) &&
-					    !
-					    (ath9k_regd_get_eeprom_reg_ext_bits
-					     (ah, REG_EXT_FCC_DFS_HT40))
-					    && (fband->useDfs)
-					    && (rd->conformanceTestLimit !=
-						MKK)) {
-
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"Skipping HT40 "
-							"channel "
-							"(en_fcc_dfs_ht40 = "
-							"0)\n");
-						continue;
-					}
-					if (IS_HT40_MODE(cm->mode) &&
-					    !
-					    (ath9k_regd_get_eeprom_reg_ext_bits
-					     (ah,
-					      REG_EXT_JAPAN_NONDFS_HT40))
-					    && !(fband->useDfs)
-					    && (rd->conformanceTestLimit ==
-						MKK)) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"Skipping HT40 "
-							"channel (en_jap_ht40 "
-							"= 0)\n");
-						continue;
-					}
-					if (IS_HT40_MODE(cm->mode) &&
-					    !
-					    (ath9k_regd_get_eeprom_reg_ext_bits
-					     (ah, REG_EXT_JAPAN_DFS_HT40))
-					    && (fband->useDfs)
-					    && (rd->conformanceTestLimit ==
-						MKK)) {
-						HDPRINTF(ah,
-							 HAL_DBG_REGULATORY,
-							"Skipping HT40 channel"
-							" (en_jap_dfs_ht40 = "
-							"0)\n");
-						continue;
-					}
-					memset(&icv, 0, sizeof(icv));
-					icv.channel = c;
-					icv.channelFlags = cm->flags;
-
-					switch (fband->channelBW) {
-					case CHANNEL_HALF_BW:
-						icv.channelFlags |=
-						    CHANNEL_HALF;
-						break;
-					case CHANNEL_QUARTER_BW:
-						icv.channelFlags |=
-						    CHANNEL_QUARTER;
-						break;
-					}
-
-					icv.maxRegTxPower =
-					    fband->powerDfs;
-					icv.antennaMax = fband->antennaMax;
-					icv.regDmnFlags = rd->flags;
-					icv.conformanceTestLimit = ctl;
-					if (fband->usePassScan & rd->pscan)
-						icv.channelFlags |=
-						    CHANNEL_PASSIVE;
-					else
-						icv.channelFlags &=
-						    ~CHANNEL_PASSIVE;
-					if (fband->useDfs & rd->dfsMask)
-						icv.privFlags =
-						    CHANNEL_DFS;
-					else
-						icv.privFlags = 0;
-					if (rd->flags & LIMIT_FRAME_4MS)
-						icv.privFlags |=
-						    CHANNEL_4MS_LIMIT;
-
-					if (icv.privFlags & CHANNEL_DFS) {
-						icv.privFlags |=
-						    CHANNEL_DISALLOW_ADHOC;
-					}
-					if (icv.
-					    regDmnFlags & ADHOC_PER_11D) {
-						icv.privFlags |=
-						    CHANNEL_PER_11D_ADHOC;
-					}
-					if (icv.
-					    channelFlags & CHANNEL_PASSIVE) {
-
-						if ((icv.channel < 2412)
-						    || (icv.channel >
-							2462)) {
-							if (rd5GHz.
-							    regDmnEnum ==
-							    MKK1
-							    || rd5GHz.
-							    regDmnEnum ==
-							    MKK2) {
-								u_int32_t
-								    regcap
-								    =
-								    ah->
-								    ah_caps.
-								    halRegCap;
-								if (!
-								    (regcap
-								     &
-								     (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
-								      |
-								      AR_EEPROM_EEREGCAP_EN_KK_U2
-								      |
-								      AR_EEPROM_EEREGCAP_EN_KK_MIDBAND))
-&& isUNII1OddChan(icv.channel)) {
-
-									icv.channelFlags &= ~CHANNEL_PASSIVE;
-								} else {
-									icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
-								}
-							} else {
-								icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
-							}
-						}
-					}
-					if (cm->
-					    mode & (ATH9K_MODE_SEL_11A |
-						    ATH9K_MODE_SEL_11NA_HT20
-						    |
-						    ATH9K_MODE_SEL_11NA_HT40PLUS
-						    |
-						    ATH9K_MODE_SEL_11NA_HT40MINUS)) {
-						if (icv.
-						    regDmnFlags &
-						    (ADHOC_NO_11A |
-						     DISALLOW_ADHOC_11A)) {
-							icv.privFlags |=
-							    CHANNEL_DISALLOW_ADHOC;
-						}
-					}
-
-					memcpy(&ichans[next++], &icv,
-					       sizeof(struct
-						      hal_channel_internal));
+					if (ath9k_regd_add_channel(ah,
+						   c, c_lo, c_hi,
+						   maxChan, ctl,
+						   next,
+						   rd5GHz,
+						   fband, rd, cm,
+						   ichans,
+						   enableExtendedChannels))
+						next++;
 				}
-
-				if (IS_HT40_MODE(cm->mode)
-				    && (fband->lowChannel == 5280)) {
+				if (IS_HT40_MODE(cm->mode) &&
+				    (fband->lowChannel == 5280)) {
 					low_adj -= 20;
 				}
 			}
 		}
 	}
 done:
-      if (next != 0) {
+	if (next != 0) {
 		int i;
 
-
 		if (next > ARRAY_SIZE(ah->ah_channels)) {
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
-				 "%s: too many channels %u; truncating to %u\n",
-				 __func__, next,
-				 (int) ARRAY_SIZE(ah->ah_channels));
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+				"%s: too many channels %u; truncating to %u\n",
+				__func__, next,
+				(int) ARRAY_SIZE(ah->ah_channels));
 			next = ARRAY_SIZE(ah->ah_channels);
 		}
 #ifdef ATH_NF_PER_CHAN
-
 		ath9k_regd_init_rf_buffer(ichans, next);
 #endif
-
 		ath9k_regd_sort(ichans, next,
 				sizeof(struct hal_channel_internal),
 				ath9k_regd_chansort);
 		ah->ah_nchan = next;
 
-		HDPRINTF(ah, HAL_DBG_REGULATORY, "Channel list:\n");
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "Channel list:\n");
 		for (i = 0; i < next; i++) {
-			HDPRINTF(ah, HAL_DBG_REGULATORY,
-				 "chan: %d flags: 0x%x\n",
-				 ichans[i].channel,
-				 ichans[i].channelFlags);
+			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+				"chan: %d flags: 0x%x\n",
+				ichans[i].channel,
+				ichans[i].channelFlags);
 			chans[i].channel = ichans[i].channel;
 			chans[i].channelFlags = ichans[i].channelFlags;
 			chans[i].privFlags = ichans[i].privFlags;
@@ -965,20 +879,22 @@ done:
 		ah->ah_iso[0] = country->isoName[0];
 		ah->ah_iso[1] = country->isoName[1];
 	}
+
 	return next != 0;
 }
 
-struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
-	const struct hal_channel *c)
+struct hal_channel_internal*
+ath9k_regd_check_channel(struct ath_hal *ah,
+			 const struct hal_channel *c)
 {
 	struct hal_channel_internal *base, *cc;
 
 	int flags = c->channelFlags & CHAN_FLAGS;
 	int n, lim;
 
-	HDPRINTF(ah, HAL_DBG_REGULATORY,
-		 "%s: channel %u/0x%x (0x%x) requested\n", __func__,
-		 c->channel, c->channelFlags, flags);
+	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+		"%s: channel %u/0x%x (0x%x) requested\n", __func__,
+		c->channel, c->channelFlags, flags);
 
 	cc = ah->ah_curchan;
 	if (cc != NULL && cc->channel == c->channel &&
@@ -999,24 +915,24 @@ struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
 		d = c->channel - cc->channel;
 		if (d == 0) {
 			if ((cc->channelFlags & CHAN_FLAGS) == flags) {
-				if ((cc->privFlags & CHANNEL_INTERFERENCE)
-				    && (cc->privFlags & CHANNEL_DFS))
+				if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
+				    (cc->privFlags & CHANNEL_DFS))
 					return NULL;
 				else
 					return cc;
 			}
 			d = flags - (cc->channelFlags & CHAN_FLAGS);
 		}
-		HDPRINTF(ah, HAL_DBG_REGULATORY,
-			 "%s: channel %u/0x%x d %d\n", __func__,
-			 cc->channel, cc->channelFlags, d);
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: channel %u/0x%x d %d\n", __func__,
+			cc->channel, cc->channelFlags, d);
 		if (d > 0) {
 			base = cc + 1;
 			lim--;
 		}
 	}
-	HDPRINTF(ah, HAL_DBG_REGULATORY, "%s: no match for %u/0x%x\n",
-		 __func__, c->channel, c->channelFlags);
+	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: no match for %u/0x%x\n",
+		__func__, c->channel, c->channelFlags);
 	return NULL;
 }
 
@@ -1062,9 +978,9 @@ void ath9k_regd_get_current_country(struct ath_hal *ah,
 {
 	u_int16_t rd = ath9k_regd_get_eepromRD(ah);
 
-	ctry->isMultidomain = AH_FALSE;
+	ctry->isMultidomain = false;
 	if (rd == CTRY_DEFAULT)
-		ctry->isMultidomain = AH_TRUE;
+		ctry->isMultidomain = true;
 	else if (!(rd & COUNTRY_ERD_FLAG))
 		ctry->isMultidomain = isWwrSKU(ah);
 
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/regd.h b/package/ath9k/src/drivers/net/wireless/ath9k/regd.h
index 854611761a..125941cb62 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/regd.h
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/regd.h
@@ -19,9 +19,6 @@
 
 #include "ath9k.h"
 
-#define ATH9K_MODE_11A_TURBO  ATH9K_MODE_SEL_108A
-#define ATH9K_MODE_11G_TURBO  ATH9K_MODE_SEL_108G
-
 #define BMLEN 2
 #define BMZERO {(u_int64_t) 0, (u_int64_t) 0}
 
@@ -124,7 +121,7 @@
 	(((_mode == ATH9K_MODE_SEL_11NA_HT40PLUS  || \
 	_mode == ATH9K_MODE_SEL_11NG_HT40PLUS    || \
 	_mode == ATH9K_MODE_SEL_11NA_HT40MINUS   || \
-	_mode == ATH9K_MODE_SEL_11NG_HT40MINUS) ? AH_TRUE : AH_FALSE))
+	_mode == ATH9K_MODE_SEL_11NG_HT40MINUS) ? true : false))
 
 #define CHAN_FLAGS      (CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
 
@@ -172,13 +169,13 @@ struct country_code_to_enum_rd {
 	u_int16_t regDmnEnum;
 	const char *isoName;
 	const char *name;
-	enum hal_bool allow11g;
-	enum hal_bool allow11aTurbo;
-	enum hal_bool allow11gTurbo;
-	enum hal_bool allow11ng20;
-	enum hal_bool allow11ng40;
-	enum hal_bool allow11na20;
-	enum hal_bool allow11na40;
+	bool allow11g;
+	bool allow11aTurbo;
+	bool allow11gTurbo;
+	bool allow11ng20;
+	bool allow11ng40;
+	bool allow11na20;
+	bool allow11na40;
 	u_int16_t outdoorChanStart;
 };
 
@@ -213,8 +210,8 @@ struct cmode {
 	u_int32_t flags;
 };
 
-#define YES AH_TRUE
-#define NO  AH_FALSE
+#define YES true
+#define NO  false
 
 struct japan_bandcheck {
 	u_int16_t freqbandbit;
diff --git a/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c b/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c
index 6374bf89cf..2e3ae65945 100644
--- a/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c
+++ b/package/ath9k/src/drivers/net/wireless/ath9k/xmit.c
@@ -118,11 +118,11 @@ static void ath_tx_mcastqaddbuf(struct ath_softc *sc,
 	txq->axq_totalqueued++;
 	txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
 
-	DPRINTF(sc, ATH_DEBUG_TX_PROC,
+	DPRINTF(sc, ATH_DBG_QUEUE,
 		"%s: txq depth = %d\n", __func__, txq->axq_depth);
 	if (txq->axq_link != NULL) {
 		*txq->axq_link = bf->bf_daddr;
-		DPRINTF(sc, ATH_DEBUG_XMIT,
+		DPRINTF(sc, ATH_DBG_XMIT,
 			"%s: link[%u](%p)=%llx (%p)\n",
 			__func__,
 			txq->axq_qnum, txq->axq_link,
@@ -158,18 +158,18 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc,
 	txq->axq_totalqueued++;
 	txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
 
-	DPRINTF(sc, ATH_DEBUG_TX_PROC,
+	DPRINTF(sc, ATH_DBG_QUEUE,
 		"%s: txq depth = %d\n", __func__, txq->axq_depth);
 
 	if (txq->axq_link == NULL) {
 		ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-		DPRINTF(sc, ATH_DEBUG_XMIT,
+		DPRINTF(sc, ATH_DBG_XMIT,
 			"%s: TXDP[%u] = %llx (%p)\n",
 			__func__, txq->axq_qnum,
 			ito64(bf->bf_daddr), bf->bf_desc);
 	} else {
 		*txq->axq_link = bf->bf_daddr;
-		DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
+		DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
 			__func__,
 			txq->axq_qnum, txq->axq_link,
 			ito64(bf->bf_daddr), bf->bf_desc);
@@ -284,7 +284,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
 	fc = hdr->frame_control;
 
 	rt = sc->sc_currates;
-	KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
+	BUG_ON(!rt);
 
 	/* Fill misc fields */
 
@@ -334,7 +334,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
 
 	/* Try to avoid running out of descriptors */
 	if (txq->axq_depth >= (ATH_TXBUF - 20)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: TX queue: %d is full, depth: %d\n",
 			__func__,
 			txctl->qnum,
@@ -558,7 +558,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
 	if (tid->sched)
 		return;
 
-	tid->sched = AH_TRUE;
+	tid->sched = true;
 	list_add_tail(&tid->list, &ac->tid_q);
 
 	/*
@@ -567,7 +567,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
 	if (ac->sched)
 		return;
 
-	ac->sched = AH_TRUE;
+	ac->sched = true;
 	list_add_tail(&ac->list, &txq->axq_acq);
 }
 
@@ -625,7 +625,7 @@ static int ath_tx_num_badfrms(struct ath_softc *sc,
 	int nbad = 0;
 	int isaggr = 0;
 
-	if (isnodegone || ds->ds_txstat.ts_flags == HAL_TX_SW_ABORTED)
+	if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
 		return 0;
 
 	isaggr = bf->bf_isaggr;
@@ -690,7 +690,7 @@ static u_int32_t ath_pkt_duration(struct ath_softc *sc,
 				  struct ath_buf *bf,
 				  int width,
 				  int half_gi,
-				  enum hal_bool shortPreamble)
+				  bool shortPreamble)
 {
 	const struct hal_rate_table *rt = sc->sc_currates;
 	u_int32_t nbits, nsymbits, duration, nsymbols;
@@ -780,8 +780,8 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 * let rate series flags determine which rates will actually
 	 * use RTS.
 	 */
-	if (sc->sc_hashtsupport && bf->bf_isdata) {
-		KASSERT(an != NULL, ("an == null"));
+	if (ah->ah_caps.halHTSupport && bf->bf_isdata) {
+		BUG_ON(!an);
 		/*
 		 * 802.11g protection not needed, use our default behavior
 		 */
@@ -829,7 +829,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 * in whether or not a short preamble is to be used.
 	 */
 	/* NB: cix is set above where RTS/CTS is enabled */
-	KASSERT(cix != 0xff, ("cix not setup"));
+	BUG_ON(cix == 0xff);
 	ctsrate = rt->info[cix].rateCode |
 		(bf->bf_shpreamble ? rt->info[cix].shortPreamble : 0);
 
@@ -896,7 +896,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 * For non-HT devices, calculate RTS/CTS duration in software
 	 * and disable multi-rate retry.
 	 */
-	if (flags && !sc->sc_hashtsupport) {
+	if (flags && !ah->ah_caps.halHTSupport) {
 		/*
 		 * Compute the transmit duration based on the frame
 		 * size and the size of an ACK frame.  We call into the
@@ -1069,7 +1069,7 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
 		} else {
 
 			if (!tid->cleanup_inprogress && !isnodegone &&
-			    ds->ds_txstat.ts_flags != HAL_TX_SW_ABORTED) {
+			    ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
 				if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
 					ath_tx_set_retry(sc, bf);
 					txpending = 1;
@@ -1218,7 +1218,7 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
 			tid->addba_exchangeattempts = 0;
 			spin_unlock_bh(&txq->axq_lock);
 
-			tid->cleanup_inprogress = AH_FALSE;
+			tid->cleanup_inprogress = false;
 
 			/* send buffered frames as singles */
 			ath_tx_flush_tid(sc, tid);
@@ -1257,11 +1257,10 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 	struct sk_buff *skb;
 	struct ieee80211_tx_info *tx_info;
 	struct ath_tx_info_priv *tx_info_priv;
-	u_int8_t txant;
 	int nacked, txok, nbad = 0, isrifs = 0;
 	enum hal_status status;
 
-	DPRINTF(sc, ATH_DEBUG_TX_PROC,
+	DPRINTF(sc, ATH_DBG_QUEUE,
 		"%s: tx queue %d (%x), link %p\n", __func__,
 		txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
 		txq->axq_link);
@@ -1345,17 +1344,13 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 			spin_unlock_bh(&sc->sc_txbuflock);
 		}
 
-		if (txok) {
-			txant = ds->ds_txstat.ts_antenna;
-			sc->sc_ant_tx[txant]++;
-		}
 		if (!bf->bf_isampdu) {
 			/*
 			 * This frame is sent out as a single frame.
 			 * Use hardware retry status for this frame.
 			 */
 			bf->bf_retries = ds->ds_txstat.ts_longretry;
-			if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
+			if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
 				bf->bf_isxretried = 1;
 			nbad = 0;
 		} else {
@@ -1365,9 +1360,9 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 		tx_info = IEEE80211_SKB_CB(skb);
 		tx_info_priv = (struct ath_tx_info_priv *)
 			tx_info->driver_data[0];
-		if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
+		if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
 			tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
-		if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
+		if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
 				(bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
 			if (ds->ds_txstat.ts_status == 0)
 				nacked++;
@@ -1422,14 +1417,14 @@ static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
 	struct ath_hal *ah = sc->sc_ah;
 
 	(void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
-	DPRINTF(sc, ATH_DEBUG_XMIT, "%s: tx queue [%u] %x, link %p\n",
+	DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
 		__func__, txq->axq_qnum,
 		ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
 }
 
 /* Drain only the data queues */
 
-static void ath_drain_txdataq(struct ath_softc *sc, enum hal_bool retry_tx)
+static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	int i;
@@ -1454,16 +1449,16 @@ static void ath_drain_txdataq(struct ath_softc *sc, enum hal_bool retry_tx)
 		enum hal_status status;
 
 		/* TxDMA not stopped, reset the hal */
-		DPRINTF(sc, ATH_DEBUG_XMIT,
+		DPRINTF(sc, ATH_DBG_XMIT,
 			"%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
 
 		spin_lock_bh(&sc->sc_resetlock);
 		if (!ath9k_hw_reset(ah, sc->sc_opmode,
 			&sc->sc_curchan, ht_macmode,
 			sc->sc_tx_chainmask, sc->sc_rx_chainmask,
-			sc->sc_ht_extprotspacing, AH_TRUE, &status)) {
+			sc->sc_ht_extprotspacing, true, &status)) {
 
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: unable to reset hardware; hal status %u\n",
 				__func__,
 				status);
@@ -1974,10 +1969,10 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
 
 	list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
 		list_del(&ac->list);
-		ac->sched = AH_FALSE;
+		ac->sched = false;
 		list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
 			list_del(&tid->list);
-			tid->sched = AH_FALSE;
+			tid->sched = false;
 			ath_tid_drain(sc, txq, tid, bh_flag);
 		}
 	}
@@ -2059,8 +2054,8 @@ static int ath_tx_start_dma(struct ath_softc *sc,
 	ath9k_hw_filltxdesc(ah,
 			    ds,
 			    sg_dma_len(sg),     /* segment length */
-			    AH_TRUE,            /* first segment */
-			    (n_sg == 1) ? AH_TRUE : AH_FALSE, /* last segment */
+			    true,            /* first segment */
+			    (n_sg == 1) ? true : false, /* last segment */
 			    ds);                /* first descriptor */
 
 	bf->bf_lastfrm = bf;
@@ -2168,7 +2163,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
 		error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
 			"tx", nbufs * ATH_FRAG_PER_MSDU, ATH_TXDESC);
 		if (error != 0) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: failed to allocate tx descriptors: %d\n",
 				__func__, error);
 			break;
@@ -2178,7 +2173,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
 		error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
 					  "beacon", ATH_BCBUF, 1);
 		if (error != 0) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: failed to allocate "
 				"beacon descripotrs: %d\n",
 				__func__, error);
@@ -2252,7 +2247,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
 		return NULL;
 	}
 	if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: hal qnum %u out of range, max %u!\n",
 			__func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
 		ath9k_hw_releasetxqueue(ah, qnum);
@@ -2299,7 +2294,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
 	struct ath_txq *txq;
 
 	if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: HAL AC %u out of range, max %zu!\n",
 			__func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
 		return 0;
@@ -2319,7 +2314,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
 	switch (qtype) {
 	case HAL_TX_QUEUE_DATA:
 		if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: HAL AC %u out of range, max %zu!\n",
 				__func__,
 				haltype, ARRAY_SIZE(sc->sc_haltype2q));
@@ -2367,7 +2362,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *qi0)
 	qi.tqi_readyTime = qi0->tqi_readyTime;
 
 	if (!ath9k_hw_settxqueueprops(ah, qnum, &qi)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: unable to update hardware queue %u!\n",
 			__func__, qnum);
 		error = -EIO;
@@ -2445,7 +2440,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
 }
 
 void ath_tx_draintxq(struct ath_softc *sc,
-	struct ath_txq *txq, enum hal_bool retry_tx)
+	struct ath_txq *txq, bool retry_tx)
 {
 	struct ath_buf *bf, *lastbf;
 	struct list_head bf_head;
@@ -2480,7 +2475,8 @@ void ath_tx_draintxq(struct ath_softc *sc,
 
 		lastbf = bf->bf_lastbf;
 		if (!retry_tx)
-			lastbf->bf_desc->ds_txstat.ts_flags = HAL_TX_SW_ABORTED;
+			lastbf->bf_desc->ds_txstat.ts_flags =
+				ATH9K_TX_SW_ABORTED;
 
 		/* remove ath_buf's of the same mpdu from txq */
 		list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
@@ -2507,13 +2503,13 @@ void ath_tx_draintxq(struct ath_softc *sc,
 
 /* Drain the transmit queues and reclaim resources */
 
-void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx)
+void ath_draintxq(struct ath_softc *sc, bool retry_tx)
 {
 	/* stop beacon queue. The beacon will be freed when
 	 * we go to INIT state */
 	if (!sc->sc_invalid) {
 		(void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
-		DPRINTF(sc, ATH_DEBUG_XMIT, "%s: beacon queue %x\n", __func__,
+		DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
 			ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
 	}
 
@@ -2579,7 +2575,7 @@ int ath_tx_aggr_start(struct ath_softc *sc,
 	spin_unlock_bh(&sc->node_lock);
 
 	if (!an) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Node not found to initialize "
 			"TX aggregation\n", __func__);
 		return -1;
@@ -2607,7 +2603,7 @@ int ath_tx_aggr_stop(struct ath_softc *sc,
 	spin_unlock_bh(&sc->node_lock);
 
 	if (!an) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: TX aggr stop for non-existent node\n", __func__);
 		return -1;
 	}
@@ -2632,7 +2628,7 @@ void ath_tx_aggr_teardown(struct ath_softc *sc,
 	struct list_head bf_head;
 	INIT_LIST_HEAD(&bf_head);
 
-	DPRINTF(sc, ATH_DEBUG_AGGR, "%s: teardown TX aggregation\n", __func__);
+	DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
 
 	if (txtid->cleanup_inprogress) /* cleanup is in progress */
 		return;
@@ -2667,7 +2663,7 @@ void ath_tx_aggr_teardown(struct ath_softc *sc,
 
 	if (txtid->baw_head != txtid->baw_tail) {
 		spin_unlock_bh(&txq->axq_lock);
-		txtid->cleanup_inprogress = AH_TRUE;
+		txtid->cleanup_inprogress = true;
 	} else {
 		txtid->addba_exchangecomplete = 0;
 		txtid->addba_exchangeattempts = 0;
@@ -2694,7 +2690,7 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
 	 */
 	ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
 	list_del(&ac->list);
-	ac->sched = AH_FALSE;
+	ac->sched = false;
 
 	/*
 	 * process a single tid per destination
@@ -2706,7 +2702,7 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
 
 		tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
 		list_del(&tid->list);
-		tid->sched = AH_FALSE;
+		tid->sched = false;
 
 		if (tid->paused)    /* check next tid to keep h/w busy */
 			continue;
@@ -2734,8 +2730,8 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
 		/*
 		 * add dest ac to txq if not already added
 		 */
-		if (ac->sched == AH_FALSE) {
-			ac->sched = AH_TRUE;
+		if (!ac->sched) {
+			ac->sched = true;
 			list_add_tail(&ac->list, &txq->axq_acq);
 		}
 	}
@@ -2763,9 +2759,9 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
 			tid->seq_start = tid->seq_next = 0;
 			tid->baw_size  = WME_MAX_BA;
 			tid->baw_head  = tid->baw_tail = 0;
-			tid->sched     = AH_FALSE;
-			tid->paused = AH_FALSE;
-			tid->cleanup_inprogress = AH_FALSE;
+			tid->sched     = false;
+			tid->paused = false;
+			tid->cleanup_inprogress = false;
 			INIT_LIST_HEAD(&tid->buf_q);
 
 			acno = TID_TO_WME_AC(tidno);
@@ -2782,7 +2778,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
 		 */
 		for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
 				acno < WME_NUM_AC; acno++, ac++) {
-			ac->sched    = AH_FALSE;
+			ac->sched    = false;
 			INIT_LIST_HEAD(&ac->tid_q);
 
 			switch (acno) {
@@ -2832,16 +2828,16 @@ void ath_tx_node_cleanup(struct ath_softc *sc,
 				if (tid && tid->an != an)
 					continue;
 				list_del(&ac->list);
-				ac->sched = AH_FALSE;
+				ac->sched = false;
 
 				list_for_each_entry_safe(tid,
 						tid_tmp, &ac->tid_q, list) {
 					list_del(&tid->list);
-					tid->sched = AH_FALSE;
+					tid->sched = false;
 					ath_tid_drain(sc, txq, tid, bh_flag);
 					tid->addba_exchangecomplete = 0;
 					tid->addba_exchangeattempts = 0;
-					tid->cleanup_inprogress = AH_FALSE;
+					tid->cleanup_inprogress = false;
 				}
 			}