arm-trusted-firmware-mvebu: CZ.NIC's Secure Firmware bump to v2021.09.07

bump version and remove patches that have been applied

176d701 wtmi: Wait 1s after putting PHYs INTn pin low
2eeccfe wtmi: Change comment describing reset workaround
e8c94a5 wtmi: Count RAM size from both CS0 and CS1
995979e wtmi: Rename macro
e29eb29 wtmi: soc: Fix start_ap_workaround() for TF-A with debug
81245ed wtmi: Use constant name PLAT_MARVELL_MAILBOX_BASE
18ccb83 wtmi: Do a proper UART reset with clock change as described in spec
15ff106 avs: Validate VDD value from OTP
3f33626 fix: clock: a3700: change pwm clock for 600/600 and 1200/750 preset
fb5e436 wtmi: uart: fix UART baudrate divisor calculation

Signed-off-by: sean lee <ilf@live.com>

4 files changed, 2 insertions, 168 deletions

diff --git a/package/boot/arm-trusted-firmware-mvebu/Makefile b/package/boot/arm-trusted-firmware-mvebu/Makefile
index 2369a1930a..8836388bec 100644
--- a/package/boot/arm-trusted-firmware-mvebu/Makefile
+++ b/package/boot/arm-trusted-firmware-mvebu/Makefile
@@ -149,13 +149,13 @@ define Download/mv-ddr-marvell
 endef
 
 MOX_BB_NAME:=mox-boot-builder
-MOX_BB_RELEASE:=v2021.04.09
+MOX_BB_RELEASE:=v2021.09.07
 MOX_BB_SOURCE:=$(MOX_BB_NAME)-$(MOX_BB_RELEASE).tar.bz2
 
 define Download/mox-boot-builder
   FILE:=$(MOX_BB_SOURCE)
   URL:=https://gitlab.nic.cz/turris/mox-boot-builder/-/archive/$(MOX_BB_RELEASE)
-  HASH:=f0ed4fa25006e36a07d4256f633e3f25d6f8898dbe2e081e578251a182885520
+  HASH:=fd5fe276a3b0dee3177d61c017907a8eb23cd2169478fa78e9a3a836cfe3a4a8
 endef
 
 CM3_GCC_NAME:=gcc-arm
diff --git a/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/100-wtmi-uart-fix-UART-baudrate-divisor-calculation.patch b/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/100-wtmi-uart-fix-UART-baudrate-divisor-calculation.patch
deleted file mode 100644
index 4bd66f9107..0000000000
--- a/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/100-wtmi-uart-fix-UART-baudrate-divisor-calculation.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From fb5e436843614f93b30aec0a2a00e5e59a133aab Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
-Date: Sat, 15 May 2021 17:44:24 +0200
-Subject: [PATCH] wtmi: uart: fix UART baudrate divisor calculation
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The UART code uses the xtal clock as parent for UART baudrate
-generation, but it assumes that xtal runs at 25 MHz, which isn't
-necessarily the case for all A3720 boards.
-
-Use get_ref_clk() to determine xtal clock rate.
-
-Use rounding division to compute the divisor value.
-
-Signed-off-by: Marek Behún <marek.behun@nic.cz>
-Suggested-by: Pali Rohár <pali@kernel.org>
----
- wtmi/types.h | 5 +++++
- wtmi/uart.c  | 7 ++++---
- 2 files changed, 9 insertions(+), 3 deletions(-)
-
-diff --git a/wtmi/types.h b/wtmi/types.h
-index 7a6c6c6..ea873fc 100644
---- a/wtmi/types.h
-+++ b/wtmi/types.h
-@@ -47,4 +47,9 @@ typedef u32			size_t;
- 
- #define maybe_unused __attribute__((unused))
- 
-+static inline u32 div_round_closest_u32(u32 x, u32 d)
-+{
-+	return (x + d / 2) / d;
-+}
-+
- #endif /* __TYPES_H */
-diff --git a/wtmi/uart.c b/wtmi/uart.c
-index d40633d..75864b5 100644
---- a/wtmi/uart.c
-+++ b/wtmi/uart.c
-@@ -40,8 +40,6 @@
- #include "stdio.h"
- #include "debug.h"
- 
--#define UART_CLOCK_FREQ		25804800
--
- const struct uart_info uart1_info = {
- 	.rx	= 0xc0012000,
- 	.tx	= 0xc0012004,
-@@ -76,8 +74,11 @@ void uart_set_stdio(const struct uart_info *info)
- 
- void uart_reset(const struct uart_info *info, unsigned int baudrate)
- {
-+	u32 parent_rate = get_ref_clk() * 1000000;
-+
- 	/* set baudrate */
--	writel((UART_CLOCK_FREQ / baudrate / 16), info->baud);
-+	writel(div_round_closest_u32(parent_rate, baudrate * 16), info->baud);
-+
- 	/* set Programmable Oversampling Stack to 0, UART defaults to 16X scheme */
- 	writel(0, info->possr);
- 
--- 
-2.30.2
-
diff --git a/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/101-fix-clock-a3700-change-pwm-clock-for-600-600-and-120.patch b/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/101-fix-clock-a3700-change-pwm-clock-for-600-600-and-120.patch
deleted file mode 100644
index 6d74a053e2..0000000000
--- a/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/101-fix-clock-a3700-change-pwm-clock-for-600-600-and-120.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 3f33626ac7037bd62df9391e899f50e076e58cf7 Mon Sep 17 00:00:00 2001
-From: zachary <zhangzg@marvell.com>
-Date: Wed, 25 Oct 2017 15:50:29 +0800
-Subject: [PATCH] fix: clock: a3700: change pwm clock for 600/600 and 1200/750
- preset
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This patch is to change pwm clock from 100MHz to 50MHz for 600/600 and
-1200/750 preset to align with other presets.
-
-Change-Id: I067e189043be8c776bd3e7015a06f8ddf2590b96
-Signed-off-by: zachary <zhangzg@marvell.com>
-Reviewed-on: http://vgitil04.il.marvell.com:8080/45513
-Tested-by: iSoC Platform CI <ykjenk@marvell.com>
-Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
-Reviewed-by: Hua Jing <jinghua@marvell.com>
-Signed-off-by: Marek Behún <marek.behun@nic.cz>
----
- wtmi/clock.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/wtmi/clock.c b/wtmi/clock.c
-index 97c2825..1a1f0c6 100644
---- a/wtmi/clock.c
-+++ b/wtmi/clock.c
-@@ -447,7 +447,7 @@ static struct clock_cfg clk_cfg_all[] = {\
- 		/* NorthBridge */\
- 		{{TBG_A_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_A_P, TBG_A_P, TBG_A_P,\
- 		  TBG_B_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_P, TBG_B_S},\
--		 {2, 5, 2, 4, 1, 2, 6, 2},		/* DIV0 */\
-+		 {4, 5, 2, 4, 1, 2, 6, 2},		/* DIV0 */\
- 		 {1, 5, 2, 5, 2, 3, 2, 2, 3},		/* DIV1 */\
- 		 {4, 1, 5, 1, 3, 1, 2, 0, 0, 1} },	/* DIV2 */\
- 		/* SouthBridge */\
-@@ -495,7 +495,7 @@ static struct clock_cfg clk_cfg_all[] = {\
- 		/* NorthBridge */\
- 		{{TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S, TBG_B_S,\
- 		  TBG_B_S, TBG_A_S, TBG_B_S, TBG_A_P, TBG_B_S, TBG_A_S},\
--		{3, 4, 3, 4, 1, 1, 5, 1},		/* DIV0 */\
-+		{6, 4, 3, 4, 1, 1, 5, 1},		/* DIV0 */\
- 		{1, 6, 3, 4, 1, 6, 1, 1, 6},		/* DIV1 */\
- 		{4, 1, 6, 1, 3, 1, 3, 0, 0, 1} },	/* DIV2 */\
- 		/* SouthBridge */\
--- 
-2.30.2
-
diff --git a/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/102-avs-Validate-VDD-value-from-OTP.patch b/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/102-avs-Validate-VDD-value-from-OTP.patch
deleted file mode 100644
index d44eb21181..0000000000
--- a/package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/102-avs-Validate-VDD-value-from-OTP.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 15ff10623c83ee2e626d93d16e022b115dcb608f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
-Date: Sat, 10 Apr 2021 16:56:12 +0200
-Subject: [PATCH] avs: Validate VDD value from OTP
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-CPU VDD voltage value for 1.2 GHz frequency on some Espressobin boards is
-not set and raw value 0x00 is returned. In this case init_avs() function
-calculated CPU VDD voltage value to 0x00 + AVS_VDD_BASE = 0.898 V, which is
-too low for any operation and Espressobin board immediately crashed
-init_avs() function set this low value.
-
-This patch fixes above issue by validating returned VDD value from OTP and
-using default VDD value when invalid value is in OTP. With this patch
-init_avs() function does cause CPU crash anymore.
-
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Signed-off-by: Marek Behún <marek.behun@nic.cz>
----
- wtmi/avs.c | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/wtmi/avs.c b/wtmi/avs.c
-index 36ca9fa..4624359 100644
---- a/wtmi/avs.c
-+++ b/wtmi/avs.c
-@@ -140,10 +140,16 @@ int init_avs(u32 speed)
- 	}
- 
- 	if (svc_rev >= SVC_REVISION_2) {
--		vdd_otp = ((otp_data[OTP_DATA_SVC_SPEED_ID] >> shift) +
--			   AVS_VDD_BASE) & AVS_VDD_MASK;
--		regval |= (vdd_otp << HIGH_VDD_LIMIT_OFF);
--		regval |= (vdd_otp << LOW_VDD_LIMIT_OFF);
-+		vdd_otp = (otp_data[OTP_DATA_SVC_SPEED_ID] >> shift) &
-+			  AVS_VDD_MASK;
-+		if (!vdd_otp || vdd_otp + AVS_VDD_BASE > AVS_VDD_MASK) {
-+			regval |= (vdd_default << HIGH_VDD_LIMIT_OFF);
-+			regval |= (vdd_default << LOW_VDD_LIMIT_OFF);
-+		} else {
-+			vdd_otp += AVS_VDD_BASE;
-+			regval |= (vdd_otp << HIGH_VDD_LIMIT_OFF);
-+			regval |= (vdd_otp << LOW_VDD_LIMIT_OFF);
-+		}
- 	} else {
- 		regval |= (vdd_default << HIGH_VDD_LIMIT_OFF);
- 		regval |= (vdd_default << LOW_VDD_LIMIT_OFF);
--- 
-2.30.2
-