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| author | Gabor Juhos <juhosg@openwrt.org> | 2014-01-10 09:05:31 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2014-01-10 09:05:31 +0000 |
| commit | 8384c0dba0cb2c1b4a05aea232b3715fe79dee2d (patch) | |
| tree | 75ae9e316a1b9a03c9521b4f68bddd0d2892b97d /package | |
| parent | 6dcf8788646667921921da3c730ad47232186db0 (diff) | |
| download | upstream-8384c0dba0cb2c1b4a05aea232b3715fe79dee2d.tar.gz upstream-8384c0dba0cb2c1b4a05aea232b3715fe79dee2d.tar.bz2 upstream-8384c0dba0cb2c1b4a05aea232b3715fe79dee2d.zip | |
ath9k: add workaround for AR9331 USB host controller hang with USB1.1 devices
When wifi radio is reset, some bits in (undocumented) USB registers may
flip. Patch adds setting them after radio reset (channel change, up/down).
With this patch stability of USB1.1 full-speed devices, connected directly
to AR9331 host port (no USB2.0 hub) is improved.
See "ar9331's usb stability issue" OpenWrt forum thread for details:
<https://forum.openwrt.org/viewtopic.php?id=39956>
Based on QCA's Open HAL WAR_USB_DISABLE_PLL_LOCK_DETECT() macro:
<https://github.com/qca/qcamain_open_hal_public/blob/master/hal/ar9300/ar9300_reset.c#L74>
Adapted to Linux mac80211 driver for 8Devices Carambola2 board by Mantas Pucka:
<https://github.com/8devices/carambola2/commit/b08b59ceb4e7f0bad4c0b17e703e1e5c4e168923>
Ported to latest OpenWrt BB branch and tested on TP-Link TL-WR703N by
Michel Stempin <michel.stempin@wanadoo.fr>.
Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
[juhosg: refresh and clean up the ath9k patch]
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 39212
Diffstat (limited to 'package')
| -rw-r--r-- | package/kernel/mac80211/patches/566-ath9k-ar933x-usb-hang-workaround.patch | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/package/kernel/mac80211/patches/566-ath9k-ar933x-usb-hang-workaround.patch b/package/kernel/mac80211/patches/566-ath9k-ar933x-usb-hang-workaround.patch new file mode 100644 index 0000000000..7608d481d7 --- /dev/null +++ b/package/kernel/mac80211/patches/566-ath9k-ar933x-usb-hang-workaround.patch @@ -0,0 +1,79 @@ +--- a/drivers/net/wireless/ath/ath9k/hw.c ++++ b/drivers/net/wireless/ath/ath9k/hw.c +@@ -269,6 +269,19 @@ void ath9k_hw_get_channel_centers(struct + centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); + } + ++static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah) ++{ ++ /* On AR9330 and AR9340 devices, some PHY registers must be ++ * tuned to gain better stability/performance. These registers ++ * might be changed while doing wlan reset so the registers must ++ * be reprogrammed after each reset. ++ */ ++ REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20)); ++ REG_RMW(ah, AR_PHY_USB_CTRL2, ++ (1 << 21) | (0xf << 22), ++ (1 << 21) | (0x3 << 22)); ++} ++ + /******************/ + /* Chip Revisions */ + /******************/ +@@ -1357,6 +1370,9 @@ static bool ath9k_hw_set_reset(struct at + if (AR_SREV_9100(ah)) + udelay(50); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return true; + } + +@@ -1457,6 +1473,9 @@ static bool ath9k_hw_chip_reset(struct a + ath9k_hw_init_pll(ah, chan); + ath9k_hw_set_rfmode(ah, chan); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return true; + } + +@@ -1817,8 +1836,14 @@ static int ath9k_hw_do_fastcc(struct ath + if (AR_SREV_9271(ah)) + ar9002_hw_load_ani_reg(ah, chan); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return 0; + fail: ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return -EINVAL; + } + +@@ -2043,6 +2068,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st + if (AR_SREV_9565(ah) && common->bt_ant_diversity) + REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return 0; + } + EXPORT_SYMBOL(ath9k_hw_reset); +--- a/drivers/net/wireless/ath/ath9k/phy.h ++++ b/drivers/net/wireless/ath/ath9k/phy.h +@@ -48,6 +48,9 @@ + #define AR_PHY_PLL_CONTROL 0x16180 + #define AR_PHY_PLL_MODE 0x16184 + ++#define AR_PHY_USB_CTRL1 0x16c84 ++#define AR_PHY_USB_CTRL2 0x16c88 ++ + enum ath9k_ant_div_comb_lna_conf { + ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, + ATH_ANT_DIV_COMB_LNA2, |