diff options
| author | John Crispin <john@openwrt.org> | 2011-10-10 15:14:17 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2011-10-10 15:14:17 +0000 |
| commit | 261389b709cb26f4eac6981d0a44ce77de284f2d (patch) | |
| tree | a0ade5dd7615822bcf8b71cc99be4a9672e20f8c /package | |
| parent | 0a866293bd9e204978c995cb0545c20f8ab63c7e (diff) | |
| download | upstream-261389b709cb26f4eac6981d0a44ce77de284f2d.tar.gz upstream-261389b709cb26f4eac6981d0a44ce77de284f2d.tar.bz2 upstream-261389b709cb26f4eac6981d0a44ce77de284f2d.zip | |
* add support for ar9
* add support for ase
(vr9 support is still a todo)
SVN-Revision: 28406
Diffstat (limited to 'package')
30 files changed, 10593 insertions, 566 deletions
diff --git a/package/ltq-dsl-app/Config.in b/package/ltq-dsl-app/Config.in index 5b8d609af1..c9a9a95637 100644 --- a/package/ltq-dsl-app/Config.in +++ b/package/ltq-dsl-app/Config.in @@ -1,6 +1,3 @@ -menu "Configuration" - depends on PACKAGE_ltq-dsl-app - config LTQ_DSL_ENABLE_CLI bool "Enable CLI support" depends on PACKAGE_ltq-dsl-app @@ -10,5 +7,3 @@ config LTQ_DSL_ENABLE_DSL_EVENT_POLLING bool "Include Event Polling support" depends on PACKAGE_ltq-dsl-app default n - -endmenu diff --git a/package/ltq-dsl-app/Makefile b/package/ltq-dsl-app/Makefile index fb3e4ac644..981a6a7961 100644 --- a/package/ltq-dsl-app/Makefile +++ b/package/ltq-dsl-app/Makefile @@ -22,12 +22,15 @@ PKG_CONFIG_DEPENDS:=\ include $(INCLUDE_DIR)/package.mk +PKG_BUILD_DEPENDS:=TARGET_lantiq_danube:kmod-ltq-dsl-danube TARGET_lantiq_ar9:kmod-ltq-dsl-ar9 \ + TARGET_lantiq_vr9:kmod-ltq-dsl-vr9 TARGET_lantiq_ase:kmod-ltq-dsl-ase + define Package/ltq-dsl-app SECTION:=net CATEGORY:=Network TITLE:=Lantiq DSL userland tool URL:=http://www.lantiq.com/ - DEPENDS:=@TARGET_lantiq_danube +kmod-ltq-dsl +libpthread + DEPENDS:=@TARGET_lantiq&&!(TARGET_lantiq_falcon||TARGET_lantiq_falcon_stable) +libpthread MAINTAINER:=John Crispin <blogic@openwrt.org> MENU:=1 endef diff --git a/package/ltq-dsl/Makefile b/package/ltq-dsl/Makefile index d645af7770..4a602e89d2 100644 --- a/package/ltq-dsl/Makefile +++ b/package/ltq-dsl/Makefile @@ -11,29 +11,32 @@ include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=ltq-dsl PKG_BASE_NAME:=drv_dsl_cpe_api_danube PKG_VERSION:=3.24.4.4 -PKG_RELEASE:=2 +PKG_RELEASE:=3 PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/drv_dsl_cpe_api-$(PKG_VERSION) PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/ PKG_MD5SUM:=c45bc531c1ed2ac80f68fb986b63bb87 -FW_BASE_NAME:=dsl_danube_firmware_adsl -FW_A_VER:=02.04.04.00.00.01 -FW_B_VER:=02.04.01.07.00.02 -FW_A_FILE_VER:=244001 -FW_B_FILE_VER:=241702 -FW_A_MD5:=f717db3067a0049a26e233ab11238710 -FW_B_MD5:=349de7cd20368f4ac9b7e8322114a512 +FW_NAME:=ltq-dsl-fw-0.1 +FW_MD5:=4700a36b66b955b4c5544227267356f4 include $(INCLUDE_DIR)/package.mk -define KernelPackage/ltq-dsl +define Download/ltq-dsl-fw + FILE:=$(FW_NAME).tar.bz2 + MD5SUM:=$(FW_MD5) + URL:=http://mirror2.openwrt.org/sources/ +endef +$(eval $(call Download,ltq-dsl-fw)) + +define KernelPackage/ltq-dsl-template SECTION:=sys CATEGORY:=Kernel modules SUBMENU:=Network Devices - TITLE:=Lantiq dsl driver + TITLE:=Lantiq dsl driver for $(1) URL:=http://www.lantiq.com/ - DEPENDS:=@TARGET_lantiq_danube +kmod-atm + VARIANT:=$(1) + DEPENDS:=@TARGET_lantiq_$(1) +kmod-atm FILES:=$(PKG_BUILD_DIR)/src/mei/lantiq_mei.ko \ $(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.ko \ $(PKG_BUILD_DIR)/src/mei/lantiq_atm.ko @@ -41,48 +44,39 @@ define KernelPackage/ltq-dsl MAINTAINER:=John Crispin <blogic@openwrt.org> endef -define Package/kmod-ltq-dsl-firmware/default +KernelPackage/ltq-dsl-danube=$(call KernelPackage/ltq-dsl-template,danube) +KernelPackage/ltq-dsl-ase=$(call KernelPackage/ltq-dsl-template,ase) +KernelPackage/ltq-dsl-ar9=$(call KernelPackage/ltq-dsl-template,ar9) +KernelPackage/ltq-dsl-vr9=$(call KernelPackage/ltq-dsl-template,vr9) + +define Package/kmod-ltq-dsl-firmware-template + TITLE+=Firmware Annex-$(1) $(2) SECTION:=sys CATEGORY:=Kernel modules SUBMENU:=Network Devices - TITLE:=Firmware + VARIANT:= $(1)-$(2) URL:=http://www.lantiq.com/ - DEPENDS:=@TARGET_lantiq_danube kmod-ltq-dsl + DEPENDS:=@TARGET_lantiq_$(2) kmod-ltq-dsl-$(2) MAINTAINER:=John Crispin <blogic@openwrt.org> endef -define Package/kmod-ltq-dsl-firmware-a - $(call Package/kmod-ltq-dsl-firmware/default) - TITLE+=Annex-A Danube -endef - -define Package/kmod-ltq-dsl-firmware-b - $(call Package/kmod-ltq-dsl-firmware/default) - TITLE+=Annex-B Danube -endef +Package/kmod-ltq-dsl-firmware-a-danube=$(call Package/kmod-ltq-dsl-firmware-template,a,danube) +Package/kmod-ltq-dsl-firmware-b-danube=$(call Package/kmod-ltq-dsl-firmware-template,b,danube) +Package/kmod-ltq-dsl-firmware-a-ase=$(call Package/kmod-ltq-dsl-firmware-template,a,ase) +Package/kmod-ltq-dsl-firmware-b-ase=$(call Package/kmod-ltq-dsl-firmware-template,b,ase) +Package/kmod-ltq-dsl-firmware-a-ar9=$(call Package/kmod-ltq-dsl-firmware-template,a,ar9) +Package/kmod-ltq-dsl-firmware-b-ar9=$(call Package/kmod-ltq-dsl-firmware-template,b,ar9) +Package/kmod-ltq-dsl-firmware-a-vr9=$(call Package/kmod-ltq-dsl-firmware-template,a,vr9) +Package/kmod-ltq-dsl-firmware-b-vr9=$(call Package/kmod-ltq-dsl-firmware-template,b,vr9) define KernelPackage/ltq-dsl/description - Lantiq DSL CPE API for Amazon SE, Danube and Vinax. + Lantiq DSL driver for AR9, Amazon SE, Danube and VR9 endef define KernelPackage/ltq-dsl/config source "$(SOURCE)/Config.in" endef -define Download/annex-a - FILE:=$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz - URL:=http://mirror2.openwrt.org/sources/ - MD5SUM:=$(FW_A_MD5) -endef -$(eval $(call Download,annex-a)) - -define Download/annex-b - FILE:=$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz - URL:=http://mirror2.openwrt.org/sources/ - MD5SUM:=$(FW_B_MD5) -endef -$(eval $(call Download,annex-b)) - IFX_DSL_MAX_DEVICE=1 IFX_DSL_LINES_PER_DEVICE=1 IFX_DSL_CHANNELS_PER_LINE=1 @@ -91,8 +85,6 @@ CONFIGURE_ARGS += --enable-kernel-include="$(LINUX_DIR)/include" \ --with-max-device="$(IFX_DSL_MAX_DEVICE)" \ --with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \ --with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \ - --enable-danube \ - --enable-add-drv-cflags="-DMODULE" \ --disable-dsl-delt-static \ --disable-adsl-led \ --enable-dsl-ceoc \ @@ -111,7 +103,17 @@ CONFIGURE_ARGS += --enable-kernel-include="$(LINUX_DIR)/include" \ --enable-kernelbuild="$(LINUX_DIR)" \ ARCH=$(LINUX_KARCH) -EXTRA_CFLAGS = -fno-pic -mno-abicalls -mlong-calls -G 0 +CONFIG_TAG_danube:=DANUBE +CONFIG_TAG_ase:=AMAZON_SE +CONFIG_TAG_ar9:=AR9 +CONFIG_TAG_vr9:=VR9 +CONFIGURE_ARGS += --enable-add-drv-cflags="-DMODULE -DCONFIG_$(CONFIG_TAG_$(BUILD_VARIANT))" + +ifeq ($(BUILD_VARIANT),vr9) +CONFIGURE_ARGS += --enable-vinax +else +CONFIGURE_ARGS += --enable-danube +endif ifeq ($(CONFIG_LANTIQ_DSL_DEBUG),y) CONFIGURE_ARGS += \ @@ -120,13 +122,14 @@ CONFIGURE_ARGS += \ EXTRA_CFLAGS += -DDEBUG endif +EXTRA_CFLAGS = -fno-pic -mno-abicalls -mlong-calls -G 0 + define Build/Prepare $(PKG_UNPACK) $(INSTALL_DIR) $(PKG_BUILD_DIR)/src/mei/ $(CP) ./src/* $(PKG_BUILD_DIR)/src/mei/ $(Build/Patch) - $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz - $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz + $(TAR) -C $(PKG_BUILD_DIR) -xjf $(DL_DIR)/$(FW_NAME).tar.bz2 endef define Build/Configure @@ -137,7 +140,7 @@ endef define Build/Compile cd $(LINUX_DIR); \ ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \ - $(MAKE) M=$(PKG_BUILD_DIR)/src/mei/ V=1 modules + BUILD_VARIANT=$(BUILD_VARIANT) $(MAKE) M=$(PKG_BUILD_DIR)/src/mei/ V=1 modules $(call Build/Compile/Default) endef @@ -155,16 +158,20 @@ define Build/InstallDev $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_cmv_danube.h $(1)/usr/include endef -define Package/kmod-ltq-dsl-firmware-a/install - $(INSTALL_DIR) $(1)/lib/firmware/ - $(CP) $(PKG_BUILD_DIR)/$(FW_BASE_NAME)_a_$(FW_A_FILE_VER).bin $(1)/lib/firmware/ModemHWE.bin -endef - -define Package/kmod-ltq-dsl-firmware-b/install +define Package/kmod-ltq-dsl-firmware-$(BUILD_VARIANT)/install $(INSTALL_DIR) $(1)/lib/firmware/ - $(CP) $(PKG_BUILD_DIR)/$(FW_BASE_NAME)_b_$(FW_B_FILE_VER).bin $(1)/lib/firmware/ModemHWE.bin + $(CP) $(PKG_BUILD_DIR)/$(FW_NAME)/ltq-dsl-fw-$(BUILD_VARIANT).bin $(1)/lib/firmware/ModemHWE.bin endef -$(eval $(call KernelPackage,ltq-dsl)) -$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a)) -$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b)) +$(eval $(call KernelPackage,ltq-dsl-danube)) +$(eval $(call KernelPackage,ltq-dsl-ase)) +$(eval $(call KernelPackage,ltq-dsl-ar9)) +#$(eval $(call KernelPackage,ltq-dsl-vr9)) +$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a-danube)) +$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b-danube)) +$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a-ase)) +$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b-ase)) +$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a-ar9)) +$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b-ar9)) +#$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-a-vr9)) +#$(eval $(call BuildPackage,kmod-ltq-dsl-firmware-b-vr9)) diff --git a/package/ltq-dsl/src/Makefile b/package/ltq-dsl/src/Makefile index 89c4e712d7..a923170981 100644 --- a/package/ltq-dsl/src/Makefile +++ b/package/ltq-dsl/src/Makefile @@ -1,3 +1,19 @@ obj-m = lantiq_mei.o lantiq_atm.o +lantiq_atm-objs := ifxmips_atm_core.o -lantiq_atm-objs := ifxmips_atm_core.o ifxmips_atm_danube.o +ifeq ($(BUILD_VARIANT),danube) + EXTRA_CFLAGS+=-DCONFIG_DANUBE + lantiq_atm-objs += ifxmips_atm_danube.o +endif +ifeq ($(BUILD_VARIANT),ase) + EXTRA_CFLAGS+=-DCONFIG_AMAZON_SE + lantiq_atm-objs += ifxmips_atm_amazon_se.o +endif +ifeq ($(BUILD_VARIANT),ar9) + EXTRA_CFLAGS+=-DCONFIG_AR9 + lantiq_atm-objs += ifxmips_atm_ar9.o +endif +ifeq ($(BUILD_VARIANT),vr9) + EXTRA_CFLAGS+=-DCONFIG_VR9 + lantiq_atm-objs += ifxmips_atm_vr9.o +endif diff --git a/package/ltq-dsl/src/ifx_atm.h b/package/ltq-dsl/src/ifx_atm.h index 32deca54e0..bf045a9754 100644 --- a/package/ltq-dsl/src/ifx_atm.h +++ b/package/ltq-dsl/src/ifx_atm.h @@ -26,10 +26,52 @@ +/*! + \defgroup IFX_ATM UEIP Project - ATM driver module + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. + */ + +/*! + \defgroup IFX_ATM_IOCTL IOCTL Commands + \ingroup IFX_ATM + \brief IOCTL Commands used by user application. + */ + +/*! + \defgroup IFX_ATM_STRUCT Structures + \ingroup IFX_ATM + \brief Structures used by user application. + */ + +/*! + \file ifx_atm.h + \ingroup IFX_ATM + \brief ATM driver header file + */ + + + +/* + * #################################### + * Definition + * #################################### + */ + +/*! + \addtogroup IFX_ATM_STRUCT + */ +/*@{*/ + /* * ATM MIB */ +/*! + \struct atm_cell_ifEntry_t + \brief Structure used for Cell Level MIB Counters. + + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". + */ typedef struct { __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ @@ -40,6 +82,12 @@ typedef struct { __u32 ifOutErrors; /*!< counter of error egress cells */ } atm_cell_ifEntry_t; +/*! + \struct atm_aal5_ifEntry_t + \brief Structure used for AAL5 Frame Level MIB Counters. + + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". + */ typedef struct { __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ @@ -53,18 +101,48 @@ typedef struct { __u32 ifOutDiscards; /*!< counter of dropped egress packets */ } atm_aal5_ifEntry_t; +/*! + \struct atm_aal5_vcc_t + \brief Structure used for per PVC AAL5 Frame Level MIB Counters. + + This structure is a part of structure "atm_aal5_vcc_x_t". + */ typedef struct { __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ } atm_aal5_vcc_t; +/*! + \struct atm_aal5_vcc_x_t + \brief Structure used for per PVC AAL5 Frame Level MIB Counters. + + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". + */ typedef struct { int vpi; /*!< VPI of the VCC to get MIB counters */ int vci; /*!< VCI of the VCC to get MIB counters */ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ } atm_aal5_vcc_x_t; +/*@}*/ + + + +/* + * #################################### + * IOCTL + * #################################### + */ + +/*! + \addtogroup IFX_ATM_IOCTL + */ +/*@{*/ + +/* + * ioctl Command + */ /*! \brief ATM IOCTL Magic Number */ @@ -99,10 +177,20 @@ typedef struct { +/* + * #################################### + * API + * #################################### + */ + #ifdef __KERNEL__ struct port_cell_info { unsigned int port_num; unsigned int tx_link_rate[2]; }; #endif -#endif + + + +#endif // IFX_ATM_H + diff --git a/package/ltq-dsl/src/ifxmips_atm_amazon_se.c b/package/ltq-dsl/src/ifxmips_atm_amazon_se.c new file mode 100644 index 0000000000..35a5cd9d53 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_amazon_se.c @@ -0,0 +1,319 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_amazon_se.c +** PROJECT : UEIP +** MODULES : ATM +** +** DATE : 7 Jul 2009 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM driver common source file (core functions) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 07 JUL 2009 Xu Liang Init Version +*******************************************************************************/ + + + +/* + * #################################### + * Head File + * #################################### + */ + +/* + * Common Head File + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/version.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/proc_fs.h> +#include <linux/init.h> +#include <linux/ioctl.h> +#include <asm/delay.h> + +/* + * Chip Specific Head File + */ +#include <lantiq_soc.h> +#include "ifxmips_compat.h" +#include "ifxmips_atm_core.h" +#include "ifxmips_atm_fw_amazon_se.h" + + + +/* + * #################################### + * Definition + * #################################### + */ + +/* + * EMA Settings + */ +#define EMA_CMD_BUF_LEN 0x0040 +#define EMA_CMD_BASE_ADDR (0x00001580 << 2) +#define EMA_DATA_BUF_LEN 0x0100 +#define EMA_DATA_BASE_ADDR (0x00000B00 << 2) +#define EMA_WRITE_BURST 0x2 +#define EMA_READ_BURST 0x2 + + + +/* + * #################################### + * Declaration + * #################################### + */ + +/* + * Hardware Init/Uninit Functions + */ +static inline void init_pmu(void); +static inline void uninit_pmu(void); +static inline void reset_ppe(void); +static inline void init_ema(void); +static inline void init_mailbox(void); +static inline void init_atm_tc(void); +static inline void clear_share_buffer(void); + + + +/* + * #################################### + * Local Variable + * #################################### + */ + + + +/* + * #################################### + * Local Function + * #################################### + */ + +static inline void init_pmu(void) +{ + //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9)); + //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); + PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); + PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); + PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); + //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); + PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); + DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE); +} + +static inline void uninit_pmu(void) +{ + PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE); + PPE_TC_PMU_SETUP(IFX_PMU_DISABLE); + PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE); + //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE); + PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE); + DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE); + //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); +} + +static inline void reset_ppe(void) +{ +#ifdef MODULE +/* unsigned int etop_cfg; + unsigned int etop_mdio_cfg; + unsigned int etop_ig_plen_ctrl; + unsigned int enet_mac_cfg; + + etop_cfg = *IFX_PP32_ETOP_CFG; + etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG; + etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL; + enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG; + + *IFX_PP32_ETOP_CFG = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001; + + // reset PPE + ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM); + + *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg; + *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl; + *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg; + *IFX_PP32_ETOP_CFG = etop_cfg;*/ +#endif +} + +static inline void init_ema(void) +{ + IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG); + IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG); + IFX_REG_W32(0x000000FF, EMA_IER); + IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG); +} + +static inline void init_mailbox(void) +{ + IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); + IFX_REG_W32(0x00000000, MBOX_IGU1_IER); + IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); + IFX_REG_W32(0x00000000, MBOX_IGU3_IER); +} + +static inline void init_atm_tc(void) +{ + IFX_REG_W32(0x0000, DREG_AT_CTRL); + IFX_REG_W32(0x0000, DREG_AR_CTRL); + IFX_REG_W32(0x0, DREG_AT_IDLE0); + IFX_REG_W32(0x0, DREG_AT_IDLE1); + IFX_REG_W32(0x0, DREG_AR_IDLE0); + IFX_REG_W32(0x0, DREG_AR_IDLE1); + IFX_REG_W32(0x40, RFBI_CFG); + IFX_REG_W32(0x0700, SFSM_DBA0); + IFX_REG_W32(0x0818, SFSM_DBA1); + IFX_REG_W32(0x0930, SFSM_CBA0); + IFX_REG_W32(0x0944, SFSM_CBA1); + IFX_REG_W32(0x14014, SFSM_CFG0); + IFX_REG_W32(0x14014, SFSM_CFG1); + IFX_REG_W32(0x0958, FFSM_DBA0); + IFX_REG_W32(0x09AC, FFSM_DBA1); + IFX_REG_W32(0x10006, FFSM_CFG0); + IFX_REG_W32(0x10006, FFSM_CFG1); + IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0); + IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1); +} + +static inline void clear_share_buffer(void) +{ + volatile u32 *p = SB_RAM0_ADDR(0); + unsigned int i; + + for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ ) + IFX_REG_W32(0, p++); +} + +/* + * Description: + * Download PPE firmware binary code. + * Input: + * src --- u32 *, binary code buffer + * dword_len --- unsigned int, binary code length in DWORD (32-bit) + * Output: + * int --- IFX_SUCCESS: Success + * else: Error Code + */ +static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +{ + volatile u32 *dest; + + if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 + || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) + return IFX_ERROR; + + if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) + IFX_REG_W32(0x00, CDM_CFG); + else + IFX_REG_W32(0x04, CDM_CFG); + + /* copy code */ + dest = CDM_CODE_MEMORY(0, 0); + while ( code_dword_len-- > 0 ) + IFX_REG_W32(*code_src++, dest++); + + /* copy data */ + dest = CDM_DATA_MEMORY(0, 0); + while ( data_dword_len-- > 0 ) + IFX_REG_W32(*data_src++, dest++); + + return IFX_SUCCESS; +} + + + +/* + * #################################### + * Global Function + * #################################### + */ + +extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor) +{ + ASSERT(major != NULL, "pointer is NULL"); + ASSERT(minor != NULL, "pointer is NULL"); + +#ifdef VER_IN_FIRMWARE + *major = FW_VER_ID->major; + *minor = FW_VER_ID->minor; +#else + *major = ATM_FW_VER_MAJOR; + *minor = ATM_FW_VER_MINOR; +#endif +} + +void ifx_atm_init_chip(void) +{ + init_pmu(); + + reset_ppe(); + + init_ema(); + + init_mailbox(); + + init_atm_tc(); + + clear_share_buffer(); +} + +void ifx_atm_uninit_chip(void) +{ + uninit_pmu(); +} + +/* + * Description: + * Initialize and start up PP32. + * Input: + * none + * Output: + * int --- IFX_SUCCESS: Success + * else: Error Code + */ +int ifx_pp32_start(int pp32) +{ + int ret; + + /* download firmware */ + ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data)); + if ( ret != IFX_SUCCESS ) + return ret; + + /* run PP32 */ + IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL); + + /* idle for a while to let PP32 init itself */ + udelay(10); + + return IFX_SUCCESS; +} + +/* + * Description: + * Halt PP32. + * Input: + * none + * Output: + * none + */ +void ifx_pp32_stop(int pp32) +{ + /* halt PP32 */ + IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL); +} diff --git a/package/ltq-dsl/src/ifxmips_atm_ar9.c b/package/ltq-dsl/src/ifxmips_atm_ar9.c new file mode 100644 index 0000000000..418863c512 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_ar9.c @@ -0,0 +1,290 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_ar9.c +** PROJECT : UEIP +** MODULES : ATM +** +** DATE : 7 Jul 2009 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM driver common source file (core functions) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 07 JUL 2009 Xu Liang Init Version +*******************************************************************************/ + + + +/* + * #################################### + * Head File + * #################################### + */ + +/* + * Common Head File + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/version.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/proc_fs.h> +#include <linux/init.h> +#include <linux/ioctl.h> +#include <asm/delay.h> + +/* + * Chip Specific Head File + */ +#include <lantiq_soc.h> +#include "ifxmips_compat.h" +#define IFX_MEI_BSP 1 +#include "ifxmips_mei_interface.h" +#include "ifxmips_atm_core.h" +#include "ifxmips_atm_ppe_common.h" + #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + #include "ifxmips_atm_fw_ar9_retx.h" +#else + #include "ifxmips_atm_fw_ar9.h" +#endif + + + +/* + * #################################### + * Definition + * #################################### + */ + +/* + * EMA Settings + */ +#define EMA_CMD_BUF_LEN 0x0040 +#define EMA_CMD_BASE_ADDR (0x00003B80 << 2) +#define EMA_DATA_BUF_LEN 0x0100 +#define EMA_DATA_BASE_ADDR (0x00003C00 << 2) +#define EMA_WRITE_BURST 0x2 +#define EMA_READ_BURST 0x2 + + + +/* + * #################################### + * Declaration + * #################################### + */ + +/* + * Hardware Init/Uninit Functions + */ +static inline void init_pmu(void); +static inline void uninit_pmu(void); +static inline void reset_ppe(void); +static inline void init_ema(void); +static inline void init_mailbox(void); +static inline void init_atm_tc(void); +static inline void clear_share_buffer(void); + + + +/* + * #################################### + * Local Variable + * #################################### + */ + + + +/* + * #################################### + * Local Function + * #################################### + */ + +static inline void init_pmu(void) +{ + //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9)); + //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); + PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); + PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); + PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); + PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); + PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); + DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE); +} + +static inline void uninit_pmu(void) +{ + PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE); + PPE_TC_PMU_SETUP(IFX_PMU_DISABLE); + PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE); + PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE); + PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE); + DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE); + //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); +} + +static inline void reset_ppe(void) +{ +#ifdef MODULE + // reset PPE + //ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM); +#endif +} + +static inline void init_ema(void) +{ + IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG); + IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG); + IFX_REG_W32(0x000000FF, EMA_IER); + IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG); +} + +static inline void init_mailbox(void) +{ + IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); + IFX_REG_W32(0x00000000, MBOX_IGU1_IER); + IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); + IFX_REG_W32(0x00000000, MBOX_IGU3_IER); +} + +static inline void init_atm_tc(void) +{ +} + +static inline void clear_share_buffer(void) +{ + volatile u32 *p = SB_RAM0_ADDR(0); + unsigned int i; + + for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ ) + IFX_REG_W32(0, p++); +} + +/* + * Description: + * Download PPE firmware binary code. + * Input: + * src --- u32 *, binary code buffer + * dword_len --- unsigned int, binary code length in DWORD (32-bit) + * Output: + * int --- IFX_SUCCESS: Success + * else: Error Code + */ +static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +{ + volatile u32 *dest; + + if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 + || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) + return IFX_ERROR; + + if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) + IFX_REG_W32(0x00, CDM_CFG); + else + IFX_REG_W32(0x04, CDM_CFG); + + /* copy code */ + dest = CDM_CODE_MEMORY(0, 0); + while ( code_dword_len-- > 0 ) + IFX_REG_W32(*code_src++, dest++); + + /* copy data */ + dest = CDM_DATA_MEMORY(0, 0); + while ( data_dword_len-- > 0 ) + IFX_REG_W32(*data_src++, dest++); + + return IFX_SUCCESS; +} + + + +/* + * #################################### + * Global Function + * #################################### + */ + +extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor) +{ + ASSERT(major != NULL, "pointer is NULL"); + ASSERT(minor != NULL, "pointer is NULL"); + +#if (defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX) || defined(VER_IN_FIRMWARE) + *major = FW_VER_ID->major; + *minor = FW_VER_ID->minor; +#else + *major = ATM_FW_VER_MAJOR; + *minor = ATM_FW_VER_MINOR; +#endif +} + +void ifx_atm_init_chip(void) +{ + init_pmu(); + + reset_ppe(); + + init_ema(); + + init_mailbox(); + + init_atm_tc(); + + clear_share_buffer(); +} + +void ifx_atm_uninit_chip(void) +{ + uninit_pmu(); +} + +/* + * Description: + * Initialize and start up PP32. + * Input: + * none + * Output: + * int --- IFX_SUCCESS: Success + * else: Error Code + */ +int ifx_pp32_start(int pp32) +{ + int ret; + + /* download firmware */ + ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data)); + if ( ret != IFX_SUCCESS ) + return ret; + + /* run PP32 */ + IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0)); + + /* idle for a while to let PP32 init itself */ + udelay(10); + + return IFX_SUCCESS; +} + +/* + * Description: + * Halt PP32. + * Input: + * none + * Output: + * none + */ +void ifx_pp32_stop(int pp32) +{ + /* halt PP32 */ + IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0)); +} diff --git a/package/ltq-dsl/src/ifxmips_atm_core.c b/package/ltq-dsl/src/ifxmips_atm_core.c index 49a31fc591..70ea2729ab 100644 --- a/package/ltq-dsl/src/ifxmips_atm_core.c +++ b/package/ltq-dsl/src/ifxmips_atm_core.c @@ -31,7 +31,7 @@ #define IFX_ATM_VER_MAJOR 1 #define IFX_ATM_VER_MID 0 -#define IFX_ATM_VER_MINOR 8 +#define IFX_ATM_VER_MINOR 19 @@ -45,6 +45,7 @@ * Common Head File */ #include <linux/kernel.h> +#include <linux/vmalloc.h> #include <linux/module.h> #include <linux/version.h> #include <linux/types.h> @@ -60,6 +61,9 @@ * Chip Specific Head File */ #include <lantiq_soc.h> +#include "ifxmips_compat.h" +#define IFX_MEI_BSP 1 +#include "ifxmips_mei_interface.h" #include "ifxmips_atm_core.h" @@ -182,7 +186,9 @@ MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cel * #################################### */ -#define DUMP_SKB_LEN ~0 +#define ENABLE_LED_FRAMEWORK 1 + +#define DUMP_SKB_LEN ~0 @@ -205,7 +211,7 @@ static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int); /* * ADSL LED */ -static INLINE int adsl_led_flash(void); +static INLINE void adsl_led_flash(void); /* * 64-bit operation used by MIB calculation @@ -251,13 +257,28 @@ static INLINE int find_vpivci(unsigned int, unsigned int); static INLINE int find_vcc(struct atm_vcc *); /* + * ReTX functions + */ +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + static void retx_polling_func(unsigned long); + static int init_atm_tc_retrans_param(void); + static void clear_atm_tc_retrans_param(void); +#endif + + +/* * Debug Functions */ #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB - static void dump_skb(struct sk_buff *, u32, char *, int, int, int); + static void dump_skb(struct sk_buff *, unsigned int, char *, int, int, int); #else #define dump_skb(skb, len, title, port, ch, is_tx) do {} while (0) #endif +#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC + static void skb_swap(struct sk_buff *, unsigned int); +#else + #define skb_swap(skb, byteoff) do {} while (0) +#endif /* * Proc File Functions @@ -267,13 +288,30 @@ static INLINE void proc_file_delete(void); static int proc_read_version(char *, char **, off_t, int, int *, void *); static int proc_read_mib(char *, char **, off_t, int, int *, void *); static int proc_write_mib(struct file *, const char *, unsigned long, void *); +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + static int proc_read_retx_mib(char *, char **, off_t, int, int *, void *); + static int proc_write_retx_mib(struct file *, const char *, unsigned long, void *); +#endif #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC static int proc_read_dbg(char *, char **, off_t, int, int *, void *); static int proc_write_dbg(struct file *, const char *, unsigned long, void *); + static int proc_write_mem(struct file *, const char *, unsigned long, void *); + #if defined(CONFIG_AR9) || defined(CONFIG_VR9) || defined(CONFIG_DANUBE) || defined(CONFIG_AMAZON_SE) + static int proc_read_pp32(char *, char **, off_t, int, int *, void *); + static int proc_write_pp32(struct file *, const char *, unsigned long, void *); + #endif #endif #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC static int proc_read_htu(char *, char **, off_t, int, int *, void *); static int proc_read_txq(char *, char **, off_t, int, int *, void *); + #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + static int proc_read_retx_fw(char *, char **, off_t, int, int *, void *); + static int proc_read_retx_stats(char *, char **, off_t, int, int *, void *); + static int proc_write_retx_stats(struct file *, const char *, unsigned long, void *); + static int proc_read_retx_cfg(char *, char **, off_t, int, int *, void *); + static int proc_write_retx_cfg(struct file *, const char *, unsigned long, void *); + static int proc_read_retx_dsl_param(char *, char **, off_t, int, int *, void *); + #endif #endif /* @@ -282,17 +320,15 @@ static int proc_write_mib(struct file *, const char *, unsigned long, void *); static int stricmp(const char *, const char *); #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC static int strincmp(const char *, const char *, int); + static int get_token(char **, char **, int *, int *); + static unsigned int get_number(char **, int *, int); + static void ignore_space(char **, int *); #endif static INLINE int ifx_atm_version(char *); -//static INLINE int print_reset_domain(char *, int); -//static INLINE int print_reset_handler(char *, int, ifx_rcu_handler_t *); /* * Init & clean-up functions */ -#ifdef MODULE - static INLINE void reset_ppe(void); -#endif static INLINE void check_parameters(void); static INLINE int init_priv_data(void); static INLINE void clear_priv_data(void); @@ -308,10 +344,14 @@ static INLINE void init_tx_tables(void); static inline void ifx_push_oam(unsigned char *dummy) {} #endif #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE) - extern int ifx_mei_atm_led_blink(void); - extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr); + #if !defined(ENABLE_LED_FRAMEWORK) || !ENABLE_LED_FRAMEWORK + extern int ifx_mei_atm_led_blink(void) __attribute__ ((weak)); + #endif + extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr) __attribute__ ((weak)); #else + #if !defined(ENABLE_LED_FRAMEWORK) || !ENABLE_LED_FRAMEWORK static inline int ifx_mei_atm_led_blink(void) { return IFX_SUCCESS; } + #endif static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr) { if ( is_showtime != NULL ) @@ -323,10 +363,13 @@ static INLINE void init_tx_tables(void); /* * External variable */ -extern struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int); +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; + + +//extern struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int); #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE) - extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *); - extern int (*ifx_mei_atm_showtime_exit)(void); + extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) __attribute__ ((weak)); + extern int (*ifx_mei_atm_showtime_exit)(void) __attribute__ ((weak)); #else int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL; EXPORT_SYMBOL(ifx_mei_atm_showtime_enter); @@ -349,8 +392,8 @@ static struct atmdev_ops g_ifx_atm_ops = { .close = ppe_close, .ioctl = ppe_ioctl, .send = ppe_send, - .send_oam = ppe_send_oam, - .change_qos = ppe_change_qos, + .send_oam = ppe_send_oam, + .change_qos = ppe_change_qos, .owner = THIS_MODULE, }; @@ -361,6 +404,20 @@ static struct atmdev_ops g_ifx_atm_ops = { static int g_showtime = 0; static void *g_xdata_addr = NULL; +#if 0 /*--- defined(ENABLE_LED_FRAMEWORK) && ENABLE_LED_FRAMEWORK ---*/ + static void *g_data_led_trigger = NULL; +#endif + +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + static unsigned long g_retx_playout_buffer = 0; + + static volatile int g_retx_htu = 1; + static struct dsl_param g_dsl_param = {0}; + static int g_retx_polling_cnt = HZ; + static struct timeval g_retx_polling_start = {0}, g_retx_polling_end = {0}; + static struct timer_list g_retx_polling_timer; +#endif + unsigned int ifx_atm_dbg_enable = 0; static struct proc_dir_entry* g_atm_dir = NULL; @@ -467,16 +524,42 @@ static int ppe_open(struct atm_vcc *vcc) if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 ) return -EPROTONOSUPPORT; +#if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND /* check bandwidth */ - if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) - || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) - || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) - || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) ) + + if (vcc->qos.txtp.traffic_class == ATM_CBR && + vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) { + printk("CBR set. %s, line %d returns EINVAL\n", __FUNCTION__, __LINE__); + ret = -EINVAL; + goto PPE_OPEN_EXIT; + } + if(vcc->qos.txtp.traffic_class == ATM_VBR_RT && + vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) + { + printk("VBR RT set. %s, line %d returns EINVAL\n", __FUNCTION__, __LINE__); + ret = -EINVAL; + goto PPE_OPEN_EXIT; + } + + if (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && + vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) + { + printk("VBR NRT set. %s, line %d returns EINVAL\n", __FUNCTION__, __LINE__); + ret = -EINVAL; + goto PPE_OPEN_EXIT; + } + + if (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && + vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) + { + printk("UBR PLUS set. %s, line %d returns EINVAL\n", __FUNCTION__, __LINE__); ret = -EINVAL; goto PPE_OPEN_EXIT; } +#endif + /* check existing vpi,vci */ conn = find_vpivci(vpi, vci); if ( conn >= 0 ) { @@ -497,6 +580,7 @@ static int ppe_open(struct atm_vcc *vcc) } if ( conn == MAX_PVC_NUMBER ) { + printk("max_pvc_number reached\n"); ret = -EINVAL; goto PPE_OPEN_EXIT; } @@ -535,7 +619,7 @@ static int ppe_open(struct atm_vcc *vcc) } /* set port */ - WTX_QUEUE_CONFIG(conn)->sbid = (int)vcc->dev->dev_data; + WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data; /* set htu entry */ set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0); @@ -566,6 +650,9 @@ static void ppe_close(struct atm_vcc *vcc) int conn; struct port *port; struct connection *connection; +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + int sys_flag; +#endif if ( vcc == NULL ) return; @@ -582,11 +669,29 @@ static void ppe_close(struct atm_vcc *vcc) /* clear htu */ clear_htu_entry(conn); +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + // ReTX: release second QID + local_irq_save(sys_flag); + if ( g_retx_htu && vcc->qos.aal == ATM_AAL5 ) + { + int retx_conn = (conn + 8) % 16; // ReTX queue + + if ( retx_conn < MAX_PVC_NUMBER && g_atm_priv_data.conn[retx_conn].vcc == vcc ) { + clear_htu_entry(retx_conn); + g_atm_priv_data.conn[retx_conn].vcc = NULL; + g_atm_priv_data.conn[retx_conn].aal5_vcc_crc_err = 0; + g_atm_priv_data.conn[retx_conn].aal5_vcc_oversize_sdu = 0; + clear_bit(retx_conn, &g_atm_priv_data.conn_table); + } + } + local_irq_restore(sys_flag); +#endif + /* release connection */ - clear_bit(conn, &g_atm_priv_data.conn_table); connection->vcc = NULL; connection->aal5_vcc_crc_err = 0; connection->aal5_vcc_oversize_sdu = 0; + clear_bit(conn, &g_atm_priv_data.conn_table); /* disable irq */ if ( g_atm_priv_data.conn_table == 0 ) { @@ -623,6 +728,7 @@ static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb) if ( vcc == NULL || skb == NULL ) return -EINVAL; + skb_orphan(skb); skb_get(skb); atm_free_tx_skb_vcc(skb, vcc); @@ -732,9 +838,14 @@ static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb) g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb; /* write discriptor to memory and write back cache */ - g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc; +#ifdef CONFIG_DEBUG_SLAB + /* be sure that "redzone 1" is written back to memory */ + dma_cache_wback((unsigned long)skb->head, 32); +#endif + dma_cache_wback((unsigned long)skb_shinfo(skb), sizeof(struct skb_shared_info)); dma_cache_wback((unsigned long)skb->data, skb->len); - + g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc; + dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1); mailbox_signal(conn, 1); @@ -820,6 +931,10 @@ static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags) dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1); + if ( vcc->qos.aal == ATM_AAL5 && (ifx_atm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ) { + skb_swap(skb, reg_desc.byteoff); + } + mailbox_signal(conn, 1); adsl_led_flash(); @@ -843,9 +958,17 @@ static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) return 0; } -static INLINE int adsl_led_flash(void) +static INLINE void adsl_led_flash(void) { - return ifx_mei_atm_led_blink(); +#if 0 +#if defined(ENABLE_LED_FRAMEWORK) && ENABLE_LED_FRAMEWORK + if ( g_data_led_trigger != NULL ) + ifx_led_trigger_activate(g_data_led_trigger); +#else + if (!IS_ERR(&ifx_mei_atm_led_blink) && &ifx_mei_atm_led_blink ) + ifx_mei_atm_led_blink(); +#endif +#endif } /* @@ -997,7 +1120,6 @@ static INLINE void mailbox_oam_rx_handler(void) vcc->push_oam(vcc, header); else ifx_push_oam((unsigned char *)header); - adsl_led_flash(); } @@ -1133,14 +1255,19 @@ static irqreturn_t mailbox_irq_handler(int irq, void *dev_id) static INLINE void mailbox_signal(unsigned int queue, int is_tx) { + int count = 1000; + if ( is_tx ) { - while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) ); + while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count) + count--; *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16); } else { - while ( MBOX_IGU3_ISR_ISR(queue) ); + while ( MBOX_IGU3_ISR_ISR(queue) && count) + count--; *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue); } + ASSERT(count != 0, "MBOX_IGU3_ISR = 0x%08x", ltq_r32(MBOX_IGU3_ISR)); } static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue) @@ -1482,8 +1609,225 @@ static INLINE int find_vcc(struct atm_vcc *vcc) return -1; } +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + +static void retx_polling_func(unsigned long arg) +{ + int sys_flag; + volatile struct dsl_param *p_dsl_param; + int new_retx_htu; + int retx_en; + int i, max_htu; + + local_irq_save(sys_flag); + if ( g_retx_playout_buffer == 0 && g_xdata_addr != NULL && (((volatile struct dsl_param *)g_xdata_addr)->RetxEnable || ((volatile struct dsl_param *)g_xdata_addr)->ServiceSpecificReTx) ) { + local_irq_restore(sys_flag); + g_retx_playout_buffer = __get_free_pages(GFP_KERNEL, RETX_PLAYOUT_BUFFER_ORDER); + if ( g_retx_playout_buffer == 0 ) + panic("no memory for g_retx_playout_buffer\n"); + memset((void *)g_retx_playout_buffer, 0, RETX_PLAYOUT_BUFFER_SIZE); + dma_cache_inv(g_retx_playout_buffer, RETX_PLAYOUT_BUFFER_SIZE); + } + else + local_irq_restore(sys_flag); + + + local_irq_save(sys_flag); + if ( g_xdata_addr != NULL ) { + p_dsl_param = (volatile struct dsl_param *)g_xdata_addr; + g_retx_polling_cnt += RETX_POLLING_INTERVAL; + + if ( p_dsl_param->update_flag ) { + do_gettimeofday(&g_retx_polling_start); + + g_dsl_param = *p_dsl_param; + + // we always enable retx (just for test purpose) + //g_dsl_param.RetxEnable = 1; + //RETX_TSYNC_CFG->fw_alpha = 0; + + if ( g_dsl_param.RetxEnable || g_dsl_param.ServiceSpecificReTx ) { + // ReTX enabled + // MIB counter updated for each polling + p_dsl_param->RxDtuCorruptedCNT = *RxDTUCorruptedCNT; + p_dsl_param->RxRetxDtuUnCorrectedCNT = *RxRetxDTUUncorrectedCNT; + p_dsl_param->RxLastEFB = *RxLastEFBCNT; + p_dsl_param->RxDtuCorrectedCNT = *RxDTUCorrectedCNT; + + // for RETX paramters, we check only once for every second + if ( g_retx_polling_cnt < HZ ) + goto _clear_update_flag; + + g_retx_polling_cnt -= HZ; + + if ( g_dsl_param.ServiceSpecificReTx && g_dsl_param.ReTxPVC == 0 ) + new_retx_htu = 1; + else + new_retx_htu = 0; + + // default fw_alpha equals to default hardware alpha + RETX_TSYNC_CFG->fw_alpha = 0; + + RETX_TD_CFG->td_max = g_dsl_param.MaxDelayrt; + RETX_TD_CFG->td_min = g_dsl_param.MinDelayrt; + + *RETX_PLAYOUT_BUFFER_BASE = ((((unsigned int)g_retx_playout_buffer | KSEG1) + 15) & 0xFFFFFFF0) >> 2; + + if ( g_dsl_param.ServiceSpecificReTx ) { + *RETX_SERVICE_HEADER_CFG= g_dsl_param.ReTxPVC << 4; + if ( g_dsl_param.ReTxPVC == 0 ) + *RETX_MASK_HEADER_CFG = 1; + else + *RETX_MASK_HEADER_CFG = 0; + } + else { + *RETX_SERVICE_HEADER_CFG= 0; + *RETX_MASK_HEADER_CFG = 0; + } + + retx_en = 1; + } + else { + // ReTX disabled + + new_retx_htu = 0; + + RETX_TSYNC_CFG->fw_alpha = 7; + + *RETX_SERVICE_HEADER_CFG = 0; + *RETX_MASK_HEADER_CFG = 0; + + retx_en = 0; + } + + + if ( retx_en != RETX_MODE_CFG->retx_en ) { + unsigned int pid_mask, vci_mask; + + if ( retx_en ) { + pid_mask = 0x03; + vci_mask = 0xFF00; + } + else { + pid_mask = 0x02; + vci_mask = 0x0000; + } + + max_htu = *CFG_WRX_HTUTS; + for ( i = OAM_HTU_ENTRY_NUMBER; i < max_htu; i++ ) + if ( HTU_ENTRY(i)->vld ) { + HTU_MASK(i)->pid_mask = pid_mask; + HTU_MASK(i)->vci_mask = vci_mask; + } + } + + if ( new_retx_htu != g_retx_htu ) { + int conn, retx_conn; + + g_retx_htu = new_retx_htu; + + if ( g_retx_htu ) { + max_htu = *CFG_WRX_HTUTS; + for ( i = OAM_HTU_ENTRY_NUMBER; i < max_htu; i++ ) + if ( HTU_ENTRY(i)->vld ) + HTU_MASK(i)->clp = 0; + + for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) + if ( g_atm_priv_data.conn[conn].vcc && g_atm_priv_data.conn[conn].vcc->qos.aal == ATM_AAL5 && !HTU_ENTRY(conn + OAM_HTU_ENTRY_NUMBER)->clp ) { + retx_conn = (conn + 8) % 16; // ReTX queue + + if ( retx_conn < MAX_PVC_NUMBER && test_and_set_bit(retx_conn, &g_atm_priv_data.conn_table) == 0 ) { + g_atm_priv_data.conn[retx_conn].vcc = g_atm_priv_data.conn[conn].vcc; + set_htu_entry(g_atm_priv_data.conn[conn].vcc->vpi, g_atm_priv_data.conn[conn].vcc->vci, retx_conn, g_atm_priv_data.conn[conn].vcc->qos.aal == ATM_AAL5 ? 1 : 0, 1); + } + else { + err("Queue number %d for ReTX queue of PVC(%d.%d) is not available!", retx_conn, g_atm_priv_data.conn[conn].vcc->vpi, g_atm_priv_data.conn[conn].vcc->vci); + } + } + } + else + { + for ( retx_conn = 0; retx_conn < MAX_PVC_NUMBER; retx_conn++ ) + if ( g_atm_priv_data.conn[retx_conn].vcc && HTU_ENTRY(retx_conn + OAM_HTU_ENTRY_NUMBER)->clp ) { + clear_htu_entry(retx_conn); + g_atm_priv_data.conn[retx_conn].vcc = NULL; + g_atm_priv_data.conn[retx_conn].aal5_vcc_crc_err = 0; + g_atm_priv_data.conn[retx_conn].aal5_vcc_oversize_sdu = 0; + clear_bit(retx_conn, &g_atm_priv_data.conn_table); + } + + max_htu = *CFG_WRX_HTUTS; + for ( i = OAM_HTU_ENTRY_NUMBER; i < max_htu; i++ ) + if ( HTU_ENTRY(i)->vld ) + HTU_MASK(i)->clp = 1; + } + } + + RETX_MODE_CFG->retx_en = retx_en; + +_clear_update_flag: + p_dsl_param->update_flag = 0; + + do_gettimeofday(&g_retx_polling_end); + } + + g_retx_polling_timer.expires = jiffies + RETX_POLLING_INTERVAL; + add_timer(&g_retx_polling_timer); + } + local_irq_restore(sys_flag); +} + +static int init_atm_tc_retrans_param(void) +{ + int i = 0; + struct DTU_stat_info reset_val; + + RETX_MODE_CFG->invld_range = 128; + RETX_MODE_CFG->buff_size = RETX_PLAYOUT_FW_BUFF_SIZE > 4096/32 ? 4096/32 : RETX_PLAYOUT_FW_BUFF_SIZE ; + RETX_MODE_CFG->retx_en = 1; + + // default fw_alpha equals to default hardware alpha + RETX_TSYNC_CFG->fw_alpha = 7; + RETX_TSYNC_CFG->sync_inp = 0; + + RETX_TD_CFG->td_max = 0; + RETX_TD_CFG->td_min = 0; + + // *RETX_PLAYOUT_BUFFER_BASE = KSEG1ADDR(g_retx_playout_buffer); // need " >> 2 " ? + *RETX_PLAYOUT_BUFFER_BASE = ((((unsigned int)g_retx_playout_buffer | KSEG1) + 15) & 0xFFFFFFF0) >> 2; + + *RETX_SERVICE_HEADER_CFG = 0; + *RETX_MASK_HEADER_CFG = 0; + + // 20us + RETX_MIB_TIMER_CFG->tick_cycle = 4800; + RETX_MIB_TIMER_CFG->ticks_per_sec = 50000; + + *LAST_DTU_SID_IN = 255; + *RFBI_FIRST_CW = 1; + // init DTU_STAT_INFO + + memset(&reset_val, 0, sizeof(reset_val)); + reset_val.dtu_rd_ptr = reset_val.dtu_wr_ptr = 0xffff; + + for(i = 0 ; i < 256; i ++) { + DTU_STAT_INFO[i] = reset_val; + } + return 0; +} + +static void clear_atm_tc_retrans_param(void) +{ + if ( g_retx_playout_buffer ) { + free_pages(g_retx_playout_buffer, RETX_PLAYOUT_BUFFER_ORDER); + g_retx_playout_buffer = 0; + } +} + +#endif + #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB -static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch, int is_tx) +static void dump_skb(struct sk_buff *skb, unsigned int len, char *title, int port, int ch, int is_tx) { int i; @@ -1494,7 +1838,7 @@ static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch len = skb->len; if ( len > RX_DMA_CH_AAL_BUF_SIZE ) { - printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32)skb, (u32)skb->data, skb->len); + printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (unsigned int)skb, (unsigned int)skb->data, skb->len); return; } @@ -1502,7 +1846,7 @@ static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch printk("%s (port %d, ch %d)\n", title, port, ch); else printk("%s\n", title); - printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32)skb->data, (u32)skb->tail, (int)skb->len); + printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (unsigned int)skb->data, (unsigned int)skb->tail, (int)skb->len); for ( i = 1; i <= len; i++ ) { if ( i % 16 == 1 ) printk(" %4d:", i - 1); @@ -1515,36 +1859,151 @@ static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch } #endif +#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC +static void skb_swap(struct sk_buff *skb, unsigned int byteoff) +{ + unsigned int mac_offset = ~0; + unsigned int ip_offset = ~0; + unsigned char tmp[8]; + unsigned char *p = NULL; + + skb_pull(skb, byteoff + TX_INBAND_HEADER_LENGTH); + + if ( skb->data[0] == 0xAA && skb->data[1] == 0xAA && skb->data[2] == 0x03 ) { + // LLC + if ( skb->data[3] == 0x00 && skb->data[4] == 0x80 && skb->data[5] == 0xC2 ) { + // EoA + if ( skb->data[22] == 0x08 && skb->data[23] == 0x00 ) { + // IPv4 + mac_offset = 10; + ip_offset = 24; + } + else if ( skb->data[31] == 0x21 ) { + // PPPoE IPv4 + mac_offset = 10; + ip_offset = 32; + } + } + else { + // IPoA + if ( skb->data[6] == 0x08 && skb->data[7] == 0x00 ) { + // IPv4 + ip_offset = 8; + } + } + } + else if ( skb->data[0] == 0xFE && skb->data[1] == 0xFE && skb->data[2] == 0x03 ) { + // LLC PPPoA + if ( skb->data[4] == 0x00 && skb->data[5] == 0x21 ) { + // IPv4 + ip_offset = 6; + } + } + else { + // VC-mux + if ( skb->data[0] == 0x00 && skb->data[1] == 0x21 ) { + // PPPoA IPv4 + ip_offset = 2; + } + else if ( skb->data[0] == 0x00 && skb->data[1] == 0x00 ) { + // EoA + if ( skb->data[14] == 0x08 && skb->data[15] ==0x00 ) { + // IPv4 + mac_offset = 2; + ip_offset = 16; + } + else if ( skb->data[23] == 0x21 ) { + // PPPoE IPv4 + mac_offset = 2; + ip_offset = 26; + } + } + else { + // IPoA + ip_offset = 0; + } + } + + if ( mac_offset != ~0 && !(skb->data[mac_offset] & 0x01) ) { + p = skb->data + mac_offset; + // swap MAC + memcpy(tmp, p, 6); + memcpy(p, p + 6, 6); + memcpy(p + 6, tmp, 6); + p += 12; + } + + if ( ip_offset != ~0 ) { + p = skb->data + ip_offset + 12; + // swap IP + memcpy(tmp, p, 4); + memcpy(p, p + 4, 4); + memcpy(p + 4, tmp, 4); + p += 8; + } + + if ( p != NULL ) { + dma_cache_wback((unsigned long)skb->data, (unsigned long)p - (unsigned long)skb->data); + } + + skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH); +} +#endif + static INLINE void proc_file_create(void) { -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC struct proc_dir_entry *res; -#endif g_atm_dir = proc_mkdir("driver/ifx_atm", NULL); create_proc_read_entry("version", - 0, - g_atm_dir, - proc_read_version, - NULL); + 0, + g_atm_dir, + proc_read_version, + NULL); res = create_proc_entry("mib", 0, g_atm_dir); if ( res != NULL ) { - res->read_proc = proc_read_mib; - res->write_proc = proc_write_mib; + res->read_proc = proc_read_mib; + res->write_proc = proc_write_mib; } +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + res = create_proc_entry("retx_mib", + 0, + g_atm_dir); + if ( res != NULL ) { + res->read_proc = proc_read_retx_mib; + res->write_proc = proc_write_retx_mib; + } +#endif + #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC res = create_proc_entry("dbg", 0, g_atm_dir); if ( res != NULL ) { - res->read_proc = proc_read_dbg; - res->write_proc = proc_write_dbg; + res->read_proc = proc_read_dbg; + res->write_proc = proc_write_dbg; + } + + res = create_proc_entry("mem", + 0, + g_atm_dir); + if ( res != NULL ) + res->write_proc = proc_write_mem; + + #if defined(CONFIG_AR9) || defined(CONFIG_VR9) || defined(CONFIG_DANUBE) || defined(CONFIG_AMAZON_SE) + res = create_proc_entry("pp32", + 0, + g_atm_dir); + if ( res != NULL ) { + res->read_proc = proc_read_pp32; + res->write_proc = proc_write_pp32; } + #endif #endif #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC @@ -1555,25 +2014,77 @@ static INLINE void proc_file_create(void) NULL); create_proc_read_entry("txq", + 0, + g_atm_dir, + proc_read_txq, + NULL); + + #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + create_proc_read_entry("retx_fw", + 0, + g_atm_dir, + proc_read_retx_fw, + NULL); + + res = create_proc_entry("retx_stats", + 0, + g_atm_dir); + if ( res != NULL ) { + res->read_proc = proc_read_retx_stats; + res->write_proc = proc_write_retx_stats; + } + + res = create_proc_entry("retx_cfg", + 0, + g_atm_dir); + if ( res != NULL ) { + res->read_proc = proc_read_retx_cfg; + res->write_proc = proc_write_retx_cfg; + } + + create_proc_read_entry("retx_dsl_param", 0, g_atm_dir, - proc_read_txq, + proc_read_retx_dsl_param, NULL); + #endif #endif } static INLINE void proc_file_delete(void) { #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC + #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + remove_proc_entry("retx_dsl_param", g_atm_dir); + + remove_proc_entry("retx_cfg", g_atm_dir); + + remove_proc_entry("retx_stats", g_atm_dir); + + remove_proc_entry("retx_fw", g_atm_dir); + #endif + remove_proc_entry("txq", g_atm_dir); remove_proc_entry("htu", g_atm_dir); #endif #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC + #if defined(CONFIG_AR9) || defined(CONFIG_VR9) || defined(CONFIG_DANUBE) || defined(CONFIG_AMAZON_SE) + remove_proc_entry("pp32", g_atm_dir); + #endif + + remove_proc_entry("mem", g_atm_dir); + remove_proc_entry("dbg", g_atm_dir); #endif +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + remove_proc_entry("retx_mib", g_atm_dir); +#endif + + remove_proc_entry("mib", g_atm_dir); + remove_proc_entry("version", g_atm_dir); remove_proc_entry("driver/ifx_atm", NULL); @@ -1627,7 +2138,7 @@ static int proc_read_mib(char *page, char **start, off_t off, int count, int *eo static int proc_write_mib(struct file *file, const char *buf, unsigned long count, void *data) { - char str[2048]; + char str[1024]; char *p; int len, rlen; @@ -1653,6 +2164,172 @@ static int proc_write_mib(struct file *file, const char *buf, unsigned long coun return count; } +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + +static int proc_read_retx_mib(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + int len = 0; + + printk("Retx FW DTU MIB :\n"); + printk(" rx_total_dtu = %u\n", *URETX_RX_TOTAL_DTU); + printk(" rx_bad_dtu = %u\n", *URETX_RX_BAD_DTU); + printk(" rx_good_dtu = %u\n", *URETX_RX_GOOD_DTU); + printk(" rx_corrected_dtu = %u\n", *URETX_RX_CORRECTED_DTU); + printk(" rx_outofdate_dtu = %u\n", *URETX_RX_OUTOFDATE_DTU); + printk(" rx_duplicate_dtu = %u\n", *URETX_RX_DUPLICATE_DTU); + printk(" rx_timeout_dtu = %u\n", *URETX_RX_TIMEOUT_DTU); + printk(" RxDTURetransmittedCNT = %u\n", *RxDTURetransmittedCNT); + printk("\n"); + + printk("Retx Standard DTU MIB:\n"); + printk(" RxLastEFB = %u\n", *RxLastEFBCNT); + printk(" RxDTUCorrectedCNT = %u\n", *RxDTUCorrectedCNT); + printk(" RxDTUCorruptedCNT = %u\n", *RxDTUCorruptedCNT); + printk(" RxRetxDTUUncorrectedCNT = %u\n", *RxRetxDTUUncorrectedCNT); + printk("\n"); + + printk("Retx FW Cell MIB :\n"); + printk(" bc0_total_cell = %u\n", *WRX_BC0_CELL_NUM); + printk(" bc0_drop_cell = %u\n", *WRX_BC0_DROP_CELL_NUM); + printk(" bc0_nonretx_cell = %u\n", *WRX_BC0_NONRETX_CELL_NUM); + printk(" bc0_retx_cell = %u\n", *WRX_BC0_RETX_CELL_NUM); + printk(" bc0_outofdate_cell = %u\n", *WRX_BC0_OUTOFDATE_CELL_NUM); + printk(" bc0_directup_cell = %u\n", *WRX_BC0_DIRECTUP_NUM); + printk(" bc0_to_pb_total_cell = %u\n", *WRX_BC0_PBW_TOTAL_NUM); + printk(" bc0_to_pb_succ_cell = %u\n", *WRX_BC0_PBW_SUCC_NUM); + printk(" bc0_to_pb_fail_cell = %u\n", *WRX_BC0_PBW_FAIL_NUM); + printk(" bc1_total_cell = %u\n", *WRX_BC1_CELL_NUM); + + printk("\n"); + + printk("ATM Rx AAL5/OAM MIB:\n"); + printk(" wrx_drophtu_cell = %u\n", WAN_MIB_TABLE->wrx_drophtu_cell); + printk(" wrx_dropdes_pdu = %u\n", WAN_MIB_TABLE->wrx_dropdes_pdu); + + printk(" wrx_correct_pdu = %-10u ", WAN_MIB_TABLE->wrx_correct_pdu); + if ( WAN_MIB_TABLE->wrx_correct_pdu == 0 ) + printk("\n"); + else { + int i = 0; + + printk("[ "); + for ( i = 0; i < 16; ++i ) { + if ( WRX_PER_PVC_CORRECT_PDU_BASE[i] ) + printk("q%-2d = %-10u , ", i, WRX_PER_PVC_CORRECT_PDU_BASE[i]); + } + printk("]\n"); + } + + printk(" wrx_err_pdu = %-10u ", WAN_MIB_TABLE->wrx_err_pdu); + if ( WAN_MIB_TABLE->wrx_err_pdu == 0 ) + printk("\n"); + else { + int i = 0; + + printk("[ "); + for ( i = 0; i < 16; ++i ) { + if ( WRX_PER_PVC_ERROR_PDU_BASE[i] ) + printk("q%-2d = %-10u , ", i, WRX_PER_PVC_ERROR_PDU_BASE[i] ); + } + printk("]\n"); + } + + printk(" wrx_dropdes_cell = %u\n", WAN_MIB_TABLE->wrx_dropdes_cell); + printk(" wrx_correct_cell = %u\n", WAN_MIB_TABLE->wrx_correct_cell); + printk(" wrx_err_cell = %u\n", WAN_MIB_TABLE->wrx_err_cell); + printk(" wrx_total_byte = %u\n", WAN_MIB_TABLE->wrx_total_byte); + printk("\n"); + + printk("ATM Tx MIB:\n"); + printk(" wtx_total_pdu = %u\n", WAN_MIB_TABLE->wtx_total_pdu); + printk(" wtx_total_cell = %u\n", WAN_MIB_TABLE->wtx_total_cell); + printk(" wtx_total_byte = %u\n", WAN_MIB_TABLE->wtx_total_byte); + printk("\n"); + + printk("Debugging Info:\n"); + printk(" Firmware version = %d.%d.%d.%d.%d.%d\n", + (int)FW_VER_ID->family, (int)FW_VER_ID->fwtype, (int)FW_VER_ID->interface, + (int)FW_VER_ID->fwmode, (int)FW_VER_ID->major, (int)FW_VER_ID->minor); + + printk(" retx_alpha_switch_to_hunt_times = %u\n", *URETX_ALPHA_SWITCH_TO_HUNT_TIMES); + + printk("\n"); + + *eof = 1; + + return len; +} + +static int proc_write_retx_mib(struct file *file, const char *buf, unsigned long count, void *data) +{ + char str[2048]; + char *p; + int len, rlen; + int i; + + len = count < sizeof(str) ? count : sizeof(str) - 1; + rlen = len - copy_from_user(str, buf, len); + while ( rlen && str[rlen - 1] <= ' ' ) + rlen--; + str[rlen] = 0; + for ( p = str; *p && *p <= ' '; p++, rlen-- ); + if ( !*p ) + return 0; + + if ( stricmp(p, "clean") == 0 || stricmp(p, "clear") == 0 || stricmp(p, "clear_all") == 0) { + *URETX_RX_TOTAL_DTU = 0; + *URETX_RX_BAD_DTU = 0; + *URETX_RX_GOOD_DTU = 0; + *URETX_RX_CORRECTED_DTU = 0; + *URETX_RX_OUTOFDATE_DTU = 0; + *URETX_RX_DUPLICATE_DTU = 0; + *URETX_RX_TIMEOUT_DTU = 0; + *RxDTURetransmittedCNT = 0; + + *WRX_BC0_CELL_NUM = 0; + *WRX_BC0_DROP_CELL_NUM = 0; + *WRX_BC0_NONRETX_CELL_NUM = 0; + *WRX_BC0_RETX_CELL_NUM = 0; + *WRX_BC0_OUTOFDATE_CELL_NUM = 0; + *WRX_BC0_DIRECTUP_NUM = 0; + *WRX_BC0_PBW_TOTAL_NUM = 0; + *WRX_BC0_PBW_SUCC_NUM = 0; + *WRX_BC0_PBW_FAIL_NUM = 0; + *WRX_BC1_CELL_NUM = 0; + + for ( i = 0; i < 16; ++i ) { + WRX_PER_PVC_CORRECT_PDU_BASE[i] = 0; + WRX_PER_PVC_ERROR_PDU_BASE[i] = 0; + } + + WAN_MIB_TABLE->wrx_drophtu_cell = 0; + WAN_MIB_TABLE->wrx_dropdes_pdu = 0; + WAN_MIB_TABLE->wrx_correct_pdu = 0; + WAN_MIB_TABLE->wrx_err_pdu = 0; + WAN_MIB_TABLE->wrx_dropdes_cell = 0; + WAN_MIB_TABLE->wrx_correct_cell = 0; + WAN_MIB_TABLE->wrx_err_cell = 0; + WAN_MIB_TABLE->wrx_total_byte = 0; + + WAN_MIB_TABLE->wtx_total_pdu = 0; + WAN_MIB_TABLE->wtx_total_cell = 0; + WAN_MIB_TABLE->wtx_total_byte = 0; + + *URETX_ALPHA_SWITCH_TO_HUNT_TIMES = 0; + + if (stricmp(p, "clear_all") == 0) { + *RxLastEFBCNT = 0; + *RxDTUCorrectedCNT = 0; + *RxDTUCorruptedCNT = 0; + *RxRetxDTUUncorrectedCNT = 0; + } + } + + return count; +} + +#endif + #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC static int proc_read_dbg(char *page, char **start, off_t off, int count, int *eof, void *data) @@ -1666,6 +2343,7 @@ static int proc_read_dbg(char *page, char **start, off_t off, int count, int *eo len += sprintf(page + off + len, "dump tx skb - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_TX) ? "enabled" : "disabled"); len += sprintf(page + off + len, "qos - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ? "enabled" : "disabled"); len += sprintf(page + off + len, "dump init - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_INIT) ? "enabled" : "disabled"); + len += sprintf(page + off + len, "mac swap - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ? "enabled" : "disabled"); *eof = 1; @@ -1689,6 +2367,8 @@ static int proc_write_dbg(struct file *file, const char *buf, unsigned long coun " qos", " dump init", " init", + " mac swap", + " swap", " all" }; static const int dbg_enable_mask_str_len[] = { @@ -1699,9 +2379,10 @@ static int proc_write_dbg(struct file *file, const char *buf, unsigned long coun 12, 3, 9, 4, 10, 5, + 9, 5, 4 }; - u32 dbg_enable_mask[] = { + unsigned int dbg_enable_mask[] = { DBG_ENABLE_MASK_ERR, DBG_ENABLE_MASK_DEBUG_PRINT, DBG_ENABLE_MASK_ASSERT, @@ -1709,25 +2390,34 @@ static int proc_write_dbg(struct file *file, const char *buf, unsigned long coun DBG_ENABLE_MASK_DUMP_SKB_TX, DBG_ENABLE_MASK_DUMP_QOS, DBG_ENABLE_MASK_DUMP_INIT, + DBG_ENABLE_MASK_MAC_SWAP, DBG_ENABLE_MASK_ALL }; - char str[2048]; + char *str; + int str_buff_len = 1024; char *p; int len, rlen; int f_enable = 0; int i; + + str = vmalloc(str_buff_len); + if(!str){ + return 0; + } - len = count < sizeof(str) ? count : sizeof(str) - 1; + len = count < str_buff_len ? count : str_buff_len - 1; rlen = len - copy_from_user(str, buf, len); while ( rlen && str[rlen - 1] <= ' ' ) rlen--; str[rlen] = 0; for ( p = str; *p && *p <= ' '; p++, rlen-- ); - if ( !*p ) + if ( !*p ){ + vfree(str); return 0; + } if ( strincmp(p, "enable", 6) == 0 ) { p += 6; @@ -1744,9 +2434,9 @@ static int proc_write_dbg(struct file *file, const char *buf, unsigned long coun if ( f_enable ) { if ( *p == 0 ) { if ( f_enable > 0 ) - ifx_atm_dbg_enable |= DBG_ENABLE_MASK_ALL; + ifx_atm_dbg_enable |= DBG_ENABLE_MASK_ALL & ~DBG_ENABLE_MASK_MAC_SWAP; else - ifx_atm_dbg_enable &= ~DBG_ENABLE_MASK_ALL; + ifx_atm_dbg_enable &= ~DBG_ENABLE_MASK_ALL | DBG_ENABLE_MASK_MAC_SWAP; } else { do { @@ -1763,9 +2453,730 @@ static int proc_write_dbg(struct file *file, const char *buf, unsigned long coun } } + vfree(str); + return count; +} + +static inline unsigned long sb_addr_to_fpi_addr_convert(unsigned long sb_addr) +{ + #define PP32_SB_ADDR_END 0xFFFF + + if ( sb_addr < PP32_SB_ADDR_END ) + return (unsigned long)SB_BUFFER(sb_addr); + else + return sb_addr; +} + +static int proc_write_mem(struct file *file, const char *buf, unsigned long count, void *data) +{ + char *p1, *p2; + int len; + int colon; + unsigned long *p; + int i, n, l; + int local_buf_size = 1024; + char *local_buf = NULL; + + local_buf = vmalloc(local_buf_size); + if ( !local_buf ){ + return 0; + } + + len = local_buf_size < count ? local_buf_size - 1 : count; + len = len - copy_from_user(local_buf, buf, len); + local_buf[len] = 0; + + p1 = local_buf; + colon = 1; + while ( get_token(&p1, &p2, &len, &colon) ) { + if ( stricmp(p1, "w") == 0 || stricmp(p1, "write") == 0 || stricmp(p1, "r") == 0 || stricmp(p1, "read") == 0 ) + break; + + p1 = p2; + colon = 1; + } + + if ( *p1 == 'w' ) { + ignore_space(&p2, &len); + p = (unsigned long *)get_number(&p2, &len, 1); + p = (unsigned long *)sb_addr_to_fpi_addr_convert((unsigned long)p); + + if ( (unsigned int)p >= KSEG0 ) + while ( 1 ) { + ignore_space(&p2, &len); + if ( !len || !((*p2 >= '0' && *p2 <= '9') || (*p2 >= 'a' && *p2 <= 'f') || (*p2 >= 'A' && *p2 <= 'F')) ) + break; + + *p++ = (unsigned int)get_number(&p2, &len, 1); + } + } + else if ( *p1 == 'r' ) { + ignore_space(&p2, &len); + p = (unsigned long *)get_number(&p2, &len, 1); + p = (unsigned long *)sb_addr_to_fpi_addr_convert((unsigned long)p); + + if ( (unsigned int)p >= KSEG0 ) { + ignore_space(&p2, &len); + n = (int)get_number(&p2, &len, 0); + if ( n ) { + char str[32] = {0}; + char *pch = str; + int k; + unsigned int data; + char c; + + n += (l = ((int)p >> 2) & 0x03); + p = (unsigned long *)((unsigned int)p & ~0x0F); + for ( i = 0; i < n; i++ ) { + if ( (i & 0x03) == 0 ) { + printk("%08X:", (unsigned int)p); + pch = str; + } + if ( i < l ) { + printk(" "); + sprintf(pch, " "); + } + else { + data = (unsigned int)*p; + printk(" %08X", data); + for ( k = 0; k < 4; k++ ) { + c = ((char*)&data)[k]; + pch[k] = c < ' ' ? '.' : c; + } + } + p++; + pch += 4; + if ( (i & 0x03) == 0x03 ) { + pch[0] = 0; + printk(" ; %s\n", str); + } + } + if ( (n & 0x03) != 0x00 ) { + for ( k = 4 - (n & 0x03); k > 0; k-- ) + printk(" "); + pch[0] = 0; + printk(" ; %s\n", str); + } + } + } + } + + vfree(local_buf); + return count; +} + + #if defined(CONFIG_AR9) || defined(CONFIG_VR9) + +static int proc_read_pp32(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + static const char *stron = " on"; + static const char *stroff = "off"; + + int len = 0; + int cur_context; + int f_stopped; + char str[256]; + char strlength; + int i, j; + + int pp32; + + for ( pp32 = 0; pp32 < NUM_OF_PP32; pp32++ ) { + f_stopped = 0; + + len += sprintf(page + off + len, "===== pp32 core %d =====\n", pp32); + + #ifdef CONFIG_VR9 + if ( (*PP32_FREEZE & (1 << (pp32 << 4))) != 0 ) { + sprintf(str, "freezed"); + f_stopped = 1; + } + #else + if ( 0 ) { + } + #endif + else if ( PP32_CPU_USER_STOPPED(pp32) || PP32_CPU_USER_BREAKIN_RCV(pp32) || PP32_CPU_USER_BREAKPOINT_MET(pp32) ) { + strlength = 0; + if ( PP32_CPU_USER_STOPPED(pp32) ) + strlength += sprintf(str + strlength, "stopped"); + if ( PP32_CPU_USER_BREAKPOINT_MET(pp32) ) + strlength += sprintf(str + strlength, strlength ? " | breakpoint" : "breakpoint"); + if ( PP32_CPU_USER_BREAKIN_RCV(pp32) ) + strlength += sprintf(str + strlength, strlength ? " | breakin" : "breakin"); + f_stopped = 1; + } + #if 0 + else if ( PP32_CPU_CUR_PC(pp32) == PP32_CPU_CUR_PC(pp32) ) { + sprintf(str, "hang"); + f_stopped = 1; + } + #endif + else + sprintf(str, "running"); + cur_context = PP32_BRK_CUR_CONTEXT(pp32); + len += sprintf(page + off + len, "Context: %d, PC: 0x%04x, %s\n", cur_context, PP32_CPU_CUR_PC(pp32), str); + + if ( PP32_CPU_USER_BREAKPOINT_MET(pp32) ) { + strlength = 0; + if ( PP32_BRK_PC_MET(pp32, 0) ) + strlength += sprintf(str + strlength, "pc0"); + if ( PP32_BRK_PC_MET(pp32, 1) ) + strlength += sprintf(str + strlength, strlength ? " | pc1" : "pc1"); + if ( PP32_BRK_DATA_ADDR_MET(pp32, 0) ) + strlength += sprintf(str + strlength, strlength ? " | daddr0" : "daddr0"); + if ( PP32_BRK_DATA_ADDR_MET(pp32, 1) ) + strlength += sprintf(str + strlength, strlength ? " | daddr1" : "daddr1"); + if ( PP32_BRK_DATA_VALUE_RD_MET(pp32, 0) ) { + strlength += sprintf(str + strlength, strlength ? " | rdval0" : "rdval0"); + if ( PP32_BRK_DATA_VALUE_RD_LO_EQ(pp32, 0) ) { + if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 0) ) + strlength += sprintf(str + strlength, " =="); + else + strlength += sprintf(str + strlength, " <="); + } + else if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 0) ) + strlength += sprintf(str + strlength, " >="); + } + if ( PP32_BRK_DATA_VALUE_RD_MET(pp32, 1) ) { + strlength += sprintf(str + strlength, strlength ? " | rdval1" : "rdval1"); + if ( PP32_BRK_DATA_VALUE_RD_LO_EQ(pp32, 1) ) { + if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 1) ) + strlength += sprintf(str + strlength, " =="); + else + strlength += sprintf(str + strlength, " <="); + } + else if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 1) ) + strlength += sprintf(str + strlength, " >="); + } + if ( PP32_BRK_DATA_VALUE_WR_MET(pp32, 0) ) { + strlength += sprintf(str + strlength, strlength ? " | wtval0" : "wtval0"); + if ( PP32_BRK_DATA_VALUE_WR_LO_EQ(pp32, 0) ) { + if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 0) ) + strlength += sprintf(str + strlength, " =="); + else + strlength += sprintf(str + strlength, " <="); + } + else if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 0) ) + strlength += sprintf(str + strlength, " >="); + } + if ( PP32_BRK_DATA_VALUE_WR_MET(pp32, 1) ) { + strlength += sprintf(str + strlength, strlength ? " | wtval1" : "wtval1"); + if ( PP32_BRK_DATA_VALUE_WR_LO_EQ(pp32, 1) ) { + if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 1) ) + strlength += sprintf(str + strlength, " =="); + else + strlength += sprintf(str + strlength, " <="); + } + else if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 1) ) + strlength += sprintf(str + strlength, " >="); + } + len += sprintf(page + off + len, "break reason: %s\n", str); + } + + if ( f_stopped ) + { + len += sprintf(page + off + len, "General Purpose Register (Context %d):\n", cur_context); + for ( i = 0; i < 4; i++ ) { + for ( j = 0; j < 4; j++ ) + len += sprintf(page + off + len, " %2d: %08x", i + j * 4, *PP32_GP_CONTEXTi_REGn(pp32, cur_context, i + j * 4)); + len += sprintf(page + off + len, "\n"); + } + } + + len += sprintf(page + off + len, "break out on: break in - %s, stop - %s\n", + PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(pp32) ? stron : stroff, + PP32_CTRL_OPT_BREAKOUT_ON_STOP(pp32) ? stron : stroff); + len += sprintf(page + off + len, " stop on: break in - %s, break point - %s\n", + PP32_CTRL_OPT_STOP_ON_BREAKIN(pp32) ? stron : stroff, + PP32_CTRL_OPT_STOP_ON_BREAKPOINT(pp32) ? stron : stroff); + len += sprintf(page + off + len, "breakpoint:\n"); + len += sprintf(page + off + len, " pc0: 0x%08x, %s\n", *PP32_BRK_PC(pp32, 0), PP32_BRK_GRPi_PCn(pp32, 0, 0) ? "group 0" : "off"); + len += sprintf(page + off + len, " pc1: 0x%08x, %s\n", *PP32_BRK_PC(pp32, 1), PP32_BRK_GRPi_PCn(pp32, 1, 1) ? "group 1" : "off"); + len += sprintf(page + off + len, " daddr0: 0x%08x, %s\n", *PP32_BRK_DATA_ADDR(pp32, 0), PP32_BRK_GRPi_DATA_ADDRn(pp32, 0, 0) ? "group 0" : "off"); + len += sprintf(page + off + len, " daddr1: 0x%08x, %s\n", *PP32_BRK_DATA_ADDR(pp32, 1), PP32_BRK_GRPi_DATA_ADDRn(pp32, 1, 1) ? "group 1" : "off"); + len += sprintf(page + off + len, " rdval0: 0x%08x\n", *PP32_BRK_DATA_VALUE_RD(pp32, 0)); + len += sprintf(page + off + len, " rdval1: 0x%08x\n", *PP32_BRK_DATA_VALUE_RD(pp32, 1)); + len += sprintf(page + off + len, " wrval0: 0x%08x\n", *PP32_BRK_DATA_VALUE_WR(pp32, 0)); + len += sprintf(page + off + len, " wrval1: 0x%08x\n", *PP32_BRK_DATA_VALUE_WR(pp32, 1)); + } + + *eof = 1; + + return len; +} + +static int proc_write_pp32(struct file *file, const char *buf, unsigned long count, void *data) +{ + char *str = NULL; + char *p; + unsigned int addr; + int str_buff_len = 1024; + + int len, rlen; + + int pp32 = 0; + + str = vmalloc(str_buff_len); + if (!str) { + return 0; + } + + len = count < str_buff_len ? count : str_buff_len - 1; + rlen = len - copy_from_user(str, buf, len); + while ( rlen && str[rlen - 1] <= ' ' ) + rlen--; + str[rlen] = 0; + for ( p = str; *p && *p <= ' '; p++, rlen-- ); + if ( !*p ){ + vfree(str); + return 0; + } + + if ( strincmp(p, "pp32 ", 5) == 0 ) { + p += 5; + rlen -= 5; + + while ( rlen > 0 && *p >= '0' && *p <= '9' ) { + pp32 += *p - '0'; + p++; + rlen--; + } + while ( rlen > 0 && *p && *p <= ' ' ) { + p++; + rlen--; + } + + if ( pp32 >= NUM_OF_PP32 ) { + err("incorrect pp32 index - %d", pp32); + vfree(str); + return count; + } + } + + if ( stricmp(p, "start") == 0 ) + *PP32_CTRL_CMD(pp32) = PP32_CTRL_CMD_RESTART; + else if ( stricmp(p, "stop") == 0 ) + *PP32_CTRL_CMD(pp32) = PP32_CTRL_CMD_STOP; + else if ( stricmp(p, "step") == 0 ) + *PP32_CTRL_CMD(pp32) = PP32_CTRL_CMD_STEP; + #ifdef CONFIG_VR9 + else if ( stricmp(p, "restart") == 0 ) + *PP32_FREEZE &= ~(1 << (pp32 << 4)); + else if ( stricmp(p, "freeze") == 0 ) + *PP32_FREEZE |= 1 << (pp32 << 4); + #endif + else if ( strincmp(p, "pc0 ", 4) == 0 ) { + p += 4; + rlen -= 4; + if ( stricmp(p, "off") == 0 ) { + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_OFF(0, 0); + *PP32_BRK_PC_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN; + *PP32_BRK_PC(pp32, 0) = 0; + } + else { + addr = get_number(&p, &rlen, 1); + *PP32_BRK_PC(pp32, 0) = addr; + *PP32_BRK_PC_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3); + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_ON(0, 0); + } + } + else if ( strincmp(p, "pc1 ", 4) == 0 ) { + p += 4; + rlen -= 4; + if ( stricmp(p, "off") == 0 ) { + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_OFF(1, 1); + *PP32_BRK_PC_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN; + *PP32_BRK_PC(pp32, 1) = 0; + } + else { + addr = get_number(&p, &rlen, 1); + *PP32_BRK_PC(pp32, 1) = addr; + *PP32_BRK_PC_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3); + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_ON(1, 1); + } + } + else if ( strincmp(p, "daddr0 ", 7) == 0 ) { + p += 7; + rlen -= 7; + if ( stricmp(p, "off") == 0 ) { + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_OFF(0, 0); + *PP32_BRK_DATA_ADDR_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN; + *PP32_BRK_DATA_ADDR(pp32, 0) = 0; + } + else { + addr = get_number(&p, &rlen, 1); + *PP32_BRK_DATA_ADDR(pp32, 0) = addr; + *PP32_BRK_DATA_ADDR_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3); + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_ON(0, 0); + } + } + else if ( strincmp(p, "daddr1 ", 7) == 0 ) { + p += 7; + rlen -= 7; + if ( stricmp(p, "off") == 0 ) { + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_OFF(1, 1); + *PP32_BRK_DATA_ADDR_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN; + *PP32_BRK_DATA_ADDR(pp32, 1) = 0; + } + else { + addr = get_number(&p, &rlen, 1); + *PP32_BRK_DATA_ADDR(pp32, 1) = addr; + *PP32_BRK_DATA_ADDR_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3); + *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_ON(1, 1); + } + } + else { + + printk("echo \"<command>\" > /proc/driver/ifx_ptm/pp32\n"); + printk(" command:\n"); + printk(" start - run pp32\n"); + printk(" stop - stop pp32\n"); + printk(" step - run pp32 with one step only\n"); + printk(" pc0 - pc0 <addr>/off, set break point PC0\n"); + printk(" pc1 - pc1 <addr>/off, set break point PC1\n"); + printk(" daddr0 - daddr0 <addr>/off, set break point data address 0\n"); + printk(" daddr0 - daddr1 <addr>/off, set break point data address 1\n"); + printk(" help - print this screen\n"); + } + + if ( *PP32_BRK_TRIG(pp32) ) + *PP32_CTRL_OPT(pp32) = PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON; + else + *PP32_CTRL_OPT(pp32) = PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF; + vfree(str); return count; } +#elif defined(CONFIG_DANUBE) + +static int proc_read_pp32(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + static const char *halt_stat[] = { + "reset", + "break in line", + "stop", + "step", + "code", + "data0", + "data1" + }; + static const char *brk_src_data[] = { + "off", + "read", + "write", + "read/write", + "write_equal", + "N/A", + "N/A", + "N/A" + }; + static const char *brk_src_code[] = { + "off", + "on" + }; + + int len = 0; + int i; + int k; + unsigned long bit; + int tsk; + + tsk = *PP32_DBG_TASK_NO & 0x03; + len += sprintf(page + off + len, "Task No %d, PC %04x\n", tsk, *PP32_DBG_CUR_PC & 0xFFFF); + + if ( !(*PP32_HALT_STAT & 0x01) ) + len += sprintf(page + off + len, " Halt State: Running\n"); + else { + len += sprintf(page + off + len, " Halt State: Stopped"); + k = 0; + for ( bit = 2, i = 0; bit <= (1 << 7); bit <<= 1, i++ ) + if ( (*PP32_HALT_STAT & bit) ) { + if ( !k ) { + len += sprintf(page + off + len, ", "); + k++; + } + else + len += sprintf(page + off + len, " | "); + len += sprintf(page + off + len, halt_stat[i]); + } + + len += sprintf(page + off + len, "\n"); + + len += sprintf(page + off + len, " Regs (Task %d):\n", tsk); + for ( i = 0; i < 8; i++ ) + len += sprintf(page + off + len, " %2d. %08x %2d. %08x\n", i, *PP32_DBG_REG_BASE(tsk, i), i + 8, *PP32_DBG_REG_BASE(tsk, i + 8)); + } + + len += sprintf(page + off + len, " Break Src: data1 - %s, data0 - %s, pc3 - %s, pc2 - %s, pc1 - %s, pc0 - %s\n", + brk_src_data[(*PP32_BRK_SRC >> 11) & 0x07], + brk_src_data[(*PP32_BRK_SRC >> 8) & 0x07], + brk_src_code[(*PP32_BRK_SRC >> 3) & 0x01], + brk_src_code[(*PP32_BRK_SRC >> 2) & 0x01], + brk_src_code[(*PP32_BRK_SRC >> 1) & 0x01], + brk_src_code[*PP32_BRK_SRC & 0x01]); + + for ( i = 0; i < 4; i++ ) + len += sprintf(page + off + len, " pc%d: %04x - %04x\n", i, *PP32_DBG_PC_MIN(i), *PP32_DBG_PC_MAX(i)); + + for ( i = 0; i < 2; i++ ) + len += sprintf(page + off + len, " data%d: %04x - %04x (%08x)\n", i, *PP32_DBG_DATA_MIN(i), *PP32_DBG_DATA_MAX(i), *PP32_DBG_DATA_VAL(i)); + + *eof = 1; + + return len; +} + +static int proc_write_pp32(struct file *file, const char *buf, unsigned long count, void *data) +{ + char *str; + char *p; + + int len, rlen; + int str_buff_len = 2048; + str = vmalloc(str_buff_len); + if (!str){ + return 0; + } + len = count < str_buff_len ? count : str_buff_len - 1; + rlen = len - copy_from_user(str, buf, len); + while ( rlen && str[rlen - 1] <= ' ' ) + rlen--; + str[rlen] = 0; + for ( p = str; *p && *p <= ' '; p++, rlen-- ); + if ( !*p ) + vfree(str); + return 0; + + if ( stricmp(p, "start") == 0 ) + *PP32_DBG_CTRL = DBG_CTRL_START_SET(1); + else if ( stricmp(p, "stop") == 0 ) + *PP32_DBG_CTRL = DBG_CTRL_STOP_SET(1); + else if ( stricmp(p, "step") == 0 ) + *PP32_DBG_CTRL = DBG_CTRL_STEP_SET(1); + else if ( strincmp(p, "pc", 2) == 0 && p[2] >= '0' && p[2] <= '3' && p[3] <= ' ' ) { + int n = p[2] - '0'; + int on_off_flag = -1; + int addr_min, addr_max; + + p += 4; + rlen -= 4; + ignore_space(&p, &rlen); + + if ( strincmp(p, "off", 3) == 0 && p[3] <= ' ' ) { + p += 3; + rlen -= 3; + on_off_flag = 0; + } + else if ( strincmp(p, "on", 2) == 0 && p[2] <= ' ' ) { + p += 2; + rlen -= 2; + on_off_flag = 1; + } + ignore_space(&p, &rlen); + + if ( rlen ) { + addr_min = get_number(&p, &rlen, 1); + ignore_space(&p, &rlen); + if ( rlen ) + addr_max = get_number(&p, &rlen, 1); + else + addr_max = addr_min; + + *PP32_DBG_PC_MIN(n) = addr_min; + *PP32_DBG_PC_MAX(n) = addr_max; + } + + if ( on_off_flag == 0 ) + *PP32_BRK_SRC &= ~(1 << n); + else if ( on_off_flag > 0 ) + *PP32_BRK_SRC |= 1 << n; + } + else if ( strincmp(p, "data", 4) == 0 && p[4] >= '0' && p[4] <= '1' && p[5] <= ' ' ) { + const static char *data_cmd_str[] = {"r", "w", "rw", "w=", "off", "min", "min addr", "max", "max addr", "val", "value"}; + const static int data_cmd_len[] = {1, 1, 2, 2, 3, 3, 8, 3, 8, 3, 5}; + const static int data_cmd_idx[] = {1, 2, 3, 4, 0, 5, 5, 6, 6, 7, 7}; + int n = p[4] - '0'; + int on_off_flag = -1, on_off_mask = 0; + int addr_min = -1, addr_max = -1; + int value = 0, f_got_value = 0; + int stat = 0; + int i; + int tmp; + + p += 6; + rlen -= 6; + + while ( 1 ) { + ignore_space(&p, &rlen); + if ( rlen <= 0 ) + break; + for ( i = 0; i < NUM_ENTITY(data_cmd_str); i++ ) + if ( strincmp(p, data_cmd_str[i], data_cmd_len[i]) == 0 && p[data_cmd_len[i]] <= ' ' ) { + p += data_cmd_len[i]; + rlen -= data_cmd_len[i]; + stat = data_cmd_idx[i]; + if ( stat <= 4 ) { + on_off_mask = 7; + on_off_flag = stat; + } + break; + } + if ( i == NUM_ENTITY(data_cmd_str) ) { + if ( (*p >= '0' && *p <= '9') || (*p >= 'a' && *p <= 'f') || (*p >= 'A' && *p <= 'F') ) { + tmp = get_number(&p, &rlen, 1); + if ( stat <= 5 ) { + addr_min = tmp; + stat = 6; + } + else if ( stat >= 7 ) { + value = tmp; + f_got_value = 1; + } + else { + addr_max = tmp; + stat = 7; + } + } + else + for ( ; rlen && *p > ' '; rlen--, p++ ); + } + } + + if ( addr_min >= 0 ) + *PP32_DBG_DATA_MIN(n) = *PP32_DBG_DATA_MAX(n) = addr_min; + if ( addr_max >= 0 ) + *PP32_DBG_DATA_MAX(n) = addr_max; + if ( f_got_value ) + *PP32_DBG_DATA_VAL(n) = value; + if ( on_off_mask && on_off_flag >= 0 ) { + on_off_flag <<= n ? 11 : 8; + on_off_mask <<= n ? 11 : 8; + *PP32_BRK_SRC = (*PP32_BRK_SRC & ~on_off_mask) | on_off_flag; + } + } + else { + printk("echo \"<command>\" > /proc/eth/etop\n"); + printk(" command:\n"); + printk(" start - run pp32\n"); + printk(" stop - stop pp32\n"); + printk(" step - run pp32 with one step only\n"); + printk(" pc - pc? [on/off] [min addr] [max addr], set PC break point\n"); + printk(" data - data? [r/w/rw/w=/off] [min <addr>] [max <addr>] [val <value>], set data break point\n"); + printk(" help - print this screen\n"); + } + + vfree(str); + return count; +} + + #elif defined(CONFIG_AMAZON_SE) + +static int proc_read_pp32(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + static const char *halt_stat[] = { + "reset", + "break in line", + "stop", + "step", + "code", + "data0", + "data1" + }; + static const char *brk_src_data[] = { + "off", + "read", + "write", + "read/write", + "write_equal", + "N/A", + "N/A", + "N/A" + }; + static const char *brk_src_code[] = { + "off", + "on" + }; + + int len = 0; + int i; + int k; + unsigned long bit; + + len += sprintf(page + off + len, "Task No %d, PC %04x\n", *PP32_DBG_TASK_NO & 0x03, *PP32_DBG_CUR_PC & 0xFFFF); + + if ( !(*PP32_HALT_STAT & 0x01) ) + len += sprintf(page + off + len, " Halt State: Running\n"); + else + { + len += sprintf(page + off + len, " Halt State: Stopped"); + k = 0; + for ( bit = 2, i = 0; bit <= (1 << 7); bit <<= 1, i++ ) + if ( (*PP32_HALT_STAT & bit) ) + { + if ( !k ) + { + len += sprintf(page + off + len, ", "); + k++; + } + else + len += sprintf(page + off + len, " | "); + len += sprintf(page + off + len, halt_stat[i]); + } + + len += sprintf(page + off + len, "\n"); + } + + len += sprintf(page + off + len, " Break Src: data1 - %s, data0 - %s, pc3 - %s, pc2 - %s, pc1 - %s, pc0 - %s\n", + brk_src_data[(*PP32_BRK_SRC >> 11) & 0x07], brk_src_data[(*PP32_BRK_SRC >> 8) & 0x07], brk_src_code[(*PP32_BRK_SRC >> 3) & 0x01], brk_src_code[(*PP32_BRK_SRC >> 2) & 0x01], brk_src_code[(*PP32_BRK_SRC >> 1) & 0x01], brk_src_code[*PP32_BRK_SRC & 0x01]); + +// for ( i = 0; i < 4; i++ ) +// len += sprintf(page + off + len, " pc%d: %04x - %04x\n", i, *PP32_DBG_PC_MIN(i), *PP32_DBG_PC_MAX(i)); + +// for ( i = 0; i < 2; i++ ) +// len += sprintf(page + off + len, " data%d: %04x - %04x (%08x)\n", i, *PP32_DBG_DATA_MIN(i), *PP32_DBG_DATA_MAX(i), *PP32_DBG_DATA_VAL(i)); + + *eof = 1; + + return len; +} + +static int proc_write_pp32(struct file *file, const char *buf, unsigned long count, void *data) +{ + char str[2048]; + char *p; + + int len, rlen; + + len = count < sizeof(str) ? count : sizeof(str) - 1; + rlen = len - copy_from_user(str, buf, len); + while ( rlen && str[rlen - 1] <= ' ' ) + rlen--; + str[rlen] = 0; + for ( p = str; *p && *p <= ' '; p++, rlen-- ); + if ( !*p ) + return 0; + + if ( stricmp(str, "start") == 0 ) + *PP32_DBG_CTRL = DBG_CTRL_RESTART; + else if ( stricmp(str, "stop") == 0 ) + *PP32_DBG_CTRL = DBG_CTRL_STOP; +// else if ( stricmp(str, "step") == 0 ) +// *PP32_DBG_CTRL = DBG_CTRL_STEP_SET(1); + else + { + printk("echo \"<command>\" > /proc/eth/etop\n"); + printk(" command:\n"); + printk(" start - run pp32\n"); + printk(" stop - stop pp32\n"); +// printk(" step - run pp32 with one step only\n"); + printk(" help - print this screen\n"); + } + + return count; +} + + #endif + #endif #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC @@ -1776,9 +3187,9 @@ static INLINE int print_htu(char *buf, int i) if ( HTU_ENTRY(i)->vld ) { len += sprintf(buf + len, "%2d. valid\n", i); - len += sprintf(buf + len, " entry 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_ENTRY(i), HTU_ENTRY(i)->pid, HTU_ENTRY(i)->vpi, HTU_ENTRY(i)->vci, HTU_ENTRY(i)->pti); - len += sprintf(buf + len, " mask 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_MASK(i), HTU_MASK(i)->pid_mask, HTU_MASK(i)->vpi_mask, HTU_MASK(i)->vci_mask, HTU_MASK(i)->pti_mask); - len += sprintf(buf + len, " result 0x%08x - type: %s, qid: %d", *(u32*)HTU_RESULT(i), HTU_RESULT(i)->type ? "cell" : "AAL5", HTU_RESULT(i)->qid); + len += sprintf(buf + len, " entry 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(unsigned int*)HTU_ENTRY(i), HTU_ENTRY(i)->pid, HTU_ENTRY(i)->vpi, HTU_ENTRY(i)->vci, HTU_ENTRY(i)->pti); + len += sprintf(buf + len, " mask 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(unsigned int*)HTU_MASK(i), HTU_MASK(i)->pid_mask, HTU_MASK(i)->vpi_mask, HTU_MASK(i)->vci_mask, HTU_MASK(i)->pti_mask); + len += sprintf(buf + len, " result 0x%08x - type: %s, qid: %d", *(unsigned int*)HTU_RESULT(i), HTU_RESULT(i)->type ? "cell" : "AAL5", HTU_RESULT(i)->qid); if ( HTU_RESULT(i)->type ) len += sprintf(buf + len, ", cell id: %d, verification: %s", HTU_RESULT(i)->cellid, HTU_RESULT(i)->ven ? "on" : "off"); len += sprintf(buf + len, "\n"); @@ -1794,11 +3205,14 @@ static int proc_read_htu(char *page, char **start, off_t off, int count, int *eo int len = 0; int len_max = off + count; char *pstr; - char str[1024]; int llen; - + char *str; int htuts = *CFG_WRX_HTUTS; int i; + + str = vmalloc (1024); + if (!str) + return 0; pstr = *start = page; @@ -1822,7 +3236,7 @@ static int proc_read_htu(char *page, char **start, off_t off, int count, int *eo } *eof = 1; - + vfree(str); return len - off; PROC_READ_HTU_OVERRUN_END: @@ -1836,8 +3250,8 @@ static INLINE int print_tx_queue(char *buf, int i) if ( (*WTX_DMACH_ON & (1 << i)) ) { len += sprintf(buf + len, "%2d. valid\n", i); - len += sprintf(buf + len, " queue 0x%08x - sbid %u, qsb %s\n", *(u32*)WTX_QUEUE_CONFIG(i), (unsigned int)WTX_QUEUE_CONFIG(i)->sbid, WTX_QUEUE_CONFIG(i)->qsben ? "enable" : "disable"); - len += sprintf(buf + len, " dma 0x%08x - base %08x, len %u, vlddes %u\n", *(u32*)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes); + len += sprintf(buf + len, " queue 0x%08x - sbid %u, qsb vcid %u, qsb %s\n", (unsigned int)WTX_QUEUE_CONFIG(i), (unsigned int)WTX_QUEUE_CONFIG(i)->sbid, (unsigned int)WTX_QUEUE_CONFIG(i)->qsb_vcid, WTX_QUEUE_CONFIG(i)->qsben ? "enable" : "disable"); + len += sprintf(buf + len, " dma 0x%08x - base %08x, len %u, vlddes %u\n", (unsigned int)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes); } else len += sprintf(buf + len, "%2d. invalid\n", i); @@ -1850,11 +3264,16 @@ static int proc_read_txq(char *page, char **start, off_t off, int count, int *eo int len = 0; int len_max = off + count; char *pstr; - char str[1024]; int llen; + int str_buff_len = 1024; + char *str; int i; - + + str = vmalloc(str_buff_len); + if (!str){ + return 0; + } pstr = *start = page; llen = sprintf(pstr, "TX Queue Config (Max %d):\n", *CFG_WTX_DCHNUM); @@ -1876,8 +3295,10 @@ static int proc_read_txq(char *page, char **start, off_t off, int count, int *eo goto PROC_READ_HTU_OVERRUN_END; } + *eof = 1; + vfree(str); return len - off; PROC_READ_HTU_OVERRUN_END: @@ -1885,14 +3306,716 @@ PROC_READ_HTU_OVERRUN_END: return len - llen - off; } + #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + +static int proc_read_retx_fw(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + int len = 0; + + unsigned int next_dtu_sid_out, last_dtu_sid_in, next_cell_sid_out, isr_cell_id; + unsigned int curr_time, sec_counter, curr_efb; + struct Retx_adsl_ppe_intf adsl_ppe_intf; + + adsl_ppe_intf = *RETX_ADSL_PPE_INTF; + next_dtu_sid_out = *NEXT_DTU_SID_OUT; + last_dtu_sid_in = *LAST_DTU_SID_IN; + next_cell_sid_out = *NEXT_CELL_SID_OUT; + isr_cell_id = *ISR_CELL_ID; + + curr_time = *URetx_curr_time; + sec_counter = *URetx_sec_counter; + curr_efb = *RxCURR_EFB; + + + len += sprintf(page + off + len, "Adsl-PPE Interface:\n"); + len += sprintf(page + off + len, " dtu_sid = 0x%02x [%3u]\n", adsl_ppe_intf.dtu_sid, adsl_ppe_intf.dtu_sid); + len += sprintf(page + off + len, " dtu_timestamp = 0x%02x\n", adsl_ppe_intf.dtu_timestamp); + len += sprintf(page + off + len, " local_time = 0x%02x\n", adsl_ppe_intf.local_time); + len += sprintf(page + off + len, " is_last_cw = %u\n", adsl_ppe_intf.is_last_cw); + len += sprintf(page + off + len, " reinit_flag = %u\n", adsl_ppe_intf.reinit_flag); + len += sprintf(page + off + len, " is_bad_cw = %u\n", adsl_ppe_intf.is_bad_cw); + len += sprintf(page + off + len, "\n"); + + + len += sprintf(page + off + len, "Retx Firmware Context:\n"); + len += sprintf(page + off + len, " next_dtu_sid_out (0x%08x) = 0x%02x [%3u]\n", (unsigned int )NEXT_DTU_SID_OUT, next_dtu_sid_out, next_dtu_sid_out); + len += sprintf(page + off + len, " last_dtu_sid_in (0x%08x) = 0x%02x [%3u]\n", (unsigned int )LAST_DTU_SID_IN, last_dtu_sid_in, last_dtu_sid_in); + len += sprintf(page + off + len, " next_cell_sid_out (0x%08x) = %u\n", (unsigned int )NEXT_CELL_SID_OUT, next_cell_sid_out); + len += sprintf(page + off + len, " isr_cell_id (0x%08x) = %u\n", (unsigned int )ISR_CELL_ID, isr_cell_id); + len += sprintf(page + off + len, " pb_cell_search_idx (0x%08x) = %u\n", (unsigned int )PB_CELL_SEARCH_IDX, *PB_CELL_SEARCH_IDX); + len += sprintf(page + off + len, " pb_read_pend_flag (0x%08x) = %u\n", (unsigned int )PB_READ_PEND_FLAG, *PB_READ_PEND_FLAG); + len += sprintf(page + off + len, " rfbi_first_cw (0x%08x) = %u\n", (unsigned int )RFBI_FIRST_CW, *RFBI_FIRST_CW); + len += sprintf(page + off + len, " rfbi_bad_cw (0x%08x) = %u\n", (unsigned int )RFBI_BAD_CW, *RFBI_BAD_CW); + len += sprintf(page + off + len, " rfbi_invalid_cw (0x%08x) = %u\n", (unsigned int )RFBI_INVALID_CW, *RFBI_INVALID_CW); + len += sprintf(page + off + len, " rfbi_retx_cw (0x%08x) = %u\n", (unsigned int )RFBI_RETX_CW, *RFBI_RETX_CW); + len += sprintf(page + off + len, " rfbi_chk_dtu_status (0x%08x) = %u\n", (unsigned int )RFBI_CHK_DTU_STATUS,*RFBI_CHK_DTU_STATUS); + len += sprintf(page + off + len, "\n"); + + + len += sprintf(page + off + len, "SFSM Status: bc0 bc1 \n\n"); + len += sprintf(page + off + len, " state = %-22s , %s\n", + (*__WRXCTXT_PortState(0) & 3) == 0 ? "Hunt" : + (*__WRXCTXT_PortState(0) & 3) == 1 ? "Pre_sync" : + (*__WRXCTXT_PortState(0) & 3) == 2 ? "Sync" : + "Unknown(error)", + (*__WRXCTXT_PortState(1) & 3) == 0 ? "Hunt" : + (*__WRXCTXT_PortState(1) & 3) == 1 ? "Pre_sync" : + (*__WRXCTXT_PortState(1) & 3) == 2 ? "Sync" : + "Unknown(error)" ); + len += sprintf(page + off + len, " dbase = 0x%04x ( 0x%08x ) , 0x%04x ( 0x%08x )\n", + SFSM_DBA(0)->dbase, (unsigned int)PPM_INT_UNIT_ADDR(SFSM_DBA(0)->dbase + 0x2000), + SFSM_DBA(1)->dbase, (unsigned int)PPM_INT_UNIT_ADDR(SFSM_DBA(1)->dbase + 0x2000)); + len += sprintf(page + off + len, " cbase = 0x%04x ( 0x%08x ) , 0x%04x ( 0x%08x )\n", + SFSM_CBA(0)->cbase, (unsigned int)PPM_INT_UNIT_ADDR(SFSM_CBA(0)->cbase + 0x2000), + SFSM_CBA(1)->cbase, (unsigned int)PPM_INT_UNIT_ADDR(SFSM_CBA(1)->cbase + 0x2000)); + len += sprintf(page + off + len, " sen = %-22d , %d\n", SFSM_CFG(0)->sen, SFSM_CFG(1)->sen ); + len += sprintf(page + off + len, " idlekeep = %-22d , %d\n", SFSM_CFG(0)->idlekeep, SFSM_CFG(1)->idlekeep ); + len += sprintf(page + off + len, " pnum = %-22d , %d\n", SFSM_CFG(0)->pnum, SFSM_CFG(1)->pnum ); + len += sprintf(page + off + len, " pptr = %-22d , %d\n", SFSM_PGCNT(0)->pptr, SFSM_PGCNT(1)->pptr); + len += sprintf(page + off + len, " upage = %-22d , %d\n", SFSM_PGCNT(0)->upage, SFSM_PGCNT(1)->upage); + len += sprintf(page + off + len, " l2_rdptr = %-22d , %d\n", *__WRXCTXT_L2_RdPtr(0), *__WRXCTXT_L2_RdPtr(1) ); + len += sprintf(page + off + len, " l2_page = %-22d , %d\n", *__WRXCTXT_L2Pages(0), *__WRXCTXT_L2Pages(1) ); + len += sprintf(page + off + len, "\n"); + + + len += sprintf(page + off + len, "FFSM Status: bc0 bc1 \n\n"); + len += sprintf(page + off + len, " dbase = 0x%04x ( 0x%08x ) , 0x%04x ( 0x%08x )\n", + FFSM_DBA(0)->dbase, (unsigned int)PPM_INT_UNIT_ADDR(FFSM_DBA(0)->dbase + 0x2000), + FFSM_DBA(1)->dbase, (unsigned int)PPM_INT_UNIT_ADDR(FFSM_DBA(1)->dbase + 0x2000)); + len += sprintf(page + off + len, " pnum = %-22d , %d\n", FFSM_CFG(0)->pnum, FFSM_CFG(1)->pnum); + len += sprintf(page + off + len, " vpage = %-22d , %d\n", FFSM_PGCNT(0)->vpage, FFSM_PGCNT(1)->vpage); + len += sprintf(page + off + len, " ival = %-22d , %d\n", FFSM_PGCNT(0)->ival, FFSM_PGCNT(1)->ival); + len += sprintf(page + off + len, " tc_wrptr = %-22d , %d\n", *__WTXCTXT_TC_WRPTR(0), *__WTXCTXT_TC_WRPTR(1)); + len += sprintf(page + off + len, "\n"); + + + len += sprintf(page + off + len, "Misc: \n\n"); + len += sprintf(page + off + len, " curr_time = %08x\n", curr_time ); + len += sprintf(page + off + len, " sec_counter = %d\n", sec_counter ); + len += sprintf(page + off + len, " curr_efb = %d\n", curr_efb ); + len += sprintf(page + off + len, "\n"); + + *eof = 1; + + return len; +} + +static inline int is_valid(unsigned int * dtu_vld_stat, int dtu_sid) +{ + int dw_idx = (dtu_sid / 32) & 7; + int bit_pos = dtu_sid % 32; + + return dtu_vld_stat[dw_idx] & (0x80000000 >> bit_pos); +} + +static int proc_read_retx_stats(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + int i; + int len = 0; + int len_max = off + count; + char *pstr; + char str[2048]; + int llen = 0; + + unsigned int next_dtu_sid_out, last_dtu_sid_in, next_cell_sid_out; + unsigned int dtu_vld_stat[8]; + struct DTU_stat_info dtu_stat_info[256]; + struct Retx_adsl_ppe_intf adsl_ppe_intf; + + pstr = *start = page; + + __sync(); + + // capture a snapshot of internal status + next_dtu_sid_out = *NEXT_DTU_SID_OUT; + last_dtu_sid_in = *LAST_DTU_SID_IN; + next_cell_sid_out = *NEXT_CELL_SID_OUT; + adsl_ppe_intf = *RETX_ADSL_PPE_INTF; + + memcpy(&dtu_vld_stat, (void *)DTU_VLD_STAT, sizeof(dtu_vld_stat)); + memcpy(&dtu_stat_info, (void *)DTU_STAT_INFO, sizeof(dtu_stat_info)); + + + llen += sprintf(str + llen, "Adsl-PPE Interface:\n"); + llen += sprintf(str + llen, " dtu_sid = 0x%02x [%3u]\n", adsl_ppe_intf.dtu_sid, adsl_ppe_intf.dtu_sid); + llen += sprintf(str + llen, " dtu_timestamp = 0x%02x\n", adsl_ppe_intf.dtu_timestamp); + llen += sprintf(str + llen, " local_time = 0x%02x\n", adsl_ppe_intf.local_time); + llen += sprintf(str + llen, " is_last_cw = %u\n", adsl_ppe_intf.is_last_cw); + llen += sprintf(str + llen, " reinit_flag = %u\n", adsl_ppe_intf.reinit_flag); + llen += sprintf(str + llen, " is_bad_cw = %u\n", adsl_ppe_intf.is_bad_cw); + llen += sprintf(str + llen, "\n"); + + llen += sprintf(str + llen, "Retx Internal State:\n"); + llen += sprintf(str + llen, " next_dtu_sid_out (0x%08x) = 0x%02x [%3u]\n", (unsigned int )NEXT_DTU_SID_OUT, next_dtu_sid_out, next_dtu_sid_out); + llen += sprintf(str + llen, " last_dtu_sid_in (0x%08x) = 0x%02x [%3u]\n", (unsigned int )LAST_DTU_SID_IN, last_dtu_sid_in, last_dtu_sid_in); + llen += sprintf(str + llen, " next_cell_sid_out (0x%08x) = %u\n", (unsigned int )NEXT_CELL_SID_OUT, next_cell_sid_out); + llen += sprintf(str + llen, " dtu_valid_stat (0x%08x)\n", (unsigned int )DTU_VLD_STAT); + llen += sprintf(str + llen, " dtu_stat_info (0x%08x)\n", (unsigned int )DTU_STAT_INFO); + llen += sprintf(str + llen, " pb_buffer_usage (0x%08x)\n", (unsigned int )PB_BUFFER_USAGE); + + if ( len <= off && len + llen > off ) { + memcpy(pstr, str + off - len, len + llen - off); + pstr += len + llen - off; + } + else if ( len > off ) { + memcpy(pstr, str, llen); + pstr += llen; + } + len += llen; + if ( len >= len_max ) + goto PROC_READ_RETX_STATS_OVERRUN_END; + llen = 0; + + + llen += sprintf(str + llen, "\n"); + llen += sprintf(str + llen, "DTU_VALID_STAT: [0x%08x]:\n", (unsigned int)DTU_VLD_STAT); + llen += sprintf(str + llen, "%08X: %08X %08X %08X %08X %08X %08X %08X %08X\n", + (unsigned int)DTU_VLD_STAT, + dtu_vld_stat[0], dtu_vld_stat[1], dtu_vld_stat[2], dtu_vld_stat[3], + dtu_vld_stat[4], dtu_vld_stat[5], dtu_vld_stat[6], dtu_vld_stat[7]); + + if ( len <= off && len + llen > off ) { + memcpy(pstr, str + off - len, len + llen - off); + pstr += len + llen - off; + } + else if ( len > off ) { + memcpy(pstr, str, llen); + pstr += llen; + } + len += llen; + if ( len >= len_max ) + goto PROC_READ_RETX_STATS_OVERRUN_END; + llen = 0; + + + llen += sprintf(str + llen, "\n"); + llen += sprintf(str + llen, "DTU_STAT_INFO: [0x%08x]:\n", (unsigned int)DTU_STAT_INFO); + llen += sprintf(str + llen, "dtu_id ts complete bad cell_cnt dtu_rd_ptr dtu_wr_ptr\n"); + llen += sprintf(str + llen, "---------------------------------------------------------------------\n"); + for ( i = 0; i < 256; i++ ) { + if ( !is_valid(dtu_vld_stat, i) ) + continue; + + llen += sprintf(str + llen, "0x%02x [%3u] 0x%02x %d %d %3d %5d %5d\n", + i, i, + DTU_STAT_INFO[i].time_stamp, + DTU_STAT_INFO[i].complete, + DTU_STAT_INFO[i].bad, + DTU_STAT_INFO[i].cell_cnt, + DTU_STAT_INFO[i].dtu_rd_ptr, + DTU_STAT_INFO[i].dtu_wr_ptr ); + + if ( len <= off && len + llen > off ) { + memcpy(pstr, str + off - len, len + llen - off); + pstr += len + llen - off; + } + else if ( len > off ) + { + memcpy(pstr, str, llen); + pstr += llen; + } + len += llen; + if ( len >= len_max ) + goto PROC_READ_RETX_STATS_OVERRUN_END; + llen = 0; + } + + + llen += sprintf(str + llen, "\n"); + llen += sprintf(str + llen, "Playout buffer status --- valid status [0x%08x]:\n", (unsigned int)PB_BUFFER_USAGE); + for( i = 0; i < RETX_MODE_CFG->buff_size; i += 8 ) { + llen += sprintf(str + llen, "%08X: %08X %08X %08X %08X %08X %08X %08X %08X\n", + (unsigned int)PB_BUFFER_USAGE + i * sizeof(unsigned int), + PB_BUFFER_USAGE[i], PB_BUFFER_USAGE[i+1], PB_BUFFER_USAGE[i+2], PB_BUFFER_USAGE[i+3], + PB_BUFFER_USAGE[i+4], PB_BUFFER_USAGE[i+5], PB_BUFFER_USAGE[i+6], PB_BUFFER_USAGE[i+7]); + } + + if ( len <= off && len + llen > off ) { + memcpy(pstr, str + off - len, len + llen - off); + pstr += len + llen - off; + } + else if ( len > off ) { + memcpy(pstr, str, llen); + pstr += llen; + } + len += llen; + if ( len >= len_max ) + goto PROC_READ_RETX_STATS_OVERRUN_END; + llen = 0; + + + *eof = 1; + + return len - off; + +PROC_READ_RETX_STATS_OVERRUN_END: + return len - llen - off; +} + +static int proc_write_retx_stats(struct file *file, const char *buf, unsigned long count, void *data) +{ + char str[2048]; + char *p; + + int len, rlen; + + len = count < sizeof(str) ? count : sizeof(str) - 1; + rlen = len - copy_from_user(str, buf, len); + while ( rlen && str[rlen - 1] <= ' ' ) + rlen--; + str[rlen] = 0; + for ( p = str; *p && *p <= ' '; p++, rlen-- ); + if ( !*p ) + return 0; + + if ( stricmp(p, "help") == 0 ) { + printk("echo clear_pb > /proc/driver/ifx_atm/retx_stats \n"); + printk(" :clear context in playout buffer\n\n"); + printk("echo read_pb <pb_index> <cell_num> > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : read playout buffer contents\n\n"); + printk("echo read_[r|t]x_cb > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : read cell buffer\n\n"); + printk("echo clear_[r|t]x_cb > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : clear cell buffer\n\n"); + printk("echo read_bad_dtu_intf_rec > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : read bad dtu intrface information record\n\n"); + printk("echo clear_bad_dtu_intf_rec > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : clear bad dtu interface information record\n\n"); + printk("echo read_wrx_context [i] > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : clear bad dtu interface information record\n\n"); + printk("echo read_intf_rec > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : read interface info record buffer\n\n"); + printk("echo reinit_intf_rec > /proc/driver/ifx_atm/retx_stats\n"); + printk(" : reinit intf record, must be called before showtime\n\n"); + } + else if ( stricmp(p, "reinit_intf_rec") == 0 ) { + int i = 0; + struct Retx_adsl_ppe_intf_rec rec[16]; + + *DBG_DTU_INTF_WRPTR = 0; + *DBG_INTF_FCW_DUP_CNT = 0; + *DBG_INTF_SID_CHANGE_IN_DTU_CNT = 0; + *DBG_INTF_LCW_DUP_CNT = 0; + + *DBG_RFBI_DONE_INT_CNT = 0; + *DBG_RFBI_INTV0 = 0; + *DBG_RFBI_INTV1 = 0; + *DBG_RFBI_BC0_INVALID_CNT = 0; + *DBG_RFBI_LAST_T = 0; + *DBG_DREG_BEG_END = 0; + + memset((void *) DBG_INTF_INFO(0), 0, sizeof(rec)); + for( i = 0; i < 16; i++ ) + DBG_INTF_INFO(i)->res1_1 = 1; + DBG_INTF_INFO(15)->dtu_sid = 255; + } + else if ( stricmp(p, "read_intf_rec") == 0 ) { + int i, cnt; + unsigned int dtu_intf_wrptr, fcw_dup_cnt, sid_change_in_dtu_cnt, lcw_dup_cnt ; + unsigned int rfbi_done_int_cnt, rfbi_intv0, rfbi_intv1, rfbi_bc0_invalid_cnt, dreg_beg_end; + struct Retx_adsl_ppe_intf_rec rec[16]; + + memcpy((void *) rec, (void *) DBG_INTF_INFO(0), sizeof(rec)); + + dtu_intf_wrptr = *DBG_DTU_INTF_WRPTR; + fcw_dup_cnt = *DBG_INTF_FCW_DUP_CNT; + sid_change_in_dtu_cnt = *DBG_INTF_SID_CHANGE_IN_DTU_CNT; + lcw_dup_cnt = *DBG_INTF_LCW_DUP_CNT; + + rfbi_done_int_cnt = *DBG_RFBI_DONE_INT_CNT; + rfbi_intv0 = *DBG_RFBI_INTV0; + rfbi_intv1 = *DBG_RFBI_INTV1; + rfbi_bc0_invalid_cnt = *DBG_RFBI_BC0_INVALID_CNT; + dreg_beg_end = *DBG_DREG_BEG_END; + + printk("PPE-Adsl Interface recrod [addr 0x23F0]:\n\n"); + + printk(" rfbi_done_int_cnt = %d [0x%x] \n", rfbi_done_int_cnt, rfbi_done_int_cnt); + printk(" rfbi_intv = 0x%08x 0x%08x [%d, %d, %d, %d, %d, %d, %d, %d]\n", + rfbi_intv0, rfbi_intv1, + rfbi_intv0 >> 24, (rfbi_intv0>>16) & 0xff, (rfbi_intv0>>8) & 0xff, rfbi_intv0 & 0xff, + rfbi_intv1 >> 24, (rfbi_intv1>>16) & 0xff, (rfbi_intv1>>8) & 0xff, rfbi_intv1 & 0xff + ); + printk(" rfbi_bc0_invld_cnt = %d\n", rfbi_bc0_invalid_cnt); + printk(" dreg_beg_end = %d, %d\n\n", dreg_beg_end >> 16, dreg_beg_end & 0xffff); + + printk(" wrptr = %d [0x%x] \n", dtu_intf_wrptr, dtu_intf_wrptr); + printk(" fcw_dup_cnt = %d\n", fcw_dup_cnt); + printk(" sid_chg_cnt = %d\n", sid_change_in_dtu_cnt); + printk(" lcw_dup_cnt = %d\n\n", lcw_dup_cnt); + + + printk(" idx itf_dw0 itf_dw1 dtu_sid timestamp local_time res1 last_cw bad_flag reinit\n"); + printk(" -------------------------------------------------------------------------------------\n"); + for ( i = (dtu_intf_wrptr + 1) % 16, cnt = 0; cnt < 16; cnt ++, i = (i + 1) % 16 ) { + if(cnt < 15) + printk(" "); + else + printk(" *"); + printk("%3d %04x %04x %3d[%02x] %3d[%02x] %3d[%02x] 0x%02x %d %d %d\n", + i, + (*(unsigned int *)&rec[i]) & 0xffff, + (*(unsigned int *)&rec[i]) >> 16, + rec[i].dtu_sid, rec[i].dtu_sid, + rec[i].dtu_timestamp, rec[i].dtu_timestamp, + rec[i].local_time, rec[i].local_time, + rec[i].res1_1, + rec[i].is_last_cw, + rec[i].is_bad_cw, + rec[i].reinit_flag ); + } + } + else if ( stricmp(p, "read_wrx_context") == 0 ) { + int i = 0; + int flag = 0; + for( i = 0; i < 8; ++i ) { + if ( !WRX_QUEUE_CONTEXT(i)->curr_des0 || !WRX_QUEUE_CONTEXT(i)->curr_des1 ) + continue; + + flag = 1; + printk("WRX queue context [ %d ]: \n", i); + printk(" curr_len = %4d, mfs = %d, ec = %d, clp1 = %d, aal5dp = %d\n", + WRX_QUEUE_CONTEXT(i)->curr_len, WRX_QUEUE_CONTEXT(i)->mfs, + WRX_QUEUE_CONTEXT(i)->ec, WRX_QUEUE_CONTEXT(i)->clp1, + WRX_QUEUE_CONTEXT(i)->aal5dp); + printk(" initcrc = %08x\n", WRX_QUEUE_CONTEXT(i)->intcrc); + printk(" currdes = %08x %08x\n", + WRX_QUEUE_CONTEXT(i)->curr_des0, WRX_QUEUE_CONTEXT(i)->curr_des1); + printk(" last_dw = %08x\n\n", WRX_QUEUE_CONTEXT(i)->last_dword); + if( WRX_QUEUE_CONTEXT(i)->curr_len ) { + int j = 0; + unsigned char *p_char; + struct rx_descriptor *desc = (struct rx_descriptor *)&(WRX_QUEUE_CONTEXT(i)->curr_des0); + p_char = (unsigned char *)(((unsigned int)desc->dataptr << 2) | KSEG1); + printk(" Data in SDRAM:\n "); + + for ( j = 0 ; j < WRX_QUEUE_CONTEXT(i)->curr_len; ++j ) { + printk ("%02x", p_char[j]); + if ( j % 16 == 15 ) + printk("\n "); + else if ( j % 4 == 3 ) + printk (" "); + } + printk("\n\n"); + } + } + if ( !flag ) { + printk("No active wrx queue context\n"); + } + } + else if ( stricmp(p, "clear_pb") == 0 ) { + if ( g_retx_playout_buffer ) + memset((void *)g_retx_playout_buffer, 0, RETX_PLAYOUT_BUFFER_SIZE); + } + else if ( stricmp(p, "read_bad_dtu_intf_rec") == 0 ) { + struct Retx_adsl_ppe_intf first_dtu_intf, last_dtu_intf; + first_dtu_intf = *FIRST_BAD_REC_RETX_ADSL_PPE_INTF; + last_dtu_intf = *BAD_REC_RETX_ADSL_PPE_INTF; + + printk("\nAdsl-PPE Interface for first and last DTU of recent noise:\n\n"); + printk(" dtu_sid = 0x%02x [%3u], 0x%02x [%3u]\n", + first_dtu_intf.dtu_sid, first_dtu_intf.dtu_sid, + last_dtu_intf.dtu_sid, last_dtu_intf.dtu_sid); + printk(" dtu_timestamp = 0x%02x , 0x%02x\n", + first_dtu_intf.dtu_timestamp, last_dtu_intf.dtu_timestamp); + printk(" local_time = 0x%02x , 0x%02x\n", + first_dtu_intf.local_time, last_dtu_intf.local_time); + printk(" is_last_cw = %u , %u\n", + first_dtu_intf.is_last_cw, last_dtu_intf.is_last_cw); + printk(" reinit_flag = %u , %u\n", + first_dtu_intf.reinit_flag, last_dtu_intf.reinit_flag); + printk(" is_bad_cw = %u , %u\n\n", + first_dtu_intf.is_bad_cw, last_dtu_intf.is_bad_cw); + } + else if ( stricmp(p, "clear_bad_dtu_intf_rec") == 0 ) { + memset((void *)BAD_REC_RETX_ADSL_PPE_INTF, 0, sizeof(struct Retx_adsl_ppe_intf)); + memset((void *)FIRST_BAD_REC_RETX_ADSL_PPE_INTF, 0, sizeof(struct Retx_adsl_ppe_intf)); + } + else if ( stricmp(p, "clear_tx_cb") == 0 ) { + unsigned int *dbase0; + unsigned int pnum0; + + dbase0 = (unsigned int *)PPM_INT_UNIT_ADDR( FFSM_DBA(0)->dbase + 0x2000); + pnum0 = FFSM_CFG(0)->pnum; + memset(dbase0, 0, 14 * sizeof(unsigned int ) * pnum0); + } + else if ( stricmp(p, "clear_rx_cb") == 0 ) { + unsigned int *dbase0, *cbase0, *dbase1, *cbase1; + unsigned int pnum0; + + dbase0 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_DBA(0)->dbase + 0x2000); + cbase0 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_CBA(0)->cbase + 0x2000); + + dbase1 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_DBA(1)->dbase + 0x2000); + cbase1 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_CBA(1)->cbase + 0x2000); + + pnum0 = SFSM_CFG(0)->pnum; + + memset(dbase0, 0, 14 * sizeof(unsigned int ) * pnum0); + memset(cbase0, 0, sizeof(unsigned int ) * pnum0); + + memset(dbase1, 0, 14 * sizeof(unsigned int )); + memset(cbase1, 0, sizeof(unsigned int )); + } + else if ( strnicmp(p, "read_tx_cb", 10) == 0 ) { + unsigned int *dbase0; + unsigned int pnum0, i; + unsigned int * cell; + + dbase0 = (unsigned int *)PPM_INT_UNIT_ADDR( FFSM_DBA(0)->dbase + 0x2000); + pnum0 = FFSM_CFG(0)->pnum; + + printk("ATM TX BC 0 CELL data/ctrl buffer:\n\n"); + for(i = 0; i < pnum0 ; ++ i) { + cell = dbase0 + i * 14; + printk("cell %2d: %08x %08x\n", i, cell[0], cell[1]); + printk(" %08x %08x %08x %08x\n", cell[2], cell[3], cell[4], cell[5]); + printk(" %08x %08x %08x %08x\n", cell[6], cell[7], cell[8], cell[9]); + printk(" %08x %08x %08x %08x\n", cell[10], cell[11], cell[12], cell[13]); + } + } + else if ( strnicmp(p, "read_rx_cb", 10) == 0 ) { + unsigned int *dbase0, *cbase0, *dbase1, *cbase1; + unsigned int pnum0, i; + unsigned int * cell; + + dbase0 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_DBA(0)->dbase + 0x2000); + cbase0 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_CBA(0)->cbase + 0x2000); + + dbase1 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_DBA(1)->dbase + 0x2000); + cbase1 = (unsigned int *)PPM_INT_UNIT_ADDR( SFSM_CBA(1)->cbase + 0x2000); + + pnum0 = SFSM_CFG(0)->pnum; + + printk("ATM RX BC 0 CELL data/ctrl buffer:\n\n"); + for(i = 0; i < pnum0 ; ++ i) { + struct Retx_ctrl_field * p_ctrl; + + cell = dbase0 + i * 14; + p_ctrl = (struct Retx_ctrl_field *) ( &cbase0[i]); + printk("cell %2d: %08x %08x -- [%08x]:", i, cell[0], cell[1], cbase0[i]); + + printk("l2_drop: %d, retx: %d", p_ctrl->l2_drop, p_ctrl->retx); + if ( p_ctrl->retx ) { + printk(", dtu_sid = %u, cell_sid = %u", p_ctrl->dtu_sid, p_ctrl->cell_sid); + } + + printk("\n"); + + printk(" %08x %08x %08x %08x\n", cell[2], cell[3], cell[4], cell[5]); + printk(" %08x %08x %08x %08x\n", cell[6], cell[7], cell[8], cell[9]); + printk(" %08x %08x %08x %08x\n", cell[10], cell[11], cell[12], cell[13]); + } + + printk("\n"); + printk("ATM RX BC 1 CELL data/ctrl buffer:\n\n"); + cell = dbase1; + printk("cell %2d: %08x %08x -- [%08x]: dtu_sid:%3d, cell_sid:%3d, next_ptr: %4d\n", + 0, cell[0], cell[1], cbase0[i], ( cell[1] >> 16) & 0xff, (cell[1] >> 24) & 0xff, cell[1] & 0xffff ); + printk(" %08x %08x %08x %08x\n", cell[2], cell[3], cell[4], cell[5]); + printk(" %08x %08x %08x %08x\n", cell[6], cell[7], cell[8], cell[9]); + printk(" %08x %08x %08x %08x\n", cell[10], cell[11], cell[12], cell[13]); + } + else if ( strnicmp(p, "read_pb ", 8) == 0 ) + { + int start_cell_idx = 0; + int cell_num = 0; + unsigned int *cell; + unsigned int pb_buff_size = RETX_MODE_CFG->buff_size * 32; + + p += 8; + rlen -= 8; + ignore_space(&p, &rlen); + + start_cell_idx = get_number(&p, &rlen, 0); + ignore_space(&p, &rlen); + cell_num = get_number(&p, &rlen, 0); + + if ( start_cell_idx >= pb_buff_size ) { + printk(" Invalid cell index\n"); + } + else { + int i; + if ( cell_num < 0 ) + cell_num = 1; + + if ( cell_num + start_cell_idx > pb_buff_size ) + cell_num = pb_buff_size - start_cell_idx; + + for ( i = 0; i < cell_num ; ++i ) { + cell = (unsigned int *)((unsigned int *)g_retx_playout_buffer + (14 * (start_cell_idx + i))); + printk("cell %4d: %08x %08x [next_ptr = %4u, dtu_sid = %3u, cell_sid = %3u]\n", + start_cell_idx + i, cell[0], cell[1], cell[1] & 0xffff, (cell[1] >> 16) & 0xff, (cell[1] >> 24) & 0xff); + printk(" %08x %08x %08x %08x\n", cell[2], cell[3], cell[4], cell[5]); + printk(" %08x %08x %08x %08x\n", cell[6], cell[7], cell[8], cell[9]); + printk(" %08x %08x %08x %08x\n", cell[10], cell[11], cell[12], cell[13]); + } + } + } + + return count; +} + +static int proc_read_retx_cfg(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + int len = 0; + + len += sprintf(page + off + len, "ReTX FW Config:\n"); + len += sprintf(page + off + len, " RETX_MODE_CFG = 0x%08x, invld_range=%u, buff_size=%u, retx=%u\n", *(volatile unsigned int *)RETX_MODE_CFG, (unsigned int)RETX_MODE_CFG->invld_range, (unsigned int)RETX_MODE_CFG->buff_size * 32, (unsigned int)RETX_MODE_CFG->retx_en); + len += sprintf(page + off + len, " RETX_TSYNC_CFG = 0x%08x, fw_alpha=%u, sync_inp=%u\n", *(volatile unsigned int *)RETX_TSYNC_CFG, (unsigned int)RETX_TSYNC_CFG->fw_alpha, (unsigned int)RETX_TSYNC_CFG->sync_inp); + len += sprintf(page + off + len, " RETX_TD_CFG = 0x%08x, td_max=%u, td_min=%u\n", *(volatile unsigned int *)RETX_TD_CFG, (unsigned int)RETX_TD_CFG->td_max, (unsigned int)RETX_TD_CFG->td_min); + len += sprintf(page + off + len, " RETX_PLAYOUT_BUFFER_BASE = 0x%08x\n", *RETX_PLAYOUT_BUFFER_BASE); + len += sprintf(page + off + len, " RETX_SERVICE_HEADER_CFG = 0x%08x\n", *RETX_SERVICE_HEADER_CFG); + len += sprintf(page + off + len, " RETX_MASK_HEADER_CFG = 0x%08x\n", *RETX_MASK_HEADER_CFG); + len += sprintf(page + off + len, " RETX_MIB_TIMER_CFG = 0x%08x, tick_cycle = %d, ticks_per_sec = %d\n", + *(unsigned int *)RETX_MIB_TIMER_CFG, RETX_MIB_TIMER_CFG->tick_cycle, RETX_MIB_TIMER_CFG->ticks_per_sec); + + *eof = 1; + + return len; +} + +static int proc_write_retx_cfg(struct file *file, const char *buf, unsigned long count, void *data) +{ + char *p1, *p2; + int len; + int colon; + char local_buf[1024]; + char *tokens[4] = {0}; + unsigned int token_num = 0; + + len = sizeof(local_buf) < count ? sizeof(local_buf) - 1 : count; + len = len - copy_from_user(local_buf, buf, len); + local_buf[len] = 0; + + p1 = local_buf; + colon = 0; + while ( token_num < NUM_ENTITY(tokens) && get_token(&p1, &p2, &len, &colon) ) { + tokens[token_num++] = p1; + + p1 = p2; + } + + if ( token_num > 0 ) { + if ( stricmp(tokens[0], "help") == 0 ) { + printk("echo help > /proc/driver/ifx_atm/retx_cfg ==> \n\tprint this help message\n\n"); + + printk("echo set retx <enable|disable|0|1|on|off> > /proc/driver/ifx_atm/retx_cfg\n"); + printk("\t:enable or disable retx feature\n\n"); + + printk("echo set <td_max|td_min|fw_alpha|sync_inp|invld_range|buff_size> <number> > /proc/driver/ifx_atm/retx_cfg\n"); + printk("\t: set td_max, td_min, fw_alpha, sync_inp, invalid_range, buff_size\n\n"); + + printk("echo set <service_header|service_mask> <hex_number> /proc/driver/ifx_atm/retx_cfg \n"); + printk("\t: set service_header, service_mask\n\n"); + } + else if ( stricmp(tokens[0], "set") == 0 && token_num >= 3 ) { + + if ( stricmp(tokens[1], "retx") == 0 ) { + if ( stricmp(tokens[2], "enable") == 0 || + stricmp(tokens[2], "on") == 0 || + stricmp(tokens[2], "1") == 0 ) + RETX_MODE_CFG->retx_en = 1; + else if ( stricmp(tokens[2], "disable") == 0 || + stricmp(tokens[2], "off") == 0 || + stricmp(tokens[2], "0") == 0 ) + RETX_MODE_CFG->retx_en = 0; + printk("RETX_MODE_CFG->retx_en - %d\n", RETX_MODE_CFG->retx_en); + } + else { + unsigned int dec_val, hex_val; + + p1 = tokens[2]; + dec_val = (unsigned int)get_number(&p1, NULL, 0); + p2 = tokens[2]; + hex_val = (unsigned int)get_number(&p2, NULL, 1); + + if ( *p2 == 0 ) { + if ( stricmp(tokens[1], "service_header") == 0 ) { + *RETX_SERVICE_HEADER_CFG = hex_val; + printk("RETX_SERVICE_HEADER_CFG - 0x%08x\n", *RETX_SERVICE_HEADER_CFG); + } + else if ( stricmp(tokens[1], "service_mask") == 0 ) { + *RETX_MASK_HEADER_CFG = hex_val; + printk("RETX_MASK_HEADER_CFG - 0x%08x\n", *RETX_MASK_HEADER_CFG); + } + } + if ( *p1 == 0 ) { + if ( stricmp(tokens[1], "td_max") == 0 ) { + (unsigned int)RETX_TD_CFG->td_max = (dec_val >= 0xff ? 0Xff : dec_val); + printk("RETX_TD_CFG->td_max - %d\n", RETX_TD_CFG->td_max); + } + else if ( stricmp(tokens[1], "td_min") == 0 ) { + (unsigned int)RETX_TD_CFG->td_min = (dec_val >= 0xff ? 0Xff : dec_val); + printk("RETX_TD_CFG->td_min - %d\n", RETX_TD_CFG->td_min); + } + else if ( stricmp(tokens[1], "fw_alpha") == 0 ) { + RETX_TSYNC_CFG->fw_alpha = dec_val >= 0x7FFE ? 0X7EEE : dec_val; + printk("RETX_TSYNC_CFG->fw_alpha - %d\n", RETX_TSYNC_CFG->fw_alpha); + } + else if ( stricmp(tokens[1], "sync_inp") == 0 ) { + RETX_TSYNC_CFG->sync_inp = dec_val >= 0x7FFE ? 0X7EEE : dec_val; + printk("RETX_TSYNC_CFG->sync_inp - %d\n", RETX_TSYNC_CFG->sync_inp); + } + else if ( stricmp(tokens[1], "invld_range") == 0 ) { + RETX_MODE_CFG->invld_range = dec_val >= 250 ? 250 : dec_val; + printk("RETX_MODE_CFG->invld_range - %d\n", RETX_MODE_CFG->invld_range); + } + else if ( stricmp(tokens[1], "buff_size") == 0 ) { + dec_val = (dec_val + 31) / 32; + RETX_MODE_CFG->buff_size = dec_val >= 4096 / 32 ? 4096 / 32 : dec_val; + printk("RETX_MODE_CFG->buff_size - %d\n", RETX_MODE_CFG->buff_size); + } + } + } + + } + } + + return count; +} + +static int proc_read_retx_dsl_param(char *page, char **start, off_t off, int count, int *eof, void *data) +{ + int len = 0; + + len += sprintf(page + off + len, "DSL Param [timestamp %ld.%ld]:\n", g_retx_polling_start.tv_sec, g_retx_polling_start.tv_usec); + + if ( g_xdata_addr == NULL ) + len += sprintf(page + off + len, " DSL parameters not available !\n"); + else { + volatile struct dsl_param *p_dsl_param = (volatile struct dsl_param *)g_xdata_addr; + + len += sprintf(page + off + len, " update_flag = %u\n", p_dsl_param->update_flag); + len += sprintf(page + off + len, " MinDelayrt = %u\n", p_dsl_param->MinDelayrt); + len += sprintf(page + off + len, " MaxDelayrt = %u\n", p_dsl_param->MaxDelayrt); + len += sprintf(page + off + len, " RetxEnable = %u\n", p_dsl_param->RetxEnable); + len += sprintf(page + off + len, " ServiceSpecificReTx = %u\n", p_dsl_param->ServiceSpecificReTx); + len += sprintf(page + off + len, " ReTxPVC = 0x%08x\n", p_dsl_param->ReTxPVC); + len += sprintf(page + off + len, " RxDtuCorruptedCNT = %u\n", p_dsl_param->RxDtuCorruptedCNT); + len += sprintf(page + off + len, " RxRetxDtuUnCorrectedCNT = %u\n", p_dsl_param->RxRetxDtuUnCorrectedCNT); + len += sprintf(page + off + len, " RxLastEFB = %u\n", p_dsl_param->RxLastEFB); + len += sprintf(page + off + len, " RxDtuCorrectedCNT = %u\n", p_dsl_param->RxDtuCorrectedCNT); + } + if ( g_retx_polling_end.tv_sec != 0 || g_retx_polling_end.tv_usec != 0 ) { + unsigned long polling_time_usec; + + polling_time_usec = (g_retx_polling_end.tv_sec - g_retx_polling_start.tv_sec) * 1000000 + (g_retx_polling_end.tv_usec - g_retx_polling_start.tv_usec); + len += sprintf(page + off + len, "DSL Param Update Time: %lu.%03lums\n", polling_time_usec / 1000, polling_time_usec % 1000); + } + + return len; +} + + #endif + #endif static int stricmp(const char *p1, const char *p2) { int c1, c2; - while ( *p1 && *p2 ) - { + while ( *p1 && *p2 ) { c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1; c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2; if ( (c1 -= c2) ) @@ -1905,12 +4028,12 @@ static int stricmp(const char *p1, const char *p2) } #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC + static int strincmp(const char *p1, const char *p2, int n) { int c1 = 0, c2; - while ( n && *p1 && *p2 ) - { + while ( n && *p1 && *p2 ) { c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1; c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2; if ( (c1 -= c2) ) @@ -1922,6 +4045,104 @@ static int strincmp(const char *p1, const char *p2, int n) return n ? *p1 - *p2 : c1; } + +static int get_token(char **p1, char **p2, int *len, int *colon) +{ + int tlen = 0; + + while ( *len && !((**p1 >= 'A' && **p1 <= 'Z') || (**p1 >= 'a' && **p1<= 'z') || (**p1 >= '0' && **p1<= '9')) ) + { + (*p1)++; + (*len)--; + } + if ( !*len ) + return 0; + + if ( *colon ) + { + *colon = 0; + *p2 = *p1; + while ( *len && **p2 > ' ' && **p2 != ',' ) + { + if ( **p2 == ':' ) + { + *colon = 1; + break; + } + (*p2)++; + (*len)--; + tlen++; + } + **p2 = 0; + } + else + { + *p2 = *p1; + while ( *len && **p2 > ' ' && **p2 != ',' ) + { + (*p2)++; + (*len)--; + tlen++; + } + **p2 = 0; + } + + return tlen; +} + +static unsigned int get_number(char **p, int *len, int is_hex) +{ + unsigned int ret = 0; + unsigned int n = 0; + + if ( (*p)[0] == '0' && (*p)[1] == 'x' ) + { + is_hex = 1; + (*p) += 2; + if ( len ) + (*len) -= 2; + } + + if ( is_hex ) + { + while ( (!len || *len) && ((**p >= '0' && **p <= '9') || (**p >= 'a' && **p <= 'f') || (**p >= 'A' && **p <= 'F')) ) + { + if ( **p >= '0' && **p <= '9' ) + n = **p - '0'; + else if ( **p >= 'a' && **p <= 'f' ) + n = **p - 'a' + 10; + else if ( **p >= 'A' && **p <= 'F' ) + n = **p - 'A' + 10; + ret = (ret << 4) | n; + (*p)++; + if ( len ) + (*len)--; + } + } + else + { + while ( (!len || *len) && **p >= '0' && **p <= '9' ) + { + n = **p - '0'; + ret = ret * 10 + n; + (*p)++; + if ( len ) + (*len)--; + } + } + + return ret; +} + +static void ignore_space(char **p, int *len) +{ + while ( *len && (**p <= ' ' || **p == ':' || **p == '.' || **p == ',') ) + { + (*p)++; + (*len)--; + } +} + #endif static INLINE int ifx_atm_version(char *buf) @@ -1931,19 +4152,11 @@ static INLINE int ifx_atm_version(char *buf) ifx_atm_get_fw_ver(&major, &minor); - len += sprintf(buf + len, "Infineon Technologies ATM driver version %d.%d.%d\n", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR); - len += sprintf(buf + len, "Infineon Technologies ATM (A1) firmware version %d.%d\n", major, minor); + len += sprintf(buf + len, " ATM (A1) firmware version %d.%d.%d\n", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID,IFX_ATM_VER_MINOR); return len; } -#ifdef MODULE -static INLINE void reset_ppe(void) -{ - // TODO: -} -#endif - static INLINE void check_parameters(void) { /* Please refer to Amazon spec 15.4 for setting these values. */ @@ -2155,7 +4368,9 @@ static INLINE void init_rx_tables(void) * General Registers */ *CFG_WRX_HTUTS = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER; +#ifndef CONFIG_AMAZON_SE *CFG_WRX_QNUM = MAX_QUEUE_NUMBER; +#endif *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL; *WRX_DMACH_ON = (1 << RX_DMA_CH_TOTAL) - 1; *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH; @@ -2279,11 +4494,12 @@ static INLINE void init_tx_tables(void) /* * WTX Queue Configuration Table */ - wtx_queue_config.type = 0x0; wtx_queue_config.qsben = 1; wtx_queue_config.sbid = 0; - for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) + for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) { + wtx_queue_config.qsb_vcid = i; *WTX_QUEUE_CONFIG(i) = wtx_queue_config; + } /* * WTX DMA Channel Configuration Table @@ -2337,13 +4553,29 @@ static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr IFX_REG_W32(0x0F, UTP_CFG); #endif - pr_debug("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr); +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + if ( !timer_pending(&g_retx_polling_timer) ) { + g_retx_polling_cnt = HZ; + g_retx_polling_timer.expires = jiffies + RETX_POLLING_INTERVAL; + add_timer(&g_retx_polling_timer); + } +#endif + + //printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr); return IFX_SUCCESS; } static int atm_showtime_exit(void) { + if ( !g_showtime ) + return IFX_ERROR; + +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + RETX_MODE_CFG->retx_en = 0; // disable ReTX + del_timer(&g_retx_polling_timer); +#endif + #if defined(CONFIG_VR9) IFX_REG_W32(0x00, UTP_CFG); #endif @@ -2353,7 +4585,7 @@ static int atm_showtime_exit(void) // TODO: ReTX clean state g_xdata_addr = NULL; - pr_debug("leave showtime\n"); + printk("leave showtime\n"); return IFX_SUCCESS; } @@ -2384,10 +4616,6 @@ static int __devinit ifx_atm_init(void) int i, j; char ver_str[256]; -#ifdef MODULE - reset_ppe(); -#endif - check_parameters(); ret = init_priv_data(); @@ -2407,6 +4635,7 @@ static int __devinit ifx_atm_init(void) #else g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL); #endif + if ( !g_atm_priv_data.port[port_num].dev ) { err("failed to register atm device %d!", port_num); ret = -EIO; @@ -2433,6 +4662,13 @@ static int __devinit ifx_atm_init(void) } disable_irq(PPE_MAILBOX_IGU1_INT); +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + init_atm_tc_retrans_param(); + + init_timer(&g_retx_polling_timer); + g_retx_polling_timer.function = retx_polling_func; +#endif + ret = ifx_pp32_start(0); if ( ret ) { err("ifx_pp32_start fail!"); @@ -2440,7 +4676,8 @@ static int __devinit ifx_atm_init(void) } port_cell.port_num = ATM_PORT_NUMBER; - ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr); + if( !IS_ERR(&ifx_mei_atm_showtime_check) && &ifx_mei_atm_showtime_check) + ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr); if ( g_showtime ) { for ( i = 0; i < ATM_PORT_NUMBER; i++ ) if ( port_cell.tx_link_rate[i] != 0 ) @@ -2452,11 +4689,18 @@ static int __devinit ifx_atm_init(void) qsb_global_set(); validate_oam_htu_entry(); +#if 0 /*defined(ENABLE_LED_FRAMEWORK) && ENABLE_LED_FRAMEWORK*/ + ifx_led_trigger_register("dsl_data", &g_data_led_trigger); +#endif + /* create proc file */ proc_file_create(); - ifx_mei_atm_showtime_enter = atm_showtime_enter; - ifx_mei_atm_showtime_exit = atm_showtime_exit; + if( !IS_ERR(&ifx_mei_atm_showtime_enter) && &ifx_mei_atm_showtime_enter ) + ifx_mei_atm_showtime_enter = atm_showtime_enter; + + if( !IS_ERR(&ifx_mei_atm_showtime_exit) && !ifx_mei_atm_showtime_exit ) + ifx_mei_atm_showtime_exit = atm_showtime_exit; ifx_atm_version(ver_str); printk(KERN_INFO "%s", ver_str); @@ -2489,15 +4733,27 @@ static void __exit ifx_atm_exit(void) { int port_num; - ifx_mei_atm_showtime_enter = NULL; - ifx_mei_atm_showtime_exit = NULL; + if( !IS_ERR(&ifx_mei_atm_showtime_enter) && &ifx_mei_atm_showtime_enter ) + ifx_mei_atm_showtime_enter = NULL; + if( !IS_ERR(&ifx_mei_atm_showtime_exit) && !ifx_mei_atm_showtime_exit ) + ifx_mei_atm_showtime_exit = NULL; proc_file_delete(); +#if 0 /*defined(ENABLE_LED_FRAMEWORK) && ENABLE_LED_FRAMEWORK*/ + ifx_led_trigger_deregister(g_data_led_trigger); + g_data_led_trigger = NULL; +#endif + invalidate_oam_htu_entry(); ifx_pp32_stop(0); +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + del_timer(&g_retx_polling_timer); + clear_atm_tc_retrans_param(); +#endif + free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data); for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) diff --git a/package/ltq-dsl/src/ifxmips_atm_core.h b/package/ltq-dsl/src/ifxmips_atm_core.h index 8f0a3ebfba..e566039552 100644 --- a/package/ltq-dsl/src/ifxmips_atm_core.h +++ b/package/ltq-dsl/src/ifxmips_atm_core.h @@ -52,6 +52,8 @@ #define DEBUG_QOS 1 +#define DISABLE_QOS_WORKAROUND 0 + #define ENABLE_DBG_PROC 1 #define ENABLE_FW_PROC 1 @@ -60,6 +62,13 @@ #define ENABLE_TASKLET 1 #endif +#ifdef CONFIG_IFX_ATM_RETX + #define ENABLE_ATM_RETX 1 +#endif + +#if defined(CONFIG_DSL_MEI_CPE_DRV) && !defined(CONFIG_IFXMIPS_DSL_CPE_MEI) + #define CONFIG_IFXMIPS_DSL_CPE_MEI 1 +#endif /* * Debug/Assert/Error Message @@ -72,7 +81,8 @@ #define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9) #define DBG_ENABLE_MASK_DUMP_QOS (1 << 10) #define DBG_ENABLE_MASK_DUMP_INIT (1 << 11) -#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT) +#define DBG_ENABLE_MASK_MAC_SWAP (1 << 12) +#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT | DBG_ENABLE_MASK_MAC_SWAP) #define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 ) @@ -131,11 +141,11 @@ #define OAM_F5_HTU_ENTRY 2 #define OAM_F4_CELL_ID 0 #define OAM_F5_CELL_ID 15 -//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX -// #undef OAM_HTU_ENTRY_NUMBER -// #define OAM_HTU_ENTRY_NUMBER 4 -// #define OAM_ARQ_HTU_ENTRY 3 -//#endif +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + #undef OAM_HTU_ENTRY_NUMBER + #define OAM_HTU_ENTRY_NUMBER 4 + #define OAM_ARQ_HTU_ENTRY 3 +#endif /* * RX Frame Definitions @@ -159,6 +169,16 @@ */ #define CELL_SIZE ATM_AAL0_SDU +/* + * ReTX Constant + */ +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + #define RETX_PLAYOUT_BUFFER_ORDER 6 + #define RETX_PLAYOUT_BUFFER_SIZE (PAGE_SIZE * (1 << RETX_PLAYOUT_BUFFER_ORDER)) + #define RETX_PLAYOUT_FW_BUFF_SIZE (RETX_PLAYOUT_BUFFER_SIZE / (32 * 56 /* cell size */)) + #define RETX_POLLING_INTERVAL (HZ / 100 > 0 ? HZ / 100 : 1) +#endif + /* @@ -244,6 +264,8 @@ extern void ifx_atm_uninit_chip(void); extern int ifx_pp32_start(int pp32); extern void ifx_pp32_stop(int pp32); +extern void ifx_reset_ppe(void); + #endif // IFXMIPS_ATM_CORE_H diff --git a/package/ltq-dsl/src/ifxmips_atm_danube.c b/package/ltq-dsl/src/ifxmips_atm_danube.c index 583b5646b6..df7801e234 100644 --- a/package/ltq-dsl/src/ifxmips_atm_danube.c +++ b/package/ltq-dsl/src/ifxmips_atm_danube.c @@ -48,9 +48,11 @@ #include <lantiq_soc.h> #include "ifxmips_compat.h" #include "ifxmips_atm_core.h" -#include "ifxmips_atm_fw_danube.h" - - +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + #include "ifxmips_atm_fw_danube_retx.h" +#else + #include "ifxmips_atm_fw_danube.h" +#endif /* * #################################### @@ -81,6 +83,7 @@ */ static inline void init_pmu(void); static inline void uninit_pmu(void); +static inline void reset_ppe(void); static inline void init_ema(void); static inline void init_mailbox(void); static inline void init_atm_tc(void); @@ -105,7 +108,7 @@ static inline void clear_share_buffer(void); static inline void init_pmu(void) { //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9)); - PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); + //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); @@ -122,7 +125,32 @@ static inline void uninit_pmu(void) PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE); PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE); DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE); - PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); + //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); +} + +static inline void reset_ppe(void) +{ +#if 0 //def MODULE + unsigned int etop_cfg; + unsigned int etop_mdio_cfg; + unsigned int etop_ig_plen_ctrl; + unsigned int enet_mac_cfg; + + etop_cfg = *IFX_PP32_ETOP_CFG; + etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG; + etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL; + enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG; + + *IFX_PP32_ETOP_CFG &= ~0x03C0; + + // reset PPE + ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM); + + *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg; + *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl; + *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg; + *IFX_PP32_ETOP_CFG = etop_cfg; +#endif } static inline void init_ema(void) @@ -143,9 +171,25 @@ static inline void init_mailbox(void) static inline void init_atm_tc(void) { - // for ReTX expansion in future - //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); // pnum = 6 - //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); // pnum = 6 + IFX_REG_W32(0x0000, DREG_AT_CTRL); + IFX_REG_W32(0x0000, DREG_AR_CTRL); + IFX_REG_W32(0x0, DREG_AT_IDLE0); + IFX_REG_W32(0x0, DREG_AT_IDLE1); + IFX_REG_W32(0x0, DREG_AR_IDLE0); + IFX_REG_W32(0x0, DREG_AR_IDLE1); + IFX_REG_W32(0x40, RFBI_CFG); + IFX_REG_W32(0x1600, SFSM_DBA0); + IFX_REG_W32(0x1718, SFSM_DBA1); + IFX_REG_W32(0x1830, SFSM_CBA0); + IFX_REG_W32(0x1844, SFSM_CBA1); + IFX_REG_W32(0x14014, SFSM_CFG0); + IFX_REG_W32(0x14014, SFSM_CFG1); + IFX_REG_W32(0x1858, FFSM_DBA0); + IFX_REG_W32(0x18AC, FFSM_DBA1); + IFX_REG_W32(0x10006, FFSM_CFG0); + IFX_REG_W32(0x10006, FFSM_CFG1); + IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0); + IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1); } static inline void clear_share_buffer(void) @@ -178,7 +222,7 @@ static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) IFX_REG_W32(0x00, CDM_CFG); else - IFX_REG_W32(0x02, CDM_CFG); + IFX_REG_W32(0x04, CDM_CFG); /* copy code */ dest = CDM_CODE_MEMORY(0, 0); @@ -206,14 +250,21 @@ extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor) ASSERT(major != NULL, "pointer is NULL"); ASSERT(minor != NULL, "pointer is NULL"); +#if (defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX) || defined(VER_IN_FIRMWARE) + *major = FW_VER_ID->major; + *minor = FW_VER_ID->minor; +#else *major = ATM_FW_VER_MAJOR; *minor = ATM_FW_VER_MINOR; +#endif } void ifx_atm_init_chip(void) { init_pmu(); + reset_ppe(); + init_ema(); init_mailbox(); diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_amazon_se.h b/package/ltq-dsl/src/ifxmips_atm_fw_amazon_se.h new file mode 100644 index 0000000000..4daef9fd8c --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_amazon_se.h @@ -0,0 +1,3335 @@ +#ifndef IFXMIPS_ATM_FW_AMAZON_SE_H +#define IFXMIPS_ATM_FW_AMAZON_SE_H + + +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_amazon_se.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PP32 Firmware) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + +#define ATM_FW_VER_MAJOR 0 +#define ATM_FW_VER_MINOR 1 + + +static unsigned int firmware_binary_code[] = { +0x80000ac0, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x8000ffe0, +0x00000000, +0x00000000, +0x00000000, +0xc1000002, +0xd90c00f8, +0xc2000002, +0xda0800f9, +0x80004d48, +0xc2000000, +0xda0800f9, +0x800043b8, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x80004370, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x80005550, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x80004270, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0xc0400000, +0xc0004840, +0xc88400f8, +0x80004a08, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0xc0400002, +0xc0004840, +0xc88400f8, +0x80004988, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0xc3c00004, +0xdbc800f9, +0xc10c0002, +0xd90c00f8, +0x8000fee0, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, 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+0x9d000000, +0x58140030, +0xc5d80078, +0xcd800078, +0xc1c00000, +0xdf5c0038, +0x5ddc0080, +0x8400ffea, +0x00000000, +0x9d000000, +0x00000000, +0x00000000, +0x00000000, +0xc160fffe, +0xc0000a10, +0xc9440060, +0xc1a0fffe, +0x59981e08, +0xc000100c, +0xcd4000f8, +0xc000100e, +0xcd8000f8, +0xc0004964, +0xc98000f8, +0x00000000, +0xc170000a, +0x7158a000, +0x6c988000, +0x4588c000, +0x4588c000, +0x59980004, +0xc5940270, +0xc0001010, +0xcd4000f8, +0xc0004946, +0xc94000f8, +0x00000000, +0x00000000, +0x6d58a000, +0x6d5c4000, +0x459cc000, +0x4594c000, +0xc000494a, +0xc94000f8, +0xc0004948, +0xc9c000f8, +0x4194c000, +0xc1400012, +0xc55c1818, +0x9d000000, +0xc59c0268, +0xc0001012, +0xcdc000f8, +0xc1400000, +0x58000012, +0xc9410038, +0xc0004950, +0xc9c000f8, +0xc55800f8, +0xc5940838, +0xc5581078, +0xd99400f8, +0xc000493c, +0xc94000f8, +0xc0004954, +0xc98000f8, +0x59dc00a8, +0x45d4e000, +0x41d8e000, +0x5d5c0030, +0x88000010, +0xc1c00030, +0xc1800000, +0xc5d84028, +0xc1400000, +0xc5d40008, +0x5dd40002, +0x84000072, +0x5dd40004, +0x8400009a, +0x5dd40006, +0x840000c2, +0x5dd80026, +0x840000ea, +0xdd5400f8, +0xdd8000f9, +0x58000008, +0x40180000, +0xcd4000f8, +0x59980002, +0x8000ffc0, +0xdd5400f8, +0xdd8000f9, +0x58000008, +0x40180000, +0xcd4000b8, +0x59980002, +0x8000ff88, +0xdd5400f8, +0xdd8000f9, +0x58000008, +0x40180000, +0xcd400078, +0x59980002, +0x8000ff50, +0xdd5400f8, +0xdd8000f9, +0x58000008, +0x40180000, +0xcd400038, +0x59980002, +0x8000ff18, +0x00000000, +0x9d000000, +0x00000000, +0x00000000, +0x00000000, +0x58000012, +0xc94000f8, +0xc0004954, +0xc9c000f8, +0xc0004950, +0xc9400078, +0xdd8000f9, +0x58000028, +0x5d9c0000, +0x84000052, +0x5d9c0002, +0x84000052, +0x5d9c0004, +0x8400006a, +0xc55b0038, +0xc55c08b8, +0xcd800039, +0xcdc108b8, +0x80000060, +0xcd4000f8, +0x80000050, +0xc55900b8, +0xc55c1838, +0xcd8000b9, +0xcdc31838, +0x80000028, +0xc55a0078, +0xc55c1078, +0xcd800079, +0xcdc21078, +0x9d000000, +0x00000000, +0x00000000, +0x00000000, +0x59540002, +0x6994e018, +0x61c0c008, +0x4194a000, +0x5d940040, +0x88000012, +0xc59400f8, +0x9d000000, +0xcd4000f8, +0x00000000, +0x00000000, +0x9d000000, +0x4158a000, +0xcd4000f8, +0x00000000 +}; + +static unsigned int firmware_binary_data[] = { +}; + + +#endif // IFXMIPS_ATM_FW_AMAZON_SE_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_ar9.h b/package/ltq-dsl/src/ifxmips_atm_fw_ar9.h new file mode 100644 index 0000000000..b22bcccca4 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_ar9.h @@ -0,0 +1,439 @@ +#ifndef IFXMIPS_ATM_FW_AR9_H +#define IFXMIPS_ATM_FW_AR9_H + + +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_ar9.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 22 OCT 2007 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PP32 Firmware) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 22 OCT 2007 Xu Liang Initiate Version, v00.01 +*******************************************************************************/ + + +#define VER_IN_FIRMWARE 1 + +#define ATM_FW_VER_MAJOR 0 +#define ATM_FW_VER_MINOR 16 + + +static unsigned int firmware_binary_code[] = { + 0x800004b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000, + 0xc1000002, 0xd90c00f8, 0xc2000002, 0xda0800f9, 0x80004980, 0xc2000000, 0xda0800f9, 0x80003fe8, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80003fa0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80005178, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80003ea0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xc0400000, 0xc0004840, 0xc88400f8, 0x80004640, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xc0400002, 0xc0004840, 0xc88400f8, 0x800045c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xc3c00004, 0xdbc800f9, 0xc10c0002, 0xd90c00f8, 0x8000fee0, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xc10e0002, 0xd90c00f8, 0xc0004808, 0xc84000f8, 0x800045f0, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xc3e1fffe, 0x597dfffe, 0x593dfe14, 0x900004d9, 0x00000000, 0x00000000, 0x00000000, 0x90cc0481, + 0x00000000, 0x00000000, 0x00000000, 0xc3c00000, 0xdbc800f9, 0xc1400008, 0xc1900000, 0x71588000, + 0x14100100, 0xc140000a, 0xc1900002, 0x71588000, 0x14100100, 0xc140000c, 0xc1900004, 0x71588000, + 0x14100100, 0xc1400004, 0xc1900006, 0x71588000, 0x14100100, 0xc1400006, 0xc1900008, 0x71588000, + 0x14100100, 0xc140000e, 0xc190000a, 0x71588000, 0x14100100, 0xc1400000, 0xc190000c, 0x71588000, + 0x14100100, 0xc1400002, 0xc190000e, 0x71588000, 0x14100100, 0xc0400000, 0xc11c0000, 0xc000082c, + 0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0400002, 0xc11c0000, 0xc000082c, 0xcd05ce00, + 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0000824, 0x00000000, 0xcbc000f9, 0xcb8000f9, 0xcb4000f9, + 0xcb0000f8, 0xc0004878, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f9, 0x5b744000, 0xcf4000f9, + 0x5b304000, 0xcf0000f8, 0xc0000a10, 0x00000000, 0xcbc000f9, 0xcb8000f8, 0xc0004874, 0x5bfc4000, + 0xcfc000f9, 0x5bb84000, 0xcf8000f8, 0xc30001fe, 0xc000140a, 0xcf0000f8, 0xc3000000, 0x7f018000, + 0xc000042e, 0xcf0000f8, 0xc000040e, 0xcf0000f8, 0xc3c1fffe, 0xc000490e, 0xcfc00078, 0xc000492c, + 0xcfc00078, 0xc0004924, 0xcfc00038, 0xc0004912, 0xcfc00038, 0xc0004966, 0xcfc00038, 0xc0004968, + 0xcfc00078, 0xc000496a, 0xcfc00078, 0xc3c1fffe, 0xc00049a0, 0xcfc000f8, 0xc3c00000, 0xc2800020, + 0xc3000000, 0x7f018000, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x5838000a, 0xcf0000f8, + 0x5bfc0002, 0xb7e8ffc8, 0x00000000, 0xc3c00000, 0xc2800010, 0x6ff86000, 0x47bdc000, 0x5bb84c80, + 0xc3400000, 0x58380004, 0xcb420078, 0x00000000, 0x58380008, 0xcf400078, 0x5bfc0002, 0xb7e8ffb0, + 0x00000000, 0xc3c00000, 0xc2800020, 0xc348001e, 0xc3000000, 0x7f018000, 0x6ff8a000, 0x6fd44000, + 0x4795c000, 0x47bdc000, 0x5bb87000, 0x58380008, 0xcf408418, 0x5838000a, 0xcf0000f8, 0x5bfc0002, + 0xb7e8ffb0, 0x00000000, 0x00000000, 0xc3e0a242, 0x5bfc0020, 0xc0004002, 0xcfc000f8, 0x00000000, + 0xc121fffe, 0x5911fe14, 0x14100000, 0x80000530, 0x00000000, 0x80002130, 0x00000000, 0x8000ffe0, + 0xc0004958, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0004848, 0xcb8400f8, + 0xc000495c, 0xcac400f8, 0xc0004844, 0xc88400f8, 0x47ad0000, 0x8400ff82, 0xc000487c, 0xc80400f8, + 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc0001624, 0xcb0400f8, 0xa63c007a, 0x00000000, + 0x00000000, 0xa71eff22, 0x00000000, 0xc0000824, 0xca8400f8, 0x6ca08000, 0x6ca42000, 0x46250000, + 0x42290000, 0xc35e0002, 0xc6340060, 0xc0001624, 0xcf440078, 0xc2000000, 0xc161fffe, 0x5955fffe, + 0x14140000, 0x00000000, 0xc0004844, 0xc88400f8, 0xc000082c, 0xca040038, 0x00000000, 0x00000000, + 0x58880002, 0xb6080018, 0x00000000, 0xc0800000, 0xc0004844, 0xcc840038, 0x5aec0002, 0xc000495c, + 0xcec400f8, 0x5e6c0006, 0x84000060, 0xc0004848, 0xcb8400f8, 0xc0000838, 0xc2500002, 0xce450800, + 0x5fb80002, 0xc0004848, 0xcf8400f8, 0x5eec0002, 0xc000495c, 0xcec400f8, 0x00000000, 0xc121fffe, + 0x5911fe14, 0x14100000, 0x8000fd98, 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, + 0xcc4000f8, 0xc0004960, 0xcac400f8, 0x00000000, 0x00000000, 0x5eec0000, 0x8400010a, 0x00000000, + 0xb6fc0050, 0xc0001600, 0xca0400f8, 0x00000000, 0x00000000, 0xa61e00d2, 0x6fe90000, 0xc0000a28, + 0xce850800, 0xc2c00000, 0xc2800004, 0xb6e800a0, 0xc0001604, 0xca8400f8, 0xc0004960, 0xcec400f8, + 0xa69efcc2, 0x00000000, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00002, 0xc0001600, 0xca0400f8, + 0x00000000, 0x00000000, 0xa61e002a, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00000, 0xc0001604, + 0xca8400f8, 0xc0004960, 0xcec400f8, 0xa69efc2a, 0xc2400000, 0xc0000a14, 0xca440028, 0x00000000, + 0x00000000, 0x466d2000, 0xa4400020, 0xc2800000, 0xdfeb0029, 0x80000010, 0xdfea0029, 0xb668fba2, + 0x00000000, 0xc00048a0, 0xcb0400f8, 0xc0000a10, 0xca8400f8, 0x6f208000, 0x6f242000, 0x46250000, + 0x42a10000, 0xc2400000, 0xc0000a14, 0xca440028, 0xc35e0002, 0xc6340060, 0xc0001604, 0xcf440078, + 0x5b300002, 0xb6700018, 0x5aec0002, 0xc3000000, 0xc00048a0, 0xcf0400f8, 0xc0004960, 0xcec400f8, + 0x8000fad8, 0xc0004918, 0xd28000f8, 0xc2000000, 0xdf600038, 0x5e600080, 0x84000272, 0x00000000, + 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000480a, 0xca0000f8, 0xc0004912, 0xca4000f8, + 0xc0004924, 0xca8000f8, 0xc0004966, 0xcac000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, + 0x76250000, 0x76290000, 0x762d0000, 0x840001ca, 0xc0004918, 0xca4000f8, 0xc28001fe, 0x76290000, + 0x5a640002, 0x6a254010, 0x5ee80000, 0x8400001a, 0x6aa54000, 0x80000010, 0xc62800f8, 0x62818008, + 0xc0004918, 0xcf0000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0004966, 0xca4000f8, + 0xc2000002, 0x6a310000, 0x7e010000, 0x76612000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, + 0x14100000, 0x6f346000, 0x4771a000, 0x5b744c80, 0xc2800000, 0x58340006, 0xca800078, 0xc2c00000, + 0x58340000, 0xcac000d8, 0xc2400000, 0x5834000a, 0xca420078, 0x6ea82000, 0x42e9e000, 0x6f2ca000, + 0x42e56000, 0x5aec2e00, 0xc3990040, 0xc7381c18, 0xc6f80060, 0x99005b78, 0xdb9800f8, 0xdbd800f9, + 0x00000000, 0xdea000f8, 0x46310000, 0x8400fd80, 0xc0004958, 0xc84000f8, 0x00000000, 0xc3c00002, + 0x787c2000, 0xcc4000f8, 0xc0004848, 0xcb8400f8, 0xc0004844, 0xc88400f8, 0x5fb80000, 0x8400f7f2, + 0xc0001a1c, 0xca0000f8, 0xc2400002, 0x6a452000, 0x76250000, 0x8400f7c2, 0xc000487c, 0xc80400f8, + 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc42400f8, 0x00000000, 0xa63c17da, 0x00000000, + 0xc0004878, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000, 0x40100000, 0xca0000f8, 0xc42400f8, + 0x00000000, 0xc0004934, 0xce0000f8, 0xc2800002, 0xc4681c08, 0xc62821d0, 0xc2600010, 0x5a650060, + 0xc0004800, 0xcb4000f8, 0xc2200400, 0x5a200020, 0xc7601040, 0xc0001220, 0xce8000f8, 0xc0001200, + 0xce4000f8, 0xc0001202, 0xce0000f8, 0xc0001240, 0xcb4000f8, 0x00000000, 0x00000000, 0xa754ffe0, + 0xc2000000, 0xc7600040, 0xa7520042, 0x00000000, 0x00000000, 0x990062f0, 0xc0004822, 0xc94000f8, + 0xc1800002, 0x80001680, 0x582040a0, 0xc2000000, 0xca000018, 0xc2400000, 0xca414000, 0xc2800000, + 0xca812000, 0xc2c00000, 0xcac20018, 0xc0004938, 0xce0000f8, 0xc0004920, 0xce4000f8, 0xc0004916, + 0xce8000f8, 0xc0004922, 0xcec000f8, 0xa6400540, 0x00000000, 0xc0004938, 0xcbc000f8, 0x00000000, + 0xc3800000, 0x6ff48000, 0x6fd44000, 0x4355a000, 0x5b744a00, 0x58340000, 0xcb802010, 0x00000000, + 0xc2000000, 0x6fb46000, 0x4779a000, 0x5b744c80, 0x5834000c, 0xca000020, 0xc000491a, 0xcf8000f8, + 0x5e200000, 0x8400046a, 0xc2000000, 0xdf610048, 0x5e6001e8, 0x8800ffe8, 0xc2000002, 0xc2400466, + 0xc2a00000, 0x5aa80000, 0xc0001006, 0xce0000f8, 0xc0001008, 0xce4000f8, 0xc000100a, 0xce8000f8, + 0x990055b8, 0xc1a0fffe, 0xc0000824, 0xc9840060, 0xc0004934, 0xca4000f8, 0xc2000000, 0xc2800002, + 0x990055f8, 0xda9800f8, 0xc61400f8, 0xc65800f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, + 0x990056e0, 0xc000491a, 0xc94000f8, 0x00000000, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, + 0xc0004922, 0xca001118, 0xc3c00000, 0xc3800000, 0xc0004930, 0xce023118, 0xc0004932, 0xcbc000d8, + 0xc2800000, 0xc000491e, 0xcfc000f8, 0xc0004862, 0xca800060, 0xc3a0001a, 0x5bb94000, 0xc6b80060, + 0xc000491c, 0xcf8000f8, 0x99005950, 0xc000491c, 0xc1400000, 0xc9420048, 0x00000000, 0x00000000, + 0x00000000, 0xa8e2ffe8, 0xc2000000, 0xc1220002, 0xd90c00f8, 0xdf600038, 0x5e600080, 0x8400fff2, + 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000, 0x00000000, 0x99005b78, 0xda1800f8, + 0xda5800f9, 0x00000000, 0xc2000000, 0xdf610048, 0x5e6001fe, 0x8800ffe8, 0xc0004916, 0xca8000f8, + 0xc2c00000, 0xdfec0048, 0xc2400000, 0x466d2000, 0x8400004a, 0x5ea80000, 0x8400003a, 0xc2600002, + 0x990062f0, 0xc000482e, 0xc94000f8, 0xc1800002, 0x80000030, 0xc2600000, 0x990062f0, 0xc000482c, + 0xc94000f8, 0xc1800002, 0xc2000068, 0xc6240078, 0xc0004930, 0xce400080, 0xc000491a, 0xc98000f8, + 0xc0004862, 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x990059d8, 0xd95800f8, 0xd99800f9, + 0xd9d400f8, 0x99005950, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xdf600038, 0x5e600080, + 0x8400ffea, 0x00000000, 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000, 0x00000000, + 0x99005b78, 0xda1800f8, 0xda5800f9, 0x00000000, 0x800010e8, 0x00000000, 0x990062f0, 0xc000482a, + 0xc94000f8, 0xc1800002, 0x800010b8, 0xc0004938, 0xcbc000f8, 0x00000000, 0x00000000, 0x6ff88000, + 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x58380008, 0xca0000f8, 0x00000000, 0x00000000, 0xa6000382, + 0x00000000, 0xc0004938, 0xcbc000f8, 0xc3000000, 0x00000000, 0x6ff88000, 0x6fd44000, 0x4395c000, + 0x5bb84a00, 0x58380000, 0xcb002010, 0xc2000000, 0x58380008, 0xca020078, 0x5838000c, 0xcac000f8, + 0x5838000e, 0xca4000f8, 0xc000491a, 0xcf0000f8, 0xc0004930, 0xcec000f8, 0xc000493c, 0xce0000f8, + 0xc0004932, 0xce4000f8, 0x5e200000, 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0x00000000, 0xc9c000f8, 0xc0004930, 0xcd4000f8, 0xc0004932, + 0xcdc000f8, 0x59980004, 0xc1c20020, 0xb59c0018, 0x00000000, 0xc1800000, 0xdd9c00f9, 0x581c000a, + 0xcd800078, 0x581c000c, 0xc1800000, 0xc9800020, 0xc1c00002, 0xdd9400f8, 0x69d4e000, 0x5d980002, + 0xcd800020, 0xc0004924, 0xc98000f8, 0x00000000, 0x9d000000, 0x00000000, 0x719cc000, 0xcd8000f8, + 0xc000492a, 0xc94000f8, 0xc1c00002, 0x69d8e000, 0x7dc0c000, 0x7558a000, 0xcd4000f8, 0xc000492c, + 0xc94000f8, 0xdd8000f9, 0x58000032, 0x755ca000, 0x84000090, 0xc94000f9, 0xc98000f8, 0xdd8000f9, + 0x5800000c, 0x00000000, 0xcd4000f9, 0xcd8000f8, 0xc000492c, 0xc94000f8, 0xc000492a, 0xc98000f8, + 0x715ca000, 0xc000492c, 0xcd4000f8, 0x719cc000, 0xc000492a, 0xcd8000f8, 0x9d000000, 0x00000000, + 0x00000000, 0x00000000, 0xc0004862, 0xc98000f8, 0x00000000, 0xc1c00200, 0x4194c000, 0x459ce000, + 0x88000012, 0xc5d800f8, 0xc0004862, 0xcd8000f8, 0xc0001406, 0xc98000f8, 0xc1c00002, 0x9d000000, + 0xc5d80a00, 0xc5581048, 0xcd8000f8, 0xc0004930, 0xc98000f8, 0xc0004932, 0xc9c000f8, 0xc140000e, + 0xc5581c18, 0xdd9400f8, 0xc0007800, 0x40140000, 0x5d407a00, 0x88000012, 0x5c000200, 0xcd8000f8, + 0x58000002, 0x5d407a00, 0x88000012, 0x5c000200, 0xcdc000f8, 0xdd5400f8, 0xc1c00000, 0x58140006, + 0xc9c20078, 0xc1800000, 0x58140000, 0xc98000d8, 0x6ddc2000, 0xc000491e, 0x41d8e000, 0xcdc000f8, + 0xdd9800f8, 0xc1c00022, 0xc5d80d70, 0xdd9400f9, 0xc5581c18, 0xc000491c, 0xcd8000f8, 0xdd5400f8, + 0xc1c00000, 0x58140006, 0xc9c20078, 0xc1800000, 0x58140004, 0xc9820078, 0x00000000, 0x59dc0002, + 0x45d8c000, 0x84000010, 0xc1c00000, 0x9d000000, 0x58140006, 0xc5d81078, 0xcd821078, 0xc0004860, + 0xc94000f8, 0xc1820080, 0xc1d00002, 0x58147700, 0xd58000f8, 0x58000002, 0xd58000f9, 0x59540004, + 0xb5580018, 0xc0004860, 0xc1400000, 0xcd4000f8, 0xdd9800f9, 0x9d000000, 0xdd9400f8, 0xc0001404, + 0xcdc10800, 0xc1c00000, 0xc1800200, 0x5d980004, 0xdf5d0048, 0x459ca000, 0x8800fff2, 0xdd8000f9, + 0x5800000c, 0x00000000, 0xc94000f9, 0xc98000f8, 0xc1c00002, 0xc5d43f00, 0xc5d81e00, 0xc0004862, + 0xc9c000f8, 0x00000000, 0x00000000, 0x581c7800, 0x5dc07a00, 0x88000012, 0x5c000200, 0xcd4000f8, + 0x58000002, 0x5dc07a00, 0x88000012, 0x5c000200, 0xcd8000f8, 0xc0004862, 0xc9c000f8, 0x00000000, + 0xc15004c0, 0xc5d40060, 0xdd9c00f8, 0xc5d41c18, 0xc1c00000, 0xdd8000f9, 0x58000030, 0xc9c00078, + 0xdd8000f9, 0x58000002, 0xc98000f8, 0x6ddc2000, 0xc000491c, 0x41d8e000, 0xcd4000f9, 0xcdc000f8, + 0xdd9400f9, 0xc1c00000, 0x58140030, 0xc9c00078, 0xc1800000, 0x58140006, 0xc9820078, 0x00000000, + 0x59dc0002, 0x45d8c000, 0x84000010, 0xc1c00000, 0x9d000000, 0x58140030, 0xc5d80078, 0xcd800078, + 0xc1c00000, 0xdf5c0038, 0x5ddc0080, 0x8400ffea, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, + 0x00000000, 0xc160fffe, 0xc0000a10, 0xc9440060, 0xc1a0fffe, 0x59983008, 0xc000100c, 0xcd4000f8, + 0xc000100e, 0xcd8000f8, 0xc0004964, 0xc98000f8, 0x00000000, 0xc170000a, 0x7158a000, 0x6c988000, + 0x4588c000, 0x4588c000, 0x59980004, 0xc5940270, 0xc0001010, 0xcd4000f8, 0xc0004946, 0xc94000f8, + 0x00000000, 0x00000000, 0x6d58a000, 0x6d5c4000, 0x459cc000, 0x4594c000, 0xc000494a, 0xc94000f8, + 0xc0004948, 0xc9c000f8, 0x4194c000, 0xc1400012, 0xc55c1818, 0x9d000000, 0xc59c0268, 0xc0001012, + 0xcdc000f8, 0xc1400000, 0x58000012, 0xc9410038, 0xc0004950, 0xc9c000f8, 0xc55800f8, 0xc5940838, + 0xc5581078, 0xd99400f8, 0xc000493c, 0xc94000f8, 0xc0004954, 0xc98000f8, 0x59dc00a8, 0x45d4e000, + 0x41d8e000, 0x5d5c0030, 0x88000010, 0xc1c00030, 0xc1800000, 0xc5d84028, 0xc1400000, 0xc5d40008, + 0x5dd40002, 0x84000072, 0x5dd40004, 0x8400009a, 0x5dd40006, 0x840000c2, 0x5dd80026, 0x840000ea, + 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd4000f8, 0x59980002, 0x8000ffc0, 0xdd5400f8, + 0xdd8000f9, 0x58000008, 0x40180000, 0xcd4000b8, 0x59980002, 0x8000ff88, 0xdd5400f8, 0xdd8000f9, + 0x58000008, 0x40180000, 0xcd400078, 0x59980002, 0x8000ff50, 0xdd5400f8, 0xdd8000f9, 0x58000008, + 0x40180000, 0xcd400038, 0x59980002, 0x8000ff18, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, + 0x00000000, 0x58000012, 0xc94000f8, 0xc0004954, 0xc9c000f8, 0xc0004950, 0xc9400078, 0xdd8000f9, + 0x58000028, 0x5d9c0000, 0x84000052, 0x5d9c0002, 0x84000052, 0x5d9c0004, 0x8400006a, 0xc55b0038, + 0xc55c08b8, 0xcd800039, 0xcdc108b8, 0x80000060, 0xcd4000f8, 0x80000050, 0xc55900b8, 0xc55c1838, + 0xcd8000b9, 0xcdc31838, 0x80000028, 0xc55a0078, 0xc55c1078, 0xcd800079, 0xcdc21078, 0x9d000000, + 0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6994e018, 0x61c0c008, 0x4194a000, 0x5d940040, + 0x88000012, 0xc59400f8, 0x9d000000, 0xcd4000f8, 0x00000000, 0x00000000, 0x9d000000, 0x4158a000, + 0xcd4000f8, 0x00000000, +}; + +static unsigned int firmware_binary_data[] = { +}; + + +#endif // IFXMIPS_ATM_FW_AR9_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_ar9_retx.h b/package/ltq-dsl/src/ifxmips_atm_fw_ar9_retx.h new file mode 100644 index 0000000000..51e4f9c6c9 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_ar9_retx.h @@ -0,0 +1,611 @@ +#ifndef IFXMIPS_ATM_FW_AR9_H +#define IFXMIPS_ATM_FW_AR9_H + + +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_ar9.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 22 OCT 2007 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PP32 Firmware) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 22 OCT 2007 Xu Liang Initiate Version, v00.01 +*******************************************************************************/ + + +#define VER_IN_FIRMWARE 1 + +#define ATM_FW_VER_MAJOR 0 +#define ATM_FW_VER_MINOR 15 + + +static unsigned int firmware_binary_code[] = { + 0x800004B8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFE0, 0x00000000, 0x00000000, 0x00000000, + 0xC1000002, 0xD90C00F8, 0xC2000002, 0xDA0800F9, 0xC0001B50, 0x8C100000, 0x00000000, 0x00000000, + 0x00000000, 0xC2000000, 0xDA0800F9, 0x80006030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80006008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC1001DA6, 0x8D3C0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80005F08, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400000, 0xC0004840, 0xC88400F8, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400002, 0xC0004840, 0xC88400F8, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC3C00004, 0xDBC800F9, 0xC10C0002, 0xD90C00F8, 0x8000FEE0, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC10E0002, 0xD90C00F8, 0xC0004808, 0xC84000F8, 0xC2001B4C, 0x8E100000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481, + 0x00000000, 0x00000000, 0x00000000, 0xC3E0A252, 0x5BFC001E, 0xC0004002, 0xCFC000F8, 0xC3C00000, + 0xDBC800F9, 0xC1400008, 0xC1900000, 0x71588000, 0x14100100, 0xC140000A, 0xC1900002, 0x71588000, + 0x14100100, 0xC140000C, 0xC1900004, 0x71588000, 0x14100100, 0xC1400004, 0xC1900006, 0x71588000, + 0x14100100, 0xC1400006, 0xC1900008, 0x71588000, 0x14100100, 0xC140000E, 0xC190000A, 0x71588000, + 0x14100100, 0xC1400000, 0xC190000C, 0x71588000, 0x14100100, 0xC1400002, 0xC190000E, 0x71588000, + 0x14100100, 0xC0400000, 0xC11C0000, 0xC000082C, 0xCD05CE00, 0xC11C0002, 0xC000082C, 0xCD05CE00, + 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD05CE00, 0xC0000824, 0x00000000, 0xCBC000F9, 0xCB8000F9, + 0xCB4000F9, 0xCB0000F8, 0xC0004878, 0x5BFC4000, 0xCFC000F9, 0x5BB84000, 0xCF8000F9, 0x5B744000, + 0xCF4000F9, 0x5B304000, 0xCF0000F8, 0xC0000A10, 0x00000000, 0xCBC000F9, 0xCB8000F8, 0xC0004874, + 0x5BFC4000, 0xCFC000F9, 0x5BB84000, 0xCF8000F8, 0xC30001FE, 0xC000140A, 0xCF0000F8, 0xC3000000, + 0x7F018000, 0xC000042E, 0xCF0000F8, 0xC000040E, 0xCF0000F8, 0xC3C1FFFE, 0xC000490E, 0xCFC00078, + 0xC000492C, 0xCFC00078, 0xC0004924, 0xCFC00038, 0xC0004912, 0xCFC00038, 0xC0004966, 0xCFC00038, + 0xC0004968, 0xCFC00078, 0xC000496A, 0xCFC00078, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, + 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFC8, + 0x00000000, 0xC3C00000, 0xC2800010, 0x6FF86000, 0x47BDC000, 0x5BB84C80, 0xC3400000, 0x58380004, + 0xCB420078, 0x00000000, 0x58380008, 0xCF400078, 0x5BFC0002, 0xB7E8FFB0, 0x00000000, 0xC3C00000, + 0xC2800020, 0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000, + 0x5BB87000, 0x58380008, 0xCF408418, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFB0, 0x00000000, + 0x00000000, 0xC0004816, 0xC3C00000, 0xCBC00078, 0x00000000, 0x00000000, 0xC1000000, 0xD90400F9, + 0xDBC40078, 0xC1000006, 0xD90400F9, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0xC3C00000, + 0xDCFC2000, 0x5FFC0002, 0x00000000, 0x98C08D62, 0xC0004730, 0xC94000F8, 0xC0004732, 0xC0001AF2, + 0xCBC000F8, 0x00000000, 0x00000000, 0xA7C20470, 0xC000474A, 0xCA8000F8, 0x00000000, 0x00000000, + 0x5D280000, 0x8400FFE0, 0x00000000, 0xC121FFFE, 0x5911FEF4, 0x14100000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC2802000, 0x6EA8E010, 0xC0004200, 0xC2400000, 0x7E410000, 0xC1000000, 0xCE4000F9, 0xCE4000F9, + 0xCE4000F9, 0xCE4000F9, 0x5EA80002, 0x8400FFD8, 0xC0004300, 0xC2800200, 0x6EA84010, 0xCE4000F9, + 0xCE0000F9, 0xCE4000F9, 0xCE0000F9, 0xCE4000F9, 0xCE0000F9, 0xCE4000F9, 0xCE0000F9, 0x5EA80002, + 0x8400FFB8, 0xC0004700, 0xC2800200, 0x6EA8E010, 0xCE4000F9, 0xCE4000F9, 0xCE4000F9, 0xCE4000F9, + 0x5EA80002, 0x8400FFD8, 0xC0004740, 0xCE4000F8, 0xC0004742, 0xC1000200, 0x5D100002, 0xCD0000F8, + 0xC0004744, 0xCE4000F8, 0xC0004746, 0xCE4000F8, 0xC0004748, 0xCE4000F8, 0xC000474A, 0xCE4000F8, + 0xC000474C, 0xC1000002, 0xCD0000F8, 0xC000474E, 0xCE4000F8, 0xC0004750, 0xCE4000F8, 0xC0004752, + 0xCE4000F8, 0xC0004754, 0xCE4000F8, 0xC0400000, 0xC11C0000, 0xC000082C, 0xCD05CE00, 0xC0000838, + 0xCE4000F8, 0xC0000818, 0xCE4000F8, 0xC0000820, 0xCE4000F8, 0xC2804840, 0xC240485A, 0x98C086B0, + 0xC68000F8, 0xC65400F8, 0xC1800000, 0xC11C0002, 0xC000082C, 0xCD05CE00, 0x00000000, 0xC121FFFE, + 0x5911FE54, 0x14100000, 0xC0000A10, 0xCB8000F8, 0xC0000A12, 0xCB4000F8, 0xC0000A14, 0xCB0000F8, + 0xC0000A16, 0xCAC000F8, 0xC0000040, 0xC2800000, 0xCE800000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC2800002, + 0xCE800000, 0xC0000A10, 0xCF8000F8, 0xC0000A12, 0xCF4000F8, 0xC0000A14, 0xCF0000F8, 0xC0000A16, + 0xCEC000F8, 0xC1000000, 0xC00048A0, 0xCD0000F8, 0xC00048A2, 0xCD0000F8, 0xC0001AF2, 0xC1000000, + 0xCD002100, 0x80001038, 0x00000000, 0xC3C00000, 0xDCFC2000, 0x5FFC0002, 0x00000000, 0x98C08D62, + 0xC0004730, 0xC94000F8, 0xC0004732, 0x800033D8, 0x00000000, 0xC3C00000, 0xDCFC2000, 0x5FFC0002, + 0x00000000, 0x98C08D62, 0xC0004730, 0xC94000F8, 0xC0004732, 0xC0004810, 0xC90000F8, 0xC000474A, + 0xC94000F8, 0xA50007E8, 0x00000000, 0x5D140002, 0x840007D2, 0xC1000000, 0xC000484A, 0xC90000F8, + 0xC0004740, 0xC84000F8, 0x5D100000, 0x84000798, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FEF4, + 0x14100000, 0xC0004744, 0xC88000F8, 0xC0001AF0, 0xC3000000, 0x58000002, 0xCB010038, 0x6C7C2000, + 0x5BFC4300, 0x98C08A88, 0xC1400000, 0xC4540020, 0x6C40A010, 0x5D240002, 0x8400021A, 0x00000000, + 0xC0004742, 0xCA8000F8, 0x00000000, 0x00000000, 0x59280002, 0x6D130000, 0x6D130010, 0x45048000, + 0x84000692, 0x00000000, 0x98C08870, 0xC45400F8, 0xC69800F8, 0xC241FFFE, 0xC67400F8, 0x5D35FFFE, + 0x84000652, 0x47448000, 0x84000642, 0xC1000000, 0x6F502000, 0xC0004300, 0x40100000, 0xC1400000, + 0x58000000, 0xC9410038, 0xC1800000, 0xC0004814, 0xC9820038, 0x4714A000, 0xC10001FE, 0x4150A004, + 0x45588000, 0x880005CA, 0x4744C000, 0xC1000200, 0x4190C004, 0xC000473E, 0xC90000F8, 0x00000000, + 0x00000000, 0x41188000, 0xCD0000F8, 0xC000471C, 0xC90000F8, 0x00000000, 0x00000000, 0x41188000, + 0xCD0000F8, 0x98C087E8, 0xC45400F8, 0x6C58A010, 0xC0004700, 0x58440002, 0x6C470000, 0x6C470010, + 0x44748000, 0x8400FFC0, 0xC74400F8, 0xC0004740, 0xCC4000F8, 0xC0800000, 0xC0004744, 0xCC8000F8, + 0x800004D0, 0xC1000000, 0x583C0000, 0xC9000038, 0x00000000, 0x00000000, 0x44908000, 0x88000280, + 0xC1400000, 0x583C0000, 0xC9410038, 0xC1800000, 0xC0004814, 0xC9800038, 0x4714A000, 0xC10001FE, + 0x4150A004, 0x45588000, 0x88000442, 0xC3800000, 0x583C0002, 0xCB820078, 0xC1000000, 0x583C0002, + 0xC9000078, 0x00000000, 0x00000000, 0x47908000, 0x8400024A, 0xC0400002, 0xC0800000, 0xC3C00000, + 0xC000481A, 0xC80000F8, 0x6F908000, 0x45388000, 0x45388000, 0x4011E000, 0xC000491E, 0xCFC000F8, + 0xC3400000, 0xC0004878, 0xC80400F8, 0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCAC000F8, + 0xC43000F8, 0x00000000, 0xC7340060, 0xC1000002, 0xC5341B00, 0xC100001C, 0xC5341048, 0xC100000C, + 0xC5340D10, 0xC000491C, 0xCF4000F8, 0xC3000000, 0xDF700038, 0x5D300080, 0x8800FFE8, 0xC000474A, + 0xC1000002, 0xCD0000F8, 0xC000491C, 0xCB4000F8, 0xC000491E, 0xCBC000F8, 0x99007F18, 0xDB5800F8, + 0xDBD800F9, 0x00000000, 0xC1400000, 0xC794A030, 0xC1800000, 0xC7980020, 0x58144200, 0xC9C000F8, + 0xC1210000, 0x69188010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x80000228, 0x00000000, 0xC1000000, + 0x583C0000, 0xC903E000, 0x00000000, 0x00000000, 0x5D100000, 0x84000042, 0xC0004734, 0xC90000F8, + 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x800000C0, 0xC1400000, 0x583C0000, 0xC9410038, + 0xC1800000, 0xC0004814, 0xC9820038, 0x4714A000, 0xC10001FE, 0x4150A004, 0x45588000, 0x8800015A, + 0xC000473E, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0xC000471C, 0xC90000F8, + 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0xC3800000, 0x583C0002, 0xCB820078, 0x00000000, + 0x00000000, 0x5D39FFFE, 0x84000062, 0xC1400000, 0xC794A030, 0xC1800000, 0xC7980020, 0x58144200, + 0xC9C000F8, 0xC1210000, 0x69188010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x98C087E8, 0xC45400F8, + 0x6C58A010, 0xC0004700, 0x58440002, 0x6C470000, 0x6C470010, 0xC0004740, 0xCC4000F8, 0xC0800000, + 0xC0004744, 0xCC8000F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x8000F288, 0x00000000, + 0x00000000, 0x98C086F0, 0xC0004748, 0xC98000F8, 0xC2000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xC1400000, 0xC7D4A030, 0xC1800000, 0xC7D80020, 0x58144200, + 0xC9C000F8, 0xC1210000, 0x69188010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x98C087E8, 0xC7D400F8, 0x6FD8A010, 0xC0004700, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x98C08870, 0xC7D400F8, 0xC79800F8, 0xC241FFFE, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x98C08A88, 0xC1400000, 0xC7D40020, 0x6FC0A010, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x98C08AB8, 0xC1400000, 0xC7D40020, 0x6FC0A010, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x98C08AF0, 0xC7D400F8, 0xC0004740, 0xC9C000F8, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 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0xCDC000F8, 0xC0004862, 0xC9C000F8, 0x00000000, 0x00000000, 0xD9D800F9, + 0xC0007800, 0x401C0000, 0x5DC07A00, 0x88000012, 0x5C000200, 0xCD8000F8, 0xC1F0000A, 0x715CA000, + 0xDD9800F8, 0xDD9C00F9, 0x41D8E000, 0xC5D40260, 0xC0001010, 0xCD4000F8, 0x6C9C8000, 0x45C8E000, + 0x45C8E000, 0x59DC0004, 0xC1601260, 0xC5D40260, 0x9D000000, 0xC0001012, 0xCD4000F8, 0x00000000, + 0x00000000, 0xD95800F8, 0x6D586000, 0x4594C000, 0x59984C80, 0xD99800F9, 0x5818000A, 0xC1800000, + 0xC9800078, 0xC0006E00, 0x6D5CA000, 0x401C0000, 0x40180000, 0xC94000F8, 0x58000002, 0x00000000, + 0xC9C000F8, 0xC0004930, 0xCD4000F8, 0xC0004932, 0xCDC000F8, 0x59980004, 0xC1C20020, 0xB59C0018, + 0x00000000, 0xC1800000, 0xDD9C00F9, 0x581C000A, 0xCD800078, 0x581C000C, 0xC1800000, 0xC9800020, + 0xC1C00002, 0xDD9400F8, 0x69D4E000, 0x5D980002, 0xCD800020, 0xC0004924, 0xC98000F8, 0x00000000, + 0x9D000000, 0x00000000, 0x719CC000, 0xCD8000F8, 0xC000492A, 0xC94000F8, 0xC1C00002, 0x69D8E000, + 0x7DC0C000, 0x7558A000, 0xCD4000F8, 0xC000492C, 0xC94000F8, 0xDD8000F9, 0x58000032, 0x755CA000, + 0x84000090, 0xC94000F9, 0xC98000F8, 0xDD8000F9, 0x5800000C, 0x00000000, 0xCD4000F9, 0xCD8000F8, + 0xC000492C, 0xC94000F8, 0xC000492A, 0xC98000F8, 0x715CA000, 0xC000492C, 0xCD4000F8, 0x719CC000, + 0xC000492A, 0xCD8000F8, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC0004862, 0xC98000F8, + 0x00000000, 0xC1C00200, 0x4194C000, 0x459CE000, 0x88000012, 0xC5D800F8, 0xC0004862, 0xCD8000F8, + 0xC0001406, 0xC98000F8, 0xC1C00002, 0x9D000000, 0xC5D80A00, 0xC5581048, 0xCD8000F8, 0xC0004930, + 0xC98000F8, 0xC0004932, 0xC9C000F8, 0xC140000E, 0xC5581C18, 0xDD9400F8, 0xC0007800, 0x40140000, + 0x5D407A00, 0x88000012, 0x5C000200, 0xCD8000F8, 0x58000002, 0x5D407A00, 0x88000012, 0x5C000200, + 0xCDC000F8, 0xDD5400F8, 0xC1C00000, 0x58140006, 0xC9C20078, 0xC1800000, 0x58140000, 0xC98000D8, + 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC000F8, 0xDD9800F8, 0xC1C00022, 0xC5D80D70, 0xDD9400F9, + 0xC5581C18, 0xC000491C, 0xCD8000F8, 0xDD5400F8, 0xC1C00000, 0x58140006, 0xC9C20078, 0xC1800000, + 0x58140004, 0xC9820078, 0x00000000, 0x59DC0002, 0x45D8C000, 0x84000010, 0xC1C00000, 0x9D000000, + 0x58140006, 0xC5D81078, 0xCD821078, 0xC0004860, 0xC94000F8, 0xC1820080, 0xC1D00002, 0x58147700, + 0xD58000F8, 0x58000002, 0xD58000F9, 0x59540004, 0xB5580018, 0xC0004860, 0xC1400000, 0xCD4000F8, + 0xDD9800F9, 0x9D000000, 0xDD9400F8, 0xC0001404, 0xCDC10800, 0xC1C00000, 0xC1800200, 0x5D980004, + 0xDF5D0048, 0x459CA000, 0x8800FFF2, 0xDD8000F9, 0x5800000C, 0x00000000, 0xC94000F9, 0xC98000F8, + 0xC1C00002, 0xC5D43F00, 0xC5D81E00, 0xC0004862, 0xC9C000F8, 0x00000000, 0x00000000, 0x581C7800, + 0x5DC07A00, 0x88000012, 0x5C000200, 0xCD4000F8, 0x58000002, 0x5DC07A00, 0x88000012, 0x5C000200, + 0xCD8000F8, 0xC0004862, 0xC9C000F8, 0x00000000, 0xC15004C0, 0xC5D40060, 0xDD9C00F8, 0xC5D41C18, + 0xC1C00000, 0xDD8000F9, 0x58000030, 0xC9C00078, 0xDD8000F9, 0x58000002, 0xC98000F8, 0x6DDC2000, + 0xC000491C, 0x41D8E000, 0xCD4000F9, 0xCDC000F8, 0xDD9400F9, 0xC1C00000, 0x58140030, 0xC9C00078, + 0xC1800000, 0x58140006, 0xC9820078, 0x00000000, 0x59DC0002, 0x45D8C000, 0x84000010, 0xC1C00000, + 0x9D000000, 0x58140030, 0xC5D80078, 0xCD800078, 0xC1C00000, 0xDF5C0038, 0x5DDC0080, 0x8400FFEA, + 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC160FFFE, 0xC0000A10, 0xC9440060, + 0xC1A0FFFE, 0x59983008, 0xC000100C, 0xCD4000F8, 0xC000100E, 0xCD8000F8, 0xC0004964, 0xC98000F8, + 0x00000000, 0xC170000A, 0x7158A000, 0x6C988000, 0x4588C000, 0x4588C000, 0x59980004, 0xC5940270, + 0xC0001010, 0xCD4000F8, 0xC0004946, 0xC94000F8, 0x00000000, 0x00000000, 0x6D58A000, 0x6D5C4000, + 0x459CC000, 0x4594C000, 0xC000494A, 0xC94000F8, 0xC0004948, 0xC9C000F8, 0x4194C000, 0xC1400012, + 0xC55C1818, 0x9D000000, 0xC59C0268, 0xC0001012, 0xCDC000F8, 0xC1400000, 0x58000012, 0xC9410038, + 0xC0004950, 0xC9C000F8, 0xC55800F8, 0xC5940838, 0xC5581078, 0xD99400F8, 0xC000493C, 0xC94000F8, + 0xC0004954, 0xC98000F8, 0x59DC00A8, 0x45D4E000, 0x41D8E000, 0x5D5C0030, 0x88000010, 0xC1C00030, + 0xC1800000, 0xC5D84028, 0xC1400000, 0xC5D40008, 0x5DD40002, 0x84000072, 0x5DD40004, 0x8400009A, + 0x5DD40006, 0x840000C2, 0x5DD80026, 0x840000EA, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, + 0xCD4000F8, 0x59980002, 0x8000FFC0, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD4000B8, + 0x59980002, 0x8000FF88, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400078, 0x59980002, + 0x8000FF50, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400038, 0x59980002, 0x8000FF18, + 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012, 0xC94000F8, 0xC0004954, + 0xC9C000F8, 0xC0004950, 0xC9400078, 0xDD8000F9, 0x58000028, 0x5D9C0000, 0x84000052, 0x5D9C0002, + 0x84000052, 0x5D9C0004, 0x8400006A, 0xC55B0038, 0xC55C08B8, 0xCD800039, 0xCDC108B8, 0x80000060, + 0xCD4000F8, 0x80000050, 0xC55900B8, 0xC55C1838, 0xCD8000B9, 0xCDC31838, 0x80000028, 0xC55A0078, + 0xC55C1078, 0xCD800079, 0xCDC21078, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x59540002, + 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x88000012, 0xC59400F8, 0x9D000000, 0xCD4000F8, + 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD4000F8, 0x00000000, 0xCD8000F9, 0x45408000, + 0x8800FFF0, 0x00000000, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004810, 0xCA010038, + 0xC241FFFE, 0xC1400000, 0x46148000, 0x00000000, 0x9CC00006, 0xC0004200, 0x40180000, 0xC9C000F8, + 0x00000000, 0x00000000, 0x61C08010, 0x8400005A, 0xC2400002, 0x6A512000, 0x71E4E000, 0xCDC000F8, + 0xC0004748, 0xCD8000F8, 0x9CC00000, 0x6D98A000, 0x5998003E, 0x45912000, 0x59540002, 0x59980002, + 0x46188000, 0xC1000000, 0xC51800FE, 0x8000FF38, 0x00000000, 0x40180000, 0xC9C000F8, 0xC2000000, + 0xC5600020, 0xC1210000, 0x69208010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x6D542000, 0x58144300, + 0xC1000000, 0xCD0000F9, 0x9CC00000, 0xC121FFFE, 0x5911FFFE, 0xCD0000F9, 0x79588000, 0x6D10A010, + 0x5D100000, 0x840000C0, 0x45948000, 0x880000B0, 0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700, + 0x40140000, 0xCA0000F8, 0x00000000, 0x00000000, 0x6A110000, 0x6A110010, 0x62008018, 0x84000032, + 0x00000000, 0x9CC00000, 0x6D54A000, 0x5954003E, 0x45512000, 0x59540002, 0x6D57A000, 0x6D57A010, + 0x6D54A000, 0x6D936000, 0x6D136010, 0xC1E10000, 0x69D0E010, 0x5DDC0002, 0x7DC0E000, 0x6D98A010, + 0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700, 0x40140000, 0xCA0000F8, 0x00000000, 0x00000000, + 0x6A110000, 0x6A110010, 0x45588000, 0x00000000, 0x761D0002, 0x62008018, 0x84000032, 0x00000000, + 0x9CC00000, 0x6D54A000, 0x5954003E, 0x45512000, 0x45588000, 0x00000000, 0x9CC00002, 0x59540002, + 0x6D57A000, 0x6D57A010, 0xC0004700, 0x40140000, 0xCA0000F8, 0x8000FF68, 0x00000000, 0x00000000, + 0x00000000, 0x58004700, 0xC98000F8, 0x9CC00000, 0x00000000, 0x6994C000, 0x6DA7E010, 0x58004700, + 0xC98000F8, 0xC1210000, 0x9CC00000, 0x69148010, 0x7190C000, 0xCD8000F8, 0xC1000000, 0xC0004810, + 0xC9020038, 0x00000000, 0x00000000, 0x45D0C000, 0x88000062, 0xC2400002, 0x45588000, 0xC1000000, + 0xC52400FC, 0x45D48000, 0xC1000000, 0xC52400FE, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, + 0x59980200, 0xC2400000, 0x455C8000, 0xC1000002, 0xC52400FC, 0x45948000, 0xC1000002, 0xC52400FE, + 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004740, 0xC9C000F8, 0x59180002, 0x6D130000, + 0x6D130010, 0x451C8000, 0xC2400000, 0x9CC00002, 0x00000000, 0x00000000, 0x459C8000, 0x88000062, + 0xC2400002, 0x455C8000, 0xC1000000, 0xC52400FC, 0x45948000, 0xC1000000, 0xC52400FC, 0x9CC00000, + 0x00000000, 0x00000000, 0x00000000, 0xC2400000, 0x45588000, 0xC1000002, 0xC52400FE, 0x45D48000, + 0xC1000002, 0xC52400FE, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6D570000, + 0x6D570010, 0x45588000, 0x6D402000, 0x9CC00002, 0x58004300, 0x58000000, 0xC13C0002, 0xCD03DE00, + 0x8000FFB0, 0x00000000, 0x00000000, 0x00000000, 0xC1020002, 0xD90C00F8, 0xC98000F8, 0x59540002, + 0xC0004730, 0xCD4000F8, 0x5D980002, 0x00000000, 0x80000036, 0x00000000, 0x9CC00000, 0xC0004732, + 0xCD8000F8, 0x00000000, 0xC0004734, 0xC9C000F8, 0xC1800000, 0xC0004816, 0xC9820078, 0xC0004738, + 0xCDC000F8, 0xC1C00000, 0xC0004734, 0x9CC00000, 0xCDC000F8, 0xC0004732, 0xCD8000F8, +}; + +static unsigned int firmware_binary_data[] = { +}; + + +#endif // IFXMIPS_ATM_FW_AR9_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_danube.h b/package/ltq-dsl/src/ifxmips_atm_fw_danube.h index c36c96845c..fff0d31e5e 100644 --- a/package/ltq-dsl/src/ifxmips_atm_fw_danube.h +++ b/package/ltq-dsl/src/ifxmips_atm_fw_danube.h @@ -27,28 +27,30 @@ *******************************************************************************/ +#define VER_IN_FIRMWARE 1 + #define ATM_FW_VER_MAJOR 0 -#define ATM_FW_VER_MINOR 1 +#define ATM_FW_VER_MINOR 17 static unsigned int firmware_binary_code[] = { 0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000, - 0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004710, 0xC2000000, 0xDA080001, 0x80003D98, + 0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004968, 0xC2000000, 0xDA080001, 0x80003FD0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x80003D50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80003F88, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x80004F18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80005160, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x80003C50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80003E88, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC0400000, 0xC0004840, 0xC8840000, 0x800043D0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400000, 0xC0004840, 0xC8840000, 0x80004628, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC0400002, 0xC0004840, 0xC8840000, 0x80004350, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400002, 0xC0004840, 0xC8840000, 0x800045A8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x80004380, 0x00000000, 0x00000000, 0x00000000, + 0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x800045D8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481, 0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000, @@ -63,363 +65,372 @@ static unsigned int firmware_binary_code[] = { 0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000, 0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C, 0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968, - 0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000, - 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FFA8, 0x00000000, - 0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0xC3400000, 0x58380004, 0xCB420080, - 0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0xC3C00000, 0xC2800020, - 0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, - 0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0x00000000, - 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000, - 0x8000FFC8, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, - 0xCB840000, 0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C, - 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A, - 0x00000000, 0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000, - 0x46610000, 0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE, - 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000, - 0x00000000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002, - 0xC000495C, 0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002, - 0xCE440808, 0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000, - 0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, - 0x7BC42000, 0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2, - 0x00000000, 0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000, - 0xC0000A28, 0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960, - 0xCEC40000, 0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600, - 0xCA040000, 0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000, - 0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 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0x5A200002, 0x5E600010, + 0x8400FFF8, 0xC2000000, 0xC0000808, 0xCE040018, 0xC3400000, 0x80000010, 0xC1200002, 0xC0000818, + 0xCD041008, 0x5B740002, 0xC0004858, 0xCF440000, 0x99005590, 0xC0004848, 0xC9440000, 0xC1800000, + 0xC11C0002, 0xC000082C, 0xCD040E08, 0x800005E8, 0x5B740002, 0xC0004858, 0xCF440000, 0xC7800000, + 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, + 0xC0004848, 0xCD440000, 0x58880002, 0xB4980560, 0x00000000, 0xC0800000, 0x80000550, 0xC000487C, + 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCBC00000, 0xC4280000, 0x00000000, 0xA7C00110, + 0xC000484C, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA440020, 0x5A200002, 0xC000484C, 0xCE040000, + 0xB624006A, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, + 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980450, 0x00000000, 0xC0800000, + 0x80000440, 0xC0004854, 0xC1000004, 0xCD040000, 0xC0000820, 0xC2000002, 0xCE040000, 0xC2000000, + 0xC000484C, 0xCE040000, 0xC0004858, 0xCE040000, 0x8000FF10, 0xC0004854, 0xC1000000, 0xCD040000, + 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005590, 0xC0004848, 0xC9440000, 0xC1800000, 0xC1200000, + 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC2000000, 0xC000484C, 0xCE040000, + 0x80000340, 0xC0001AC0, 0xCB840000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000, 0x40080000, + 0xCBC00000, 0xC4280000, 0x00000000, 0x00000000, 0xC6800000, 0xC13C0000, 0xCD001E08, 0xA780022A, + 0x00000000, 0x00000000, 0xA7C001EA, 0x00000000, 0xC0001B00, 0xC2060006, 0xCE040310, 0xA7E801A2, + 0x00000000, 0xC0004850, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA448020, 0x5A200002, 0xC0004850, + 0xCE040000, 0xB624008A, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0001ACC, 0xC2000002, + 0xCE040008, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, + 0xCD440000, 0x58880002, 0xB49801A8, 0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000, + 0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005590, 0xC0004848, 0xC9440000, 0xC1800000, + 0xC2000000, 0xC0000820, 0xCE040000, 0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, + 0xCD040E08, 0xC0004850, 0xCE040000, 0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002, + 0xC0004850, 0xCE040000, 0x8000FE70, 0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000, + 0xC2000002, 0xC0001B00, 0xCE040008, 0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000, + 0xC13C0002, 0xCD001E08, 0xC2020002, 0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002, + 0xC0001B00, 0xCE040208, 0x8000FDE0, 0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000, + 0xC0004848, 0xCB840000, 0xC0000838, 0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000, + 0xC0001ACC, 0xCF040108, 0x47BD8000, 0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B6B0, + 0xC0004840, 0xCC840000, 0x8000F698, 0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBB2, + 0x00000000, 0x5EF40000, 0x8400F6F2, 0x5EF40002, 0x8400F982, 0x5EF40004, 0x8400FB82, 0xC1006CE8, + 0x8000B628, 0x00000000, 0xC0800000, 0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A, + 0xA78000B0, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000, + 0x5B744C80, 0xC2400000, 0x58340004, 0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004, + 0xC6500080, 0xCD000080, 0xC0004914, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, + 0xC0000408, 0xCE000000, 0xA78200B8, 0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, + 0xD90C0000, 0x6FF4A000, 0x6FD44000, 0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, + 0xCA800080, 0xC2000000, 0xC0004900, 0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, + 0x5A7C0020, 0xC2000002, 0x6A250000, 0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B498, + 0x00000000, 0xA4800210, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000, + 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002, + 0x58380008, 0xC7500080, 0xCD000080, 0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C, + 0xCB000028, 0x5A640002, 0x46250000, 0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080, + 0xC2000000, 0x5838000A, 0xCA020080, 0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020, + 0x5A200004, 0x46612000, 0x8400FFF8, 0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966, + 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912, + 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028, + 0xC0004924, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050, + 0xC2400000, 0xC000140E, 0xCA408020, 0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000, + 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004, 0xD9000001, 0xA4840250, 0x00000000, 0xC3C00000, + 0xC000140E, 0xCBC10020, 0xC2800000, 0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, + 0x5BB84E20, 0x5838002E, 0xCA800080, 0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080, + 0x5AA80002, 0x46290000, 0x8400FFF8, 0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002, + 0x5838002E, 0xC7501080, 0xCD001080, 0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, + 0xCE400000, 0xC000492A, 0xCA800000, 0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002, + 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x6ABD4010, 0xA680009A, 0x00000000, 0x58380032, + 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C, 0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, + 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, + 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, + 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880128, 0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, + 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000, 0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, + 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, 0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, + 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000, 0xC2400002, 0x76252000, 0x8400005A, 0x58300000, + 0xCA400000, 0xC2800000, 0x00000000, 0xC6684020, 0xC24C0002, 0xC6A40020, 0xC624C408, 0x58300010, + 0xCA400508, 0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020, + 0xC2020002, 0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, + 0xC1000004, 0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000ED98, 0xDFBC0001, + 0xC000496E, 0x99006298, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, + 0x6F346000, 0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, + 0x5A640002, 0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, + 0xC0004912, 0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, + 0xC000480A, 0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000, + 0x80000020, 0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, + 0x6EF4A000, 0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, + 0x00000000, 0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, + 0x00000000, 0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, + 0xCE400000, 0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, + 0x8000EB08, 0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, + 0xC1C03200, 0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, + 0xC9C00000, 0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, + 0x5C000200, 0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, + 0xC0001010, 0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, + 0x9D000000, 0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, + 0x59984C80, 0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, + 0x40180000, 0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, + 0xCDC00000, 0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, + 0xCD800080, 0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, + 0xCD800028, 0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, + 0xC000492A, 0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, + 0xC9400000, 0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, + 0x5800000C, 0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, + 0x71D4A000, 0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, + 0x00000000, 0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, + 0x8800FFFA, 0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, + 0xC5D80A08, 0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, + 0xC5581C20, 0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, + 0x58000002, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, + 0xC9C20080, 0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, + 0xDD980000, 0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, + 0xC1C00000, 0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, + 0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, + 0xC9400000, 0xC1820080, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, + 0xB558FFF8, 0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, + 0xCDC00808, 0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, + 0x5800000C, 0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, + 0xC9C00000, 0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, + 0x58000002, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, + 0xC15004C0, 0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, + 0xDD800001, 0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, + 0xDD940001, 0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, + 0x59DC0002, 0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, + 0xC1C00000, 0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, + 0x00000000, 0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, + 0xC000100E, 0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, + 0x4498C000, 0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, + 0x00000000, 0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, + 0xC0004948, 0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, + 0xCDC00000, 0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, + 0xC5581080, 0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, + 0x41D8E000, 0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, + 0x5DD40002, 0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, + 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, + 0xDD800001, 0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, + 0x58000008, 0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, + 0x40180000, 0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, + 0x00000000, 0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, + 0x58000028, 0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, + 0xC55C08C0, 0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, + 0xCD8000C1, 0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, + 0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, + 0x8800FFFA, 0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, + 0xCD400000, 0x00000000, }; static unsigned int firmware_binary_data[] = { diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_danube_retx.h b/package/ltq-dsl/src/ifxmips_atm_fw_danube_retx.h new file mode 100644 index 0000000000..1c915dbba1 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_danube_retx.h @@ -0,0 +1,612 @@ +#ifndef IFXMIPS_ATM_FW_DANUBE_H +#define IFXMIPS_ATM_FW_DANUBE_H + + +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_danube.h +** PROJECT : Danube +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PP32 Firmware) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +*******************************************************************************/ + + +#define VER_IN_FIRMWARE 1 + +#define ATM_FW_VER_MAJOR 0 +#define ATM_FW_VER_MINOR 15 + + +static unsigned int firmware_binary_code[] = { + 0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000, + 0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0xC0001B50, 0x8C100000, 0x00000000, 0x00000000, + 0x00000000, 0xC2000000, 0xDA080001, 0x80006018, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80005FF0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC1001DA6, 0x8D3C0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80005EF0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400000, 0xC0004840, 0xC8840000, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400002, 0xC0004840, 0xC8840000, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0xC2001B4C, 0x8E100000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481, + 0x00000000, 0x00000000, 0x00000000, 0xC3E02252, 0x5BFC001E, 0xC0004002, 0xCFC00000, 0xC3C00000, + 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000, 0x15000100, 0xC140000A, 0xC1900002, 0x71948000, + 0x15000100, 0xC140000C, 0xC1900004, 0x71948000, 0x15000100, 0xC1400004, 0xC1900006, 0x71948000, + 0x15000100, 0xC1400006, 0xC1900008, 0x71948000, 0x15000100, 0xC140000E, 0xC190000A, 0x71948000, + 0x15000100, 0xC1400000, 0xC190000C, 0x71948000, 0x15000100, 0xC1400002, 0xC190000E, 0x71948000, + 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, + 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, + 0xCB400001, 0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, + 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0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032, + 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C, 0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, + 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, + 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, + 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100, 0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, + 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000, 0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, + 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, 0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, + 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000, 0xC2400002, 0x76252000, 0x84000032, 0xC24C0002, + 0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508, 0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, + 0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002, 0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, + 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004, 0xD9000001, 0xA48C0028, 0xC2800002, 0xC000484A, + 0xCE800000, 0xC2800000, 0xC000474A, 0xCE800000, 0xC0004846, 0xCE800000, 0xC0001408, 0xCC800000, + 0xC10E0002, 0xD90C0000, 0x8000EA60, 0xDFBC0001, 0xC000496E, 0x99008638, 0xC9400000, 0xC7D80000, + 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000, 0x4735A000, 0x5B744C80, 0x58340008, + 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002, 0xCE400080, 0x58340004, 0xCA000080, + 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912, 0xCA800000, 0xC2400002, 0x6A712000, + 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A, 0xCA000000, 0xC0000408, 0xCA800000, + 0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020, 0xC0004914, 0xCA000000, 0x7E412000, + 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000, 0x6ED44000, 0x4575A000, 0x46F5A000, + 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000, 0xC2000000, 0x5A640002, 0xC6501080, + 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000, 0x5A200002, 0xCE000080, 0xC0004910, + 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, 0xC2000002, 0x6A310000, 0xC000042A, + 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000E7D0, 0x00000000, 0xC4980930, 0x9D000000, + 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200, 0xC55C1078, 0xC000100E, 0x9D000000, + 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000, 0x00000000, 0x00000000, 0xD9D80001, + 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC1F0000A, 0x71D4A000, + 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010, 0xCD400000, 0x6C9C8000, 0x449CE000, + 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000, 0xC0001012, 0xCD400000, 0x00000000, + 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80, 0xD9980001, 0x5818000A, 0xC1800000, + 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000, 0xC9400000, 0x58000002, 0x00000000, + 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000, 0x59980004, 0xC1C20020, 0xB59CFFF8, + 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080, 0x581C000C, 0xC1800000, 0xC9800028, + 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028, 0xC0004924, 0xC9800000, 0x00000000, + 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A, 0xC9400000, 0xC1C00002, 0x69D8E000, + 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000, 0xDD800001, 0x58000032, 0x75D4A000, + 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C, 0x00000000, 0xCD400001, 0xCD800000, + 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000, 0xC000492C, 0xCD400000, 0x71D8C000, + 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC0004862, 0xC9800000, + 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA, 0xC5D80000, 0xC0004862, 0xCD800000, + 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08, 0xC5581050, 0xCD800000, 0xC0004930, + 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20, 0xDD940000, 0xC0007200, 0x40140000, + 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002, 0x5D407400, 0x8800FFFA, 0x5C000200, + 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080, 0xC1800000, 0x58140000, 0xC98000E0, + 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000, 0xC1C00022, 0xC5D80D78, 0xDD940001, + 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080, 0xC1800000, + 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, + 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000, 0xC1820080, 0xC1D00002, 0x58146B00, + 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8, 0xC0004860, 0xC1400000, 0xCD400000, + 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808, 0xC1C00000, 0xC1800200, 0x5D980004, + 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C, 0x00000000, 0xC9400001, 0xC9800000, + 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000, 0x00000000, 0x00000000, 0x581C7200, + 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002, 0x5DC07400, 0x8800FFFA, 0x5C000200, + 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0, 0xC5D40068, 0xDD9C0000, 0xC5D41C20, + 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001, 0x58000002, 0xC9800000, 0x6DDC2000, + 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001, 0xC1C00000, 0x58140030, 0xC9C00080, + 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000, 0x8400FFF8, 0xC1C00000, + 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000, 0xDF5C0040, 0x5DDC0080, 0x8400FFD2, + 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC160FFFE, 0xC0000A10, 0xC9440068, + 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E, 0xCD800000, 0xC0004964, 0xC9800000, + 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000, 0x4498C000, 0x59980004, 0xC5940278, + 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000, 0x00000000, 0x6D58A000, 0x6D5C4000, + 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948, 0xC9C00000, 0x4194C000, 0xC1400012, + 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000, 0xC1400000, 0x58000012, 0xC9410040, + 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080, 0xD9940000, 0xC000493C, 0xC9400000, + 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000, 0x5D5C0030, 0x8800FFF8, 0xC1C00030, + 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002, 0x8400005A, 0x5DD40004, 0x84000082, + 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, + 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD4000C0, + 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD400080, 0x59980002, + 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD400040, 0x59980002, 0x8000FF00, + 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012, 0xC9400000, 0xC0004954, + 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028, 0x5D9C0000, 0x8400003A, 0x5D9C0002, + 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0, 0xCD800041, 0xCDC008C0, 0x80000048, + 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1, 0xCDC01840, 0x80000010, 0xC55A0080, + 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x59540002, + 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA, 0xC5940000, 0x9D000000, 0xCD400000, + 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000, 0x00000000, 0xCD800001, 0x44148000, + 0x8800FFD8, 0x00000000, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004810, 0xCA010040, + 0xC241FFFE, 0xC1400000, 0x45608000, 0x00000000, 0x9CC00006, 0xC0004200, 0x40180000, 0xC9C00000, + 0x00000000, 0x00000000, 0x61C08010, 0x84000042, 0xC2400002, 0x6A512000, 0x725CE000, 0xCDC00000, + 0xC0004748, 0xCD800000, 0x9CC00000, 0x6D98A000, 0x5998003E, 0x45192000, 0x59540002, 0x59980002, + 0x45A08000, 0xC1000000, 0xC5180006, 0x8000FF20, 0x00000000, 0x40180000, 0xC9C00000, 0xC2000000, + 0xC5600028, 0xC1210000, 0x69208010, 0x7D008000, 0x751CE000, 0xCDC00000, 0x6D542000, 0x58144300, + 0xC1000000, 0xCD000001, 0x9CC00000, 0xC121FFFE, 0x5911FFFE, 0xCD000001, 0x79948000, 0x6D10A010, + 0x5D100000, 0x840000A8, 0x45588000, 0x88000098, 0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700, + 0x40140000, 0xCA000000, 0x00000000, 0x00000000, 0x6A110000, 0x6A110010, 0x62008018, 0x8400001A, + 0x00000000, 0x9CC00000, 0x6D54A000, 0x5954003E, 0x45152000, 0x59540002, 0x6D57A000, 0x6D57A010, + 0x6D54A000, 0x6D936000, 0x6D136010, 0xC1E10000, 0x69D0E010, 0x5DDC0002, 0x7DC0E000, 0x6D98A010, + 0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700, 0x40140000, 0xCA000000, 0x00000000, 0x00000000, + 0x6A110000, 0x6A110010, 0x45948000, 0x00000000, 0x75E10002, 0x62008018, 0x8400001A, 0x00000000, + 0x9CC00000, 0x6D54A000, 0x5954003E, 0x45152000, 0x45948000, 0x00000000, 0x9CC00002, 0x59540002, + 0x6D57A000, 0x6D57A010, 0xC0004700, 0x40140000, 0xCA000000, 0x8000FF50, 0x00000000, 0x00000000, + 0x00000000, 0x58004700, 0xC9800000, 0x9CC00000, 0x00000000, 0x6994C000, 0x6DA7E010, 0x58004700, + 0xC9800000, 0xC1210000, 0x9CC00000, 0x69148010, 0x7118C000, 0xCD800000, 0xC1000000, 0xC0004810, + 0xC9020040, 0x00000000, 0x00000000, 0x451CC000, 0x8800004A, 0xC2400002, 0x45948000, 0xC1000000, + 0xC5240004, 0x455C8000, 0xC1000000, 0xC5240006, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, + 0x59980200, 0xC2400000, 0x45D48000, 0xC1000002, 0xC5240004, 0x45588000, 0xC1000002, 0xC5240006, + 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004740, 0xC9C00000, 0x59180002, 0x6D130000, + 0x6D130010, 0x45D08000, 0xC2400000, 0x9CC00002, 0x00000000, 0x00000000, 0x45D88000, 0x8800004A, + 0xC2400002, 0x45D48000, 0xC1000000, 0xC5240004, 0x45588000, 0xC1000000, 0xC5240004, 0x9CC00000, + 0x00000000, 0x00000000, 0x00000000, 0xC2400000, 0x45948000, 0xC1000002, 0xC5240006, 0x455C8000, + 0xC1000002, 0xC5240006, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6D570000, + 0x6D570010, 0x45948000, 0x6D402000, 0x9CC00002, 0x58004300, 0x58000000, 0xC13C0002, 0xCD001E08, + 0x8000FF98, 0x00000000, 0x00000000, 0x00000000, 0xC1020002, 0xD90C0000, 0xC9800000, 0x59540002, + 0xC0004730, 0xCD400000, 0x5D980002, 0x00000000, 0x8000001E, 0x00000000, 0x9CC00000, 0xC0004732, + 0xCD800000, 0x00000000, 0xC0004734, 0xC9C00000, 0xC1800000, 0xC0004816, 0xC9820080, 0xC0004738, + 0xCDC00000, 0xC1C00000, 0xC0004734, 0x9CC00000, 0xCDC00000, 0xC0004732, 0xCD800000, +}; + +static unsigned int firmware_binary_data[] = { +}; + + +#endif // IFXMIPS_ATM_FW_DANUBE_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_regs_amazon_se.h b/package/ltq-dsl/src/ifxmips_atm_fw_regs_amazon_se.h new file mode 100644 index 0000000000..af2b550869 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_regs_amazon_se.h @@ -0,0 +1,30 @@ +#ifndef IFXMIPS_ATM_FW_REGS_AMAZON_SE_H +#define IFXMIPS_ATM_FW_REGS_AMAZON_SE_H + + + +/* + * Host-PPE Communication Data Address Mapping + */ +#define FW_VER_ID SB_BUFFER(0x2001) /* Firmware Version ID */ +#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */ +#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */ +#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */ +#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */ +#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */ +#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */ +#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */ +#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */ +#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20)) +#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7)) +#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i))) +#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2F00 + (i) * 27)) +#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2F01 + (i) * 27)) +#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410)) +#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x3200 + (i))) +#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x3220 + (i))) +#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x3240 + (i))) + + + +#endif // IFXMIPS_ATM_FW_REGS_AMAZON_SE_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_regs_ar9.h b/package/ltq-dsl/src/ifxmips_atm_fw_regs_ar9.h new file mode 100644 index 0000000000..dd010f54f9 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_regs_ar9.h @@ -0,0 +1,172 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_regs_ar9.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (Firmware Registers) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + +#ifndef IFXMIPS_ATM_FW_REGS_AR9_H +#define IFXMIPS_ATM_FW_REGS_AR9_H + + + +/* + * Host-PPE Communication Data Address Mapping + */ +#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001)) +#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */ +#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */ +#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */ +#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */ +#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */ +#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */ +#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */ +#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */ +#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20)) +#define WRX_QUEUE_CONTEXT(i) ((struct wrx_queue_context*) SB_BUFFER(0x2504 + (i) * 20)) +#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7)) +#define WRX_DESC_CONTEXT(i) ((struct wrx_desc_context*) SB_BUFFER(0x2643 + (i) * 7)) +#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i))) +#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x3800 + (i) * 27)) +#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x3801 + (i) * 27)) +#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410)) +#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2010 + (i))) +#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2030 + (i))) +#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2050 + (i))) + +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + + #define RETX_MODE_CFG ((volatile struct Retx_mode_cfg *) SB_BUFFER(0x2408)) + #define RETX_TSYNC_CFG ((volatile struct Retx_Tsync_cfg *) SB_BUFFER(0x2409)) + #define RETX_TD_CFG ((volatile struct Retx_Td_cfg *) SB_BUFFER(0x240A)) + #define RETX_MIB_TIMER_CFG ((volatile struct Retx_MIB_Timer_cfg *) SB_BUFFER(0x240B)) + #define RETX_PLAYOUT_BUFFER_BASE SB_BUFFER(0x240D) + #define RETX_SERVICE_HEADER_CFG SB_BUFFER(0x240E) + #define RETX_MASK_HEADER_CFG SB_BUFFER(0x240F) + + #define RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) PPE_REG_ADDR(0x0D78)) + #define BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AC)) + #define FIRST_BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AE)) + + #define PB_BUFFER_USAGE SB_BUFFER(0x2100) + #define DTU_STAT_INFO ((volatile struct DTU_stat_info *) SB_BUFFER(0x2180)) + #define DTU_VLD_STAT SB_BUFFER(0x2380) + + + //===================================================================== + // retx firmware mib, for debug purpose + // address : 0x2388 - 0x238F + // size : 8 + //===================================================================== + #define URETX_RX_TOTAL_DTU SB_BUFFER(0x2388) + #define URETX_RX_BAD_DTU SB_BUFFER(0x2389) + #define URETX_RX_GOOD_DTU SB_BUFFER(0x238A) + #define URETX_RX_CORRECTED_DTU SB_BUFFER(0x238B) + #define URETX_RX_OUTOFDATE_DTU SB_BUFFER(0x238C) + #define URETX_RX_DUPLICATE_DTU SB_BUFFER(0x238D) + #define URETX_RX_TIMEOUT_DTU SB_BUFFER(0x238E) + + #define URETX_ALPHA_SWITCH_TO_HUNT_TIMES SB_BUFFER(0x238F) + + // cell counter for debug purpose + #define WRX_BC0_CELL_NUM SB_BUFFER(0x23E0) + #define WRX_BC0_DROP_CELL_NUM SB_BUFFER(0x23E1) + #define WRX_BC0_NONRETX_CELL_NUM SB_BUFFER(0x23E2) + #define WRX_BC0_RETX_CELL_NUM SB_BUFFER(0x23E3) + #define WRX_BC0_OUTOFDATE_CELL_NUM SB_BUFFER(0x23E4) + #define WRX_BC0_DIRECTUP_NUM SB_BUFFER(0x23E5) + #define WRX_BC0_PBW_TOTAL_NUM SB_BUFFER(0x23E6) + #define WRX_BC0_PBW_SUCC_NUM SB_BUFFER(0x23E7) + #define WRX_BC0_PBW_FAIL_NUM SB_BUFFER(0x23E8) + #define WRX_BC1_CELL_NUM SB_BUFFER(0x23E9) + + // debug info (interface) + + #define DBG_DTU_INTF_WRPTR SB_BUFFER(0x2390) + #define DBG_INTF_FCW_DUP_CNT SB_BUFFER(0x2391) + #define DBG_INTF_SID_CHANGE_IN_DTU_CNT SB_BUFFER(0x2392) + #define DBG_INTF_LCW_DUP_CNT SB_BUFFER(0x2393) + + #define DBG_RFBI_DONE_INT_CNT SB_BUFFER(0x2394) + #define DBG_DREG_BEG_END SB_BUFFER(0x2395) + #define DBG_RFBI_BC0_INVALID_CNT SB_BUFFER(0x2396) + #define DBG_RFBI_LAST_T SB_BUFFER(0x2397) + + #define DBG_RFBI_INTV0 SB_BUFFER(0x23EE) + #define DBG_RFBI_INTV1 SB_BUFFER(0x23EF) + + #define DBG_INTF_INFO(i) ((volatile struct Retx_adsl_ppe_intf_rec *) SB_BUFFER(0x23F0 + i)) + + // Internal status + #define URetx_curr_time SB_BUFFER(0x2398) + #define URetx_sec_counter SB_BUFFER(0x2399) + #define RxCURR_EFB SB_BUFFER(0x239A) + #define RxDTURetransmittedCNT SB_BUFFER(0x239B) + + //===================================================================== + // standardized MIB counter + // address : 0x239C - 0x239F + // size : 4 + //===================================================================== + #define RxLastEFBCNT SB_BUFFER(0x239C) + #define RxDTUCorrectedCNT SB_BUFFER(0x239D) + #define RxDTUCorruptedCNT SB_BUFFER(0x239E) + #define RxRetxDTUUncorrectedCNT SB_BUFFER(0x239F) + + + //===================================================================== + // General URetx Context + // address : 0x23A0 - 0x23AF + // size : 16 + //===================================================================== + #define NEXT_DTU_SID_OUT SB_BUFFER(0x23A0) + #define LAST_DTU_SID_IN SB_BUFFER(0x23A1) + #define NEXT_CELL_SID_OUT SB_BUFFER(0x23A2) + #define ISR_CELL_ID SB_BUFFER(0x23A3) + #define PB_CELL_SEARCH_IDX SB_BUFFER(0x23A4) + #define PB_READ_PEND_FLAG SB_BUFFER(0x23A5) + #define RFBI_FIRST_CW SB_BUFFER(0x23A6) + #define RFBI_BAD_CW SB_BUFFER(0x23A7) + #define RFBI_INVALID_CW SB_BUFFER(0x23A8) + #define RFBI_RETX_CW SB_BUFFER(0x23A9) + #define RFBI_CHK_DTU_STATUS SB_BUFFER(0x23AA) + + //===================================================================== + // per PVC counter for RX error_pdu and correct_pdu + // address : 0x23B0 - 0x23CF + // size : 32 + //===================================================================== + #define WRX_PER_PVC_CORRECT_PDU_BASE SB_BUFFER(0x23B0) + #define WRX_PER_PVC_ERROR_PDU_BASE SB_BUFFER(0x23C0) + + #define __WRXCTXT_L2_RdPtr(i) SB_BUFFER(0x2422 + (i)) + #define __WRXCTXT_L2Pages(i) SB_BUFFER(0x2424 + (i)) + + #define __WTXCTXT_TC_WRPTR(i) SB_BUFFER(0x2450 + (i)) + #define __WRXCTXT_PortState(i) SB_BUFFER(0x242A + (i)) + +#endif + + + +#endif // IFXMIPS_ATM_FW_REGS_AR9_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_regs_common.h b/package/ltq-dsl/src/ifxmips_atm_fw_regs_common.h index a5f59b8c40..432969b933 100644 --- a/package/ltq-dsl/src/ifxmips_atm_fw_regs_common.h +++ b/package/ltq-dsl/src/ifxmips_atm_fw_regs_common.h @@ -1,3 +1,30 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_regs_common.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (Firmware Register Structures) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + #ifndef IFXMIPS_ATM_FW_REGS_COMMON_H #define IFXMIPS_ATM_FW_REGS_COMMON_H @@ -143,6 +170,15 @@ struct wan_mib_table { */ #if defined(__BIG_ENDIAN) + struct fw_ver_id { + unsigned int family :4; + unsigned int fwtype :4; + unsigned int interface :4; + unsigned int fwmode :4; + unsigned int major :8; + unsigned int minor :8; + }; + struct wrx_queue_config { /* 0h */ unsigned int res2 :27; @@ -161,6 +197,28 @@ struct wan_mib_table { unsigned int cpiexp :8; }; + struct wrx_queue_context { + /* 0h */ + unsigned int curr_len :16; + unsigned int res0 :12; + unsigned int mfs :1; + unsigned int ec :1; + unsigned int clp1 :1; + unsigned int aal5dp :1; + + /* 1h */ + unsigned int intcrc; + + /* 2h, 3h */ + unsigned int curr_des0; + unsigned int curr_des1; + + /* 4h - 0xE */ + unsigned int res1[11]; + + unsigned int last_dword; + }; + struct wtx_port_config { unsigned int res1 :27; unsigned int qid :4; @@ -170,11 +228,27 @@ struct wan_mib_table { struct wtx_queue_config { unsigned int res1 :25; unsigned int sbid :1; - unsigned int res2 :3; - unsigned int type :2; + unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to. + unsigned int res2 :1; unsigned int qsben :1; }; + struct wrx_desc_context { + unsigned int dmach_wrptr : 16; + unsigned int dmach_rdptr : 16; + + unsigned int res0 : 16; + unsigned int dmach_fcnt : 16; + + unsigned int res1 : 11; + unsigned int desbuf_wrptr : 5; + unsigned int res2 : 11; + unsigned int desbuf_rdptr : 5; + + unsigned int res3 : 27; + unsigned int desbuf_vcnt : 5; + }; + struct wrx_dma_channel_config { /* 0h */ unsigned int res1 :1; @@ -291,8 +365,8 @@ struct wan_mib_table { struct wtx_queue_config { unsigned int qsben :1; - unsigned int type :2; - unsigned int res2 :3; + unsigned int res2 :1; + unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to. unsigned int sbid :1; unsigned int res1 :25; }; @@ -359,6 +433,114 @@ struct wan_mib_table { }; #endif // defined(__BIG_ENDIAN) +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + #if defined(__BIG_ENDIAN) + + struct Retx_adsl_ppe_intf { + unsigned int res0_0 : 16; + unsigned int dtu_sid : 8; + unsigned int dtu_timestamp : 8; + + unsigned int res1_0 : 16; + unsigned int local_time : 8; + unsigned int res1_1 : 5; + unsigned int is_last_cw : 1; + unsigned int reinit_flag : 1; + unsigned int is_bad_cw : 1; + }; + + struct Retx_adsl_ppe_intf_rec { + + unsigned int local_time : 8; + unsigned int res1_1 : 5; + unsigned int is_last_cw : 1; + unsigned int reinit_flag : 1; + unsigned int is_bad_cw : 1; + + unsigned int dtu_sid : 8; + unsigned int dtu_timestamp : 8; + + }; + + struct Retx_mode_cfg { + unsigned int res0 :8; + unsigned int invld_range :8; // used for rejecting the too late arrival of the retransmitted DTU + unsigned int buff_size :8; // the total number of cells in playout buffer is 32 * buff_size + unsigned int res1 :7; + unsigned int retx_en :1; + }; + + struct Retx_Tsync_cfg { + unsigned int fw_alpha :16; // number of consecutive HEC error cell causes that the cell delineation state machine transit from SYNC to HUNT (0 means never) + unsigned int sync_inp :16; // reserved + }; + + struct Retx_Td_cfg { + unsigned int res0 :8; + unsigned int td_max :8; // maximum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver + unsigned int res1 :8; + unsigned int td_min :8; // minimum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver + }; + + struct Retx_MIB_Timer_cfg { + unsigned int ticks_per_sec : 16; + unsigned int tick_cycle : 16; + }; + + struct DTU_stat_info { + unsigned int complete : 1; + unsigned int bad : 1; + unsigned int res0_0 : 14; + unsigned int time_stamp : 8; + unsigned int cell_cnt : 8; + + unsigned int dtu_rd_ptr : 16; + unsigned int dtu_wr_ptr : 16; + }; + + struct Retx_ctrl_field { + unsigned int res0 : 1; + + unsigned int l2_drop : 1; + unsigned int res1 : 13; + unsigned int retx : 1; + + unsigned int dtu_sid : 8; + unsigned int cell_sid : 8; + }; + + #else + #error Little Endian is not supported yet. + #endif + + struct dsl_param { + unsigned int update_flag; // 00 + unsigned int res0; // 04 + unsigned int MinDelayrt; // 08 + unsigned int MaxDelayrt; // 0C + unsigned int res1; // 10 + unsigned int res2; // 14 + unsigned int RetxEnable; // 18 + unsigned int ServiceSpecificReTx; // 1C + unsigned int res3; // 20 + unsigned int ReTxPVC; // 24 + unsigned int res4; // 28 + unsigned int res5; // 2C + unsigned int res6; // 30 + unsigned int res7; // 34 + unsigned int res8; // 38 + unsigned int res9; // 3C + unsigned int res10; // 40 + unsigned int res11; // 44 + unsigned int res12; // 48 + unsigned int res13; // 4C + unsigned int RxDtuCorruptedCNT; // 50 + unsigned int RxRetxDtuUnCorrectedCNT;// 54 + unsigned int RxLastEFB; // 58 + unsigned int RxDtuCorrectedCNT; // 5C + }; +#endif + #endif // IFXMIPS_ATM_FW_REGS_COMMON_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_regs_danube.h b/package/ltq-dsl/src/ifxmips_atm_fw_regs_danube.h index c0dfc6a2e0..5239fce8c9 100644 --- a/package/ltq-dsl/src/ifxmips_atm_fw_regs_danube.h +++ b/package/ltq-dsl/src/ifxmips_atm_fw_regs_danube.h @@ -1,3 +1,30 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_regs_danube.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (Firmware Registers) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + #ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H #define IFXMIPS_ATM_FW_REGS_DANUBE_H @@ -6,7 +33,7 @@ /* * Host-PPE Communication Data Address Mapping */ -#define FW_VER_ID SB_BUFFER(0x2001) +#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001)) #define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */ #define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */ #define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */ @@ -16,14 +43,135 @@ #define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */ #define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */ #define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20)) +#define WRX_QUEUE_CONTEXT(i) ((struct wrx_queue_context*) SB_BUFFER(0x2504 + (i) * 20)) #define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7)) +#define WRX_DESC_CONTEXT(i) ((struct wrx_desc_context*) SB_BUFFER(0x2643 + (i) * 7)) #define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i))) #define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27)) #define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27)) #define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410)) -#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i))) -#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i))) -#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i))) +#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX + #define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i))) + #define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i))) + #define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i))) +#else + #define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2020 + (i))) + #define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2040 + (i))) + #define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2060 + (i))) +#endif + +#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX + + #define RETX_MODE_CFG ((volatile struct Retx_mode_cfg *) SB_BUFFER(0x2408)) + #define RETX_TSYNC_CFG ((volatile struct Retx_Tsync_cfg *) SB_BUFFER(0x2409)) + #define RETX_TD_CFG ((volatile struct Retx_Td_cfg *) SB_BUFFER(0x240A)) + #define RETX_MIB_TIMER_CFG ((volatile struct Retx_MIB_Timer_cfg *) SB_BUFFER(0x240B)) + #define RETX_PLAYOUT_BUFFER_BASE SB_BUFFER(0x240D) + #define RETX_SERVICE_HEADER_CFG SB_BUFFER(0x240E) + #define RETX_MASK_HEADER_CFG SB_BUFFER(0x240F) + + #define RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) PPE_REG_ADDR(0x0D78)) + #define BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AC)) + #define FIRST_BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AE)) + + #define PB_BUFFER_USAGE SB_BUFFER(0x2100) + #define DTU_STAT_INFO ((volatile struct DTU_stat_info *) SB_BUFFER(0x2180)) + #define DTU_VLD_STAT SB_BUFFER(0x2380) + + + //===================================================================== + // retx firmware mib, for debug purpose + // address : 0x2388 - 0x238F + // size : 8 + //===================================================================== + #define URETX_RX_TOTAL_DTU SB_BUFFER(0x2388) + #define URETX_RX_BAD_DTU SB_BUFFER(0x2389) + #define URETX_RX_GOOD_DTU SB_BUFFER(0x238A) + #define URETX_RX_CORRECTED_DTU SB_BUFFER(0x238B) + #define URETX_RX_OUTOFDATE_DTU SB_BUFFER(0x238C) + #define URETX_RX_DUPLICATE_DTU SB_BUFFER(0x238D) + #define URETX_RX_TIMEOUT_DTU SB_BUFFER(0x238E) + + #define URETX_ALPHA_SWITCH_TO_HUNT_TIMES SB_BUFFER(0x238F) + + // cell counter for debug purpose + #define WRX_BC0_CELL_NUM SB_BUFFER(0x23E0) + #define WRX_BC0_DROP_CELL_NUM SB_BUFFER(0x23E1) + #define WRX_BC0_NONRETX_CELL_NUM SB_BUFFER(0x23E2) + #define WRX_BC0_RETX_CELL_NUM SB_BUFFER(0x23E3) + #define WRX_BC0_OUTOFDATE_CELL_NUM SB_BUFFER(0x23E4) + #define WRX_BC0_DIRECTUP_NUM SB_BUFFER(0x23E5) + #define WRX_BC0_PBW_TOTAL_NUM SB_BUFFER(0x23E6) + #define WRX_BC0_PBW_SUCC_NUM SB_BUFFER(0x23E7) + #define WRX_BC0_PBW_FAIL_NUM SB_BUFFER(0x23E8) + #define WRX_BC1_CELL_NUM SB_BUFFER(0x23E9) + + // debug info (interface) + + #define DBG_DTU_INTF_WRPTR SB_BUFFER(0x2390) + #define DBG_INTF_FCW_DUP_CNT SB_BUFFER(0x2391) + #define DBG_INTF_SID_CHANGE_IN_DTU_CNT SB_BUFFER(0x2392) + #define DBG_INTF_LCW_DUP_CNT SB_BUFFER(0x2393) + + #define DBG_RFBI_DONE_INT_CNT SB_BUFFER(0x2394) + #define DBG_DREG_BEG_END SB_BUFFER(0x2395) + #define DBG_RFBI_BC0_INVALID_CNT SB_BUFFER(0x2396) + #define DBG_RFBI_LAST_T SB_BUFFER(0x2397) + + #define DBG_RFBI_INTV0 SB_BUFFER(0x23EE) + #define DBG_RFBI_INTV1 SB_BUFFER(0x23EF) + + #define DBG_INTF_INFO(i) ((volatile struct Retx_adsl_ppe_intf_rec *) SB_BUFFER(0x23F0 + i)) + + // Internal status + #define URetx_curr_time SB_BUFFER(0x2398) + #define URetx_sec_counter SB_BUFFER(0x2399) + #define RxCURR_EFB SB_BUFFER(0x239A) + #define RxDTURetransmittedCNT SB_BUFFER(0x239B) + + //===================================================================== + // standardized MIB counter + // address : 0x239C - 0x239F + // size : 4 + //===================================================================== + #define RxLastEFBCNT SB_BUFFER(0x239C) + #define RxDTUCorrectedCNT SB_BUFFER(0x239D) + #define RxDTUCorruptedCNT SB_BUFFER(0x239E) + #define RxRetxDTUUncorrectedCNT SB_BUFFER(0x239F) + + + //===================================================================== + // General URetx Context + // address : 0x23A0 - 0x23AF + // size : 16 + //===================================================================== + #define NEXT_DTU_SID_OUT SB_BUFFER(0x23A0) + #define LAST_DTU_SID_IN SB_BUFFER(0x23A1) + #define NEXT_CELL_SID_OUT SB_BUFFER(0x23A2) + #define ISR_CELL_ID SB_BUFFER(0x23A3) + #define PB_CELL_SEARCH_IDX SB_BUFFER(0x23A4) + #define PB_READ_PEND_FLAG SB_BUFFER(0x23A5) + #define RFBI_FIRST_CW SB_BUFFER(0x23A6) + #define RFBI_BAD_CW SB_BUFFER(0x23A7) + #define RFBI_INVALID_CW SB_BUFFER(0x23A8) + #define RFBI_RETX_CW SB_BUFFER(0x23A9) + #define RFBI_CHK_DTU_STATUS SB_BUFFER(0x23AA) + + //===================================================================== + // per PVC counter for RX error_pdu and correct_pdu + // address : 0x23B0 - 0x23CF + // size : 32 + //===================================================================== + #define WRX_PER_PVC_CORRECT_PDU_BASE SB_BUFFER(0x23B0) + #define WRX_PER_PVC_ERROR_PDU_BASE SB_BUFFER(0x23C0) + + #define __WRXCTXT_L2_RdPtr(i) SB_BUFFER(0x2422 + (i)) + #define __WRXCTXT_L2Pages(i) SB_BUFFER(0x2424 + (i)) + + #define __WTXCTXT_TC_WRPTR(i) SB_BUFFER(0x2450 + (i)) + #define __WRXCTXT_PortState(i) SB_BUFFER(0x242A + (i)) + +#endif diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_regs_vr9.h b/package/ltq-dsl/src/ifxmips_atm_fw_regs_vr9.h new file mode 100644 index 0000000000..edefe92d25 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_regs_vr9.h @@ -0,0 +1,59 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_regs_vr9.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (Firmware Registers) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + +#ifndef IFXMIPS_ATM_FW_REGS_VR9_H +#define IFXMIPS_ATM_FW_REGS_VR9_H + + + +/* + * Host-PPE Communication Data Address Mapping + */ +#define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001)) +#define CFG_WRX_HTUTS SB_BUFFER(0x2010) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */ +#define CFG_WRX_QNUM SB_BUFFER(0x2011) /* WAN RX Queue Number */ +#define CFG_WRX_DCHNUM SB_BUFFER(0x2012) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */ +#define CFG_WTX_DCHNUM SB_BUFFER(0x2013) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */ +#define CFG_WRDES_DELAY SB_BUFFER(0x2014) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */ +#define WRX_DMACH_ON SB_BUFFER(0x2015) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */ +#define WTX_DMACH_ON SB_BUFFER(0x2016) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */ +#define WRX_HUNT_BITTH SB_BUFFER(0x2017) /* WAN RX HUNT Threshold, must be between 2 to 8. */ +#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x4C00 + (i) * 20)) /* i < 16 */ +#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x4F80 + (i) * 7)) /* i < 8 */ +#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x4FB8 + (i))) /* i < 2 */ +#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x3A00 + (i) * 27)) /* i < 16 */ +#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x3A01 + (i) * 27)) /* i < 16 */ +#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x4EF0)) +#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x26A0 + (i))) /* i < 32 */ +#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x26C0 + (i))) /* i < 32 */ +#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x26E0 + (i))) /* i < 32 */ + +#define UTP_CFG SB_BUFFER(0x2018) // bit 0~3 - 0x0F: in showtime, 0x00: not in showtime + + + +#endif // IFXMIPS_ATM_FW_REGS_VR9_H diff --git a/package/ltq-dsl/src/ifxmips_atm_fw_vr9.h b/package/ltq-dsl/src/ifxmips_atm_fw_vr9.h new file mode 100644 index 0000000000..96b1725949 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_fw_vr9.h @@ -0,0 +1,427 @@ +#ifndef IFXMIPS_ATM_FW_VR9_H +#define IFXMIPS_ATM_FW_VR9_H + + +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_fw_vr9.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 22 OCT 2007 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PP32 Firmware) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 22 OCT 2007 Xu Liang Initial Version, v00.01 +*******************************************************************************/ + + +#define VER_IN_FIRMWARE 1 + +#define ATM_FW_VER_MAJOR 0 +#define ATM_FW_VER_MINOR 24 + + +static u32 firmware_binary_code[] = { + 0x800004B8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFE0, 0x00000000, 0x00000000, 0x00000000, + 0xC1000002, 0xD90C00F8, 0xC2000002, 0xDA0800F9, 0x80004390, 0xC2000000, 0xDA0800F9, 0x80003A10, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x800039C8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x80004B60, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x800038C8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400000, 0xC000ABC0, 0xC88400F8, 0x80004050, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0400002, 0xC000ABC0, 0xC88400F8, 0x80003FD0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC3C00004, 0xDBC800F9, 0xC10C0002, 0xD90C00F8, 0x8000FEE0, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC10E0002, 0xD90C00F8, 0xC0004028, 0xC84000F8, 0x80004000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481, + 0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC800F9, 0xC1400008, 0xC1900000, 0x71588000, + 0x14100100, 0xC140000A, 0xC1900002, 0x71588000, 0x14100100, 0xC140000C, 0xC1900004, 0x71588000, + 0x14100100, 0xC1400004, 0xC1900006, 0x71588000, 0x14100100, 0xC1400006, 0xC1900008, 0x71588000, + 0x14100100, 0xC140000E, 0xC190000A, 0x71588000, 0x14100100, 0xC1400000, 0xC190000C, 0x71588000, + 0x14100100, 0xC1400002, 0xC190000E, 0x71588000, 0x14100100, 0xC0400000, 0xC11C0000, 0xC000E82C, + 0xCD05CE00, 0xC11C0002, 0xC000E82C, 0xCD05CE00, 0xC0400002, 0xC11C0000, 0xC000E82C, 0xCD05CE00, + 0xC11C0002, 0xC000E82C, 0xCD05CE00, 0xC000E824, 0x00000000, 0xCBC000F9, 0xCB8000F9, 0xCB4000F9, + 0xCB0000F8, 0xC000ABE4, 0x5BFC4000, 0xCFC000F9, 0x5BB84000, 0xCF8000F9, 0x5B744000, 0xCF4000F9, + 0x5B304000, 0xCF0000F8, 0xC000EA10, 0x00000000, 0xCBC000F9, 0xCB8000F8, 0xC000ABE0, 0x5BFC4000, + 0xCFC000F9, 0x5BB84000, 0xCF8000F8, 0xC30001FE, 0xC000F416, 0xCF0000F8, 0xC3000000, 0x7F018000, + 0xC000E42E, 0xCF0000F8, 0xC000E40E, 0xCF0000F8, 0xC3C1FFFE, 0xC000690E, 0xCFC00078, 0xC000692C, + 0xCFC00078, 0xC0006924, 0xCFC00038, 0xC0006912, 0xCFC00038, 0xC0006966, 0xCFC00038, 0xC0006968, + 0xCFC00078, 0xC000696A, 0xCFC00078, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000, + 0x6FD44000, 0x4395C000, 0x5BB89800, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFC8, 0x00000000, + 0xC3C00000, 0xC2800010, 0x6FF86000, 0x47BDC000, 0x5BB89F00, 0xC3400000, 0x58380004, 0xCB420078, + 0x00000000, 0x58380008, 0xCF400078, 0x5BFC0002, 0xB7E8FFB0, 0x00000000, 0xC3C00000, 0xC2800020, + 0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000, 0x5BB87400, + 0x58380008, 0xCF408418, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFB0, 0x00000000, 0x00000000, + 0xC3E0E282, 0x5BFC0030, 0xC0004002, 0xCFC000F8, 0xC000E82C, 0xC11E0002, 0xCD01EF00, 0xC000E82E, + 0xCD01EF00, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x80000028, 0x00000000, 0x80001CB8, + 0x00000000, 0x8000FFE0, 0xC0006918, 0xD28000F8, 0xC2000000, 0xDF600038, 0x5E600020, 0x84000272, + 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000402A, 0xCA0000F8, 0xC0006912, + 0xCA4000F8, 0xC0006924, 0xCA8000F8, 0xC0006966, 0xCAC000F8, 0x00000000, 0xC121FFFE, 0x5911FE94, + 0x14100000, 0x76250000, 0x76290000, 0x762D0000, 0x840001CA, 0xC0006918, 0xCA4000F8, 0xC28001FE, + 0x76290000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x8400001A, 0x6AA54000, 0x80000010, 0xC62800F8, + 0x62818008, 0xC0006918, 0xCF0000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC0006966, + 0xCA4000F8, 0xC2000002, 0x6A310000, 0x7E010000, 0x76612000, 0xCE4000F8, 0x00000000, 0xC121FFFE, + 0x5911FE94, 0x14100000, 0x6F346000, 0x4771A000, 0x5B749F00, 0xC2800000, 0x58340006, 0xCA800078, + 0xC2C00000, 0x58340000, 0xCAC000D8, 0xC2400000, 0x5834000A, 0xCA420078, 0x6EA82000, 0x42E9E000, + 0x6F2CA000, 0x42E56000, 0x5AEC3200, 0xC3990040, 0xC7381C18, 0xC6F80060, 0x99005560, 0xDB9800F8, + 0xDBD800F9, 0x00000000, 0xDEA000F8, 0x46310000, 0x8400FD80, 0xC0006958, 0xC84000F8, 0x00000000, + 0xC3C00002, 0x787C2000, 0xCC4000F8, 0xC000ABC8, 0xCB8400F8, 0xC000ABC4, 0xC88400F8, 0x5FB80000, + 0x8400FCFA, 0xC000FAC0, 0xCA0400F8, 0x00000000, 0x00000000, 0xA6040070, 0xC000ABE4, 0xC80400F8, + 0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0x98C05CD8, + 0xC000697C, 0xCA0000F8, 0x59640004, 0xC0004030, 0xCA0000F8, 0xC2400002, 0x6A452000, 0x76250000, + 0x8400FC3A, 0xC000ABE8, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000, 0xCA0000F8, 0xC42400F8, + 0x00000000, 0xA63C17DA, 0x00000000, 0xC000ABE4, 0xC80400F8, 0x6C908000, 0x45088000, 0x45088000, + 0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0xC0006934, 0xCE0000F8, 0xC2800002, 0xC4681C08, + 0xC62821D0, 0xC2600010, 0x5A650D80, 0xC0004020, 0xCB4000F8, 0xC2200400, 0x5A200D40, 0xC7601040, + 0xC000F220, 0xCE8000F8, 0xC000F200, 0xCE4000F8, 0xC000F202, 0xCE0000F8, 0xC000F240, 0xCB4000F8, + 0x00000000, 0x00000000, 0xA754FFE0, 0xC2000000, 0xC7600040, 0xA7520042, 0x00000000, 0x00000000, + 0x99005FD8, 0xC0009DE2, 0xC94000F8, 0xC1800002, 0x80001680, 0x58204DC0, 0xC2000000, 0xCA000018, + 0xC2400000, 0xCA414000, 0xC2800000, 0xCA812000, 0xC2C00000, 0xCAC20018, 0xC0006938, 0xCE0000F8, + 0xC0006920, 0xCE4000F8, 0xC0006916, 0xCE8000F8, 0xC0006922, 0xCEC000F8, 0xA6400540, 0x00000000, + 0xC0006938, 0xCBC000F8, 0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B749800, + 0x58340000, 0xCB802010, 0x00000000, 0xC2000000, 0x6FB46000, 0x4779A000, 0x5B749F00, 0x5834000C, + 0xCA000020, 0xC000691A, 0xCF8000F8, 0x5E200000, 0x8400046A, 0xC2000000, 0xDF610048, 0x5E6001E8, + 0x8800FFE8, 0xC2000002, 0xC2400466, 0xC2A00000, 0x5AA80000, 0xC000F006, 0xCE0000F8, 0xC000F008, + 0xCE4000F8, 0xC000F00A, 0xCE8000F8, 0x99004FA0, 0xC1A0FFFE, 0xC000E824, 0xC9840070, 0xC0006934, + 0xCA4000F8, 0xC2000000, 0xC2800002, 0x99004FE0, 0xDA9800F8, 0xC61400F8, 0xC65800F8, 0xC161FFFE, + 0x5955FFFE, 0x14140000, 0x00000000, 0x990050C8, 0xC000691A, 0xC94000F8, 0x00000000, 0x00000000, + 0xC121FFFE, 0x5911FE94, 0x14100000, 0xC0006922, 0xCA001118, 0xC3C00000, 0xC3800000, 0xC0006930, + 0xCE023118, 0xC0006932, 0xCBC000D8, 0xC2800000, 0xC000691E, 0xCFC000F8, 0xC000ABDE, 0xCA800060, + 0xC3A0001A, 0x5BB94000, 0xC6B80060, 0xC000691C, 0xCF8000F8, 0x99005338, 0xC000691C, 0xC1400000, + 0xC9420048, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFE8, 0xC2000000, 0xC1220002, 0xD90C00F8, + 0xDF600038, 0x5E600020, 0x8400FFF2, 0xC000691C, 0xCA0000F8, 0xC000691E, 0xCA4000F8, 0x00000000, + 0x00000000, 0x99005560, 0xDA1800F8, 0xDA5800F9, 0x00000000, 0xC2000000, 0xDF610048, 0x5E6001FE, + 0x8800FFE8, 0xC0006916, 0xCA8000F8, 0xC2C00000, 0xDFEC0048, 0xC2400000, 0x466D2000, 0x8400004A, + 0x5EA80000, 0x8400003A, 0xC2600002, 0x99005FD8, 0xC0009DEE, 0xC94000F8, 0xC1800002, 0x80000030, + 0xC2600000, 0x99005FD8, 0xC0009DEC, 0xC94000F8, 0xC1800002, 0xC2000068, 0xC6240078, 0xC0006930, + 0xCE400080, 0xC000691A, 0xC98000F8, 0xC000ABDE, 0xC94000F8, 0x6D9C6000, 0x45D8E000, 0x59DC9F00, + 0x990053C0, 0xD95800F8, 0xD99800F9, 0xD9D400F8, 0x99005338, 0xC000691C, 0xC1400000, 0xC9420048, + 0xC2000000, 0xDF600038, 0x5E600020, 0x8400FFEA, 0x00000000, 0xC000691C, 0xCA0000F8, 0xC000691E, + 0xCA4000F8, 0x00000000, 0x00000000, 0x99005560, 0xDA1800F8, 0xDA5800F9, 0x00000000, 0x800010E8, + 0x00000000, 0x99005FD8, 0xC0009DEA, 0xC94000F8, 0xC1800002, 0x800010B8, 0xC0006938, 0xCBC000F8, + 0x00000000, 0x00000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB89800, 0x58380008, 0xCA0000F8, + 0x00000000, 0x00000000, 0xA6000382, 0x00000000, 0xC0006938, 0xCBC000F8, 0xC3000000, 0x00000000, + 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB89800, 0x58380000, 0xCB002010, 0xC2000000, 0x58380008, + 0xCA020078, 0x5838000C, 0xCAC000F8, 0x5838000E, 0xCA4000F8, 0xC000691A, 0xCF0000F8, 0xC0006930, + 0xCEC000F8, 0xC000693C, 0xCE0000F8, 0xC0006932, 0xCE4000F8, 0x5E200000, 0x84000120, 0xC2800000, + 0xA6FE00BA, 0x6F206000, 0x46310000, 0x5A209F00, 0x5820000C, 0xCA800020, 0x00000000, 0x00000000, + 0x5EA80000, 0x840001F2, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x990050C8, + 0xC000691A, 0xC94000F8, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0xC0006930, + 0xCAC000F8, 0xC0006932, 0xCA4000F8, 0xC7EC1118, 0xC0006930, 0xCEC000F8, 0x5838000C, 0xCEC000F8, + 0x58000002, 0xCE4000F8, 0xC0006934, 0xCA0000F8, 0xC2400002, 0x6E642000, 0x6E642000, 0x76612000, + 0x8400002A, 0xC2400002, 0x6E684000, 0x58380008, 0xCE804200, 0xA6000020, 0x6E682000, 0x58380008, + 0xCE802100, 0xC2400002, 0x6E642000, 0x76612000, 0x840000EA, 0x58380008, 0xCA0000F8, 0xC2800000, + 0xC2400000, 0xA60200C0, 0xDBA800F8, 0x6F386000, 0x47B1C000, 0x5BB89F00, 0x58380004, 0xCA400078, + 0x58380002, 0xCA800078, 0x00000000, 0xDEB800F8, 0x46A54000, 0x88000060, 0x00000000, 0xC0009DE4, + 0xCA0000F8, 0xC2400002, 0x6E640000, 0x5A200002, 0xCE0000F8, 0x58380008, 0xCE400000, 0x80000018, + 0x00000000, 0x80000048, 0xC0006934, 0xCA0000F8, 0x00000000, 0x00000000, 0xA6020C6A, 0x00000000, + 0x00000000, 0x80000C98, 0xC2800000, 0xC2000080, 0xC240001A, 0xDF690048, 0x46294000, 0x46A54000, + 0x8800FFD2, 0xC2000006, 0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA8000F8, 0xC000F006, 0xCE0000F8, + 0xC000F008, 0xCE4000F8, 0xC000F00A, 0xCE8000F8, 0x99004FA0, 0xC1A0FFFE, 0xC000E824, 0xC9840070, + 0xC2000000, 0xC0006930, 0xCA02E008, 0x58380026, 0xCA4000F8, 0x00000000, 0xC2800000, 0x99004FE0, + 0xDA9800F8, 0xC61400F8, 0xC65800F8, 0xC0006934, 0xCA0000F8, 0x00000000, 0x00000000, 0xA6020022, + 0x00000000, 0x00000000, 0x80000318, 0xC0006938, 0xCBC000F8, 0xC000ABE4, 0xC80400F8, 0x6C908000, + 0x45088000, 0x45088000, 0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0x58240018, 0xCA0000F8, + 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB89800, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0078, + 0xC6270038, 0xC0006940, 0xCE400038, 0xC6260038, 0xC0006942, 0xCE400038, 0xC000693C, 0xCA0000F8, + 0x5EEC0000, 0x8400018A, 0x5A6C0010, 0x46254000, 0x88000190, 0x5A600052, 0x46E54000, 0x88000178, + 0x58380006, 0xCA8000F8, 0xC0006940, 0xCA0000F8, 0xC2400000, 0xC6A70038, 0x7E412000, 0x76612000, + 0xC2000000, 0xC6A10038, 0x46250000, 0x84000138, 0xC0006942, 0xCA0000F8, 0xC2400000, 0xC6A60038, + 0x7E412000, 0x76612000, 0xC2000000, 0xC6A00038, 0x58380002, 0xCA8000F8, 0x46250000, 0x840000E8, + 0xC2400000, 0xC6A60078, 0x466D0000, 0x880000DA, 0xC2400000, 0xC6A40078, 0x58380008, 0xCA8000F8, + 0x46E50000, 0x880000BA, 0x00000000, 0xA6820018, 0x00000000, 0xC7700B00, 0xA6840098, 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0x58000012, + 0xC9410038, 0xC0006950, 0xC9C000F8, 0xC55800F8, 0xC5940838, 0xC5581078, 0xD99400F8, 0xC000693C, + 0xC94000F8, 0xC0006954, 0xC98000F8, 0x59DC00A8, 0x45D4E000, 0x41D8E000, 0x5D5C0030, 0x88000010, + 0xC1C00030, 0xC1800000, 0xC5D84028, 0xC1400000, 0xC5D40008, 0x5DD40002, 0x84000072, 0x5DD40004, + 0x8400009A, 0x5DD40006, 0x840000C2, 0x5DD80026, 0x840000EA, 0xDD5400F8, 0xDD8000F9, 0x58000008, + 0x40180000, 0xCD4000F8, 0x59980002, 0x8000FFC0, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, + 0xCD4000B8, 0x59980002, 0x8000FF88, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400078, + 0x59980002, 0x8000FF50, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400038, 0x59980002, + 0x8000FF18, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012, 0xC94000F8, + 0xC0006954, 0xC9C000F8, 0xC0006950, 0xC9400078, 0xDD8000F9, 0x58000028, 0x5D9C0000, 0x84000052, + 0x5D9C0002, 0x84000052, 0x5D9C0004, 0x8400006A, 0xC55B0038, 0xC55C08B8, 0xCD800039, 0xCDC108B8, + 0x80000060, 0xCD4000F8, 0x80000050, 0xC55900B8, 0xC55C1838, 0xCD8000B9, 0xCDC31838, 0x80000028, + 0xC55A0078, 0xC55C1078, 0xCD800079, 0xCDC21078, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, + 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x88000012, 0xC59400F8, 0x9D000000, + 0xCD4000F8, 0x00000000, 0x00000000, 0xC000697E, 0xCA4000F8, 0xC0000000, 0xC55800F8, 0xC9D400F9, + 0x00000000, 0x00000000, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, + 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, + 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, + 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, + 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, + 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, + 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, + 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, + 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, + 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, + 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0xC000697C, 0x9CC00000, + 0xCE0000F8, 0xC000697E, 0xCE4000F8, 0x9D000000, 0x4158A000, 0xCD4000F8, 0x00000000, +}; + +static u32 firmware_binary_data[] = { +}; + + +#endif // IFXMIPS_ATM_FW_VR9_H + diff --git a/package/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h b/package/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h new file mode 100644 index 0000000000..b9ba2c7ebd --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_ppe_amazon_se.h @@ -0,0 +1,94 @@ +#ifndef IFXMIPS_ATM_PPE_AMAZON_SE_H +#define IFXMIPS_ATM_PPE_AMAZON_SE_H + + + +/* + * FPI Configuration Bus Register and Memory Address Mapping + */ +#define IFX_PPE (KSEG1 | 0x1E180000) +#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2))) +#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2))) +#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2))) +#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2))) +#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2))) +#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2))) +#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2))) +#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2))) +#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2))) +#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2))) +#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2))) +#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2))) +#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2))) +#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2))) + +/* + * DWORD-Length of Memory Blocks + */ +#define PP32_DEBUG_REG_DWLEN 0x0030 +#define PPM_INT_REG_DWLEN 0x0010 +#define PP32_INTERNAL_RES_DWLEN 0x00C0 +#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800) +#define PPE_REG_DWLEN 0x1000 +#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) +#define PPM_INT_UNIT_DWLEN 0x0100 +#define PPM_TIMER0_DWLEN 0x0100 +#define PPM_TASK_IND_REG_DWLEN 0x0100 +#define PPS_BRK_DWLEN 0x0100 +#define PPM_TIMER1_DWLEN 0x0100 +#define SB_RAM0_DWLEN 0x0A00 +#define SB_RAM1_DWLEN 0x0A00 +#define QSB_CONF_REG_DWLEN 0x0100 + +/* + * PP32 to FPI Address Mapping + */ +#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) : \ + (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) : \ + 0)) + +/* + * PP32 Debug Control Register + */ +#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) + +#define DBG_CTRL_RESTART 0 +#define DBG_CTRL_STOP 1 + +#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0D00) +#define PP32_BREAKPOINT_REASONS PP32_DEBUG_REG_ADDR(0, 0x0A00) + +#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0F00) + +#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0F80) + +#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0F81) + +/* + * Share Buffer + */ +#define SB_MST_PRI0 PPE_REG_ADDR(0x0300) +#define SB_MST_PRI1 PPE_REG_ADDR(0x0301) + +/* + * EMA Registers + */ +#define EMA_CMDCFG PPE_REG_ADDR(0x0A00) +#define EMA_DATACFG PPE_REG_ADDR(0x0A01) +#define EMA_CMDCNT PPE_REG_ADDR(0x0A02) +#define EMA_DATACNT PPE_REG_ADDR(0x0A03) +#define EMA_ISR PPE_REG_ADDR(0x0A04) +#define EMA_IER PPE_REG_ADDR(0x0A05) +#define EMA_CFG PPE_REG_ADDR(0x0A06) +#define EMA_SUBID PPE_REG_ADDR(0x0A07) + +#define EMA_ALIGNMENT 4 + +/* + * Mailbox IGU1 Interrupt + */ +#define PPE_MAILBOX_IGU1_INT (INT_NUM_IM2_IRL0 + 13) + + + +#endif // IFXMIPS_ATM_PPE_AMAZON_SE_H diff --git a/package/ltq-dsl/src/ifxmips_atm_ppe_ar9.h b/package/ltq-dsl/src/ifxmips_atm_ppe_ar9.h new file mode 100644 index 0000000000..5c5bfa8260 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_ppe_ar9.h @@ -0,0 +1,188 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_ppe_ar9.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PPE Registers) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + +#ifndef IFXMIPS_ATM_PPE_AR9_H +#define IFXMIPS_ATM_PPE_AR9_H + + + +/* + * FPI Configuration Bus Register and Memory Address Mapping + */ +#define IFX_PPE (KSEG1 | 0x1E180000) +#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2))) +#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2))) +#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2))) +#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2))) +#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2))) +#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2))) +#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2))) +#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2))) +#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2))) +#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2))) +#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2))) +#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2))) +#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8800) << 2))) +#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9000) << 2))) +#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9800) << 2))) +#define SB_RAM4_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xA000) << 2))) +#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2))) + +/* + * DWORD-Length of Memory Blocks + */ +#define PP32_DEBUG_REG_DWLEN 0x0030 +#define PPM_INT_REG_DWLEN 0x0010 +#define PP32_INTERNAL_RES_DWLEN 0x00C0 +#define CDM_CODE_MEMORYn_DWLEN(n) 0x1000 +#define PPE_REG_DWLEN 0x1000 +#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) +#define PPM_INT_UNIT_DWLEN 0x0100 +#define PPM_TIMER0_DWLEN 0x0100 +#define PPM_TASK_IND_REG_DWLEN 0x0100 +#define PPS_BRK_DWLEN 0x0100 +#define PPM_TIMER1_DWLEN 0x0100 +#define SB_RAM0_DWLEN 0x0800 +#define SB_RAM1_DWLEN 0x0800 +#define SB_RAM2_DWLEN 0x0800 +#define SB_RAM3_DWLEN 0x0800 +#define SB_RAM4_DWLEN 0x0C00 +#define QSB_CONF_REG_DWLEN 0x0100 + +/* + * PP32 to FPI Address Mapping + */ +#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x0FFF)) ? PPE_REG_ADDR((__sb_addr)): \ + (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x27FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \ + (((__sb_addr) >= 0x2800) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2800) : \ + (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x37FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x3000) : \ + (((__sb_addr) >= 0x3800) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3800) : \ + (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4BFF)) ? SB_RAM4_ADDR((__sb_addr) - 0x4000) : \ + 0)) + +/* + * PP32 Debug Control Register + */ +#define NUM_OF_PP32 1 + +#define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) + +#define DBG_CTRL_RESTART 0 +#define DBG_CTRL_STOP 1 + +#define PP32_CTRL_CMD(n) PP32_DEBUG_REG_ADDR(n, 0x0B00) + #define PP32_CTRL_CMD_RESTART (1 << 0) + #define PP32_CTRL_CMD_STOP (1 << 1) + #define PP32_CTRL_CMD_STEP (1 << 2) + #define PP32_CTRL_CMD_BREAKOUT (1 << 3) + +#define PP32_CTRL_OPT(n) PP32_DEBUG_REG_ADDR(n, 0x0C00) + #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON (3 << 0) + #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF (2 << 0) + #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON (3 << 2) + #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2) + #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON (3 << 4) + #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF (2 << 4) + #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON (3 << 6) + #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF (2 << 6) + #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n) (*PP32_CTRL_OPT(n) & (1 << 0)) + #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 2)) + #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 4)) + #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n) (*PP32_CTRL_OPT(n) & (1 << 6)) + +#define PP32_BRK_PC(n, i) PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2) +#define PP32_BRK_PC_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2) +#define PP32_BRK_DATA_ADDR(n, i) PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2) +#define PP32_BRK_DATA_ADDR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2) +#define PP32_BRK_DATA_VALUE_RD(n, i) PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2) +#define PP32_BRK_DATA_VALUE_RD_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2) +#define PP32_BRK_DATA_VALUE_WR(n, i) PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2) +#define PP32_BRK_DATA_VALUE_WR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2) + #define PP32_BRK_CONTEXT_MASK(i) (1 << (i)) + #define PP32_BRK_CONTEXT_MASK_EN (1 << 4) + #define PP32_BRK_COMPARE_GREATER_EQUAL (1 << 5) // valid for break data value rd/wr only + #define PP32_BRK_COMPARE_LOWER_EQUAL (1 << 6) + #define PP32_BRK_COMPARE_EN (1 << 7) + +#define PP32_BRK_TRIG(n) PP32_DEBUG_REG_ADDR(n, 0x0F00) + #define PP32_BRK_GRPi_PCn_ON(i, n) ((3 << ((n) * 2)) << ((i) * 16)) + #define PP32_BRK_GRPi_PCn_OFF(i, n) ((2 << ((n) * 2)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n) ((3 << ((n) * 2 + 4)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n) ((2 << ((n) * 2 + 4)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16)) + #define PP32_BRK_GRPi_PCn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8))) + #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8))) + #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8))) + #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8))) + +#define PP32_CPU_STATUS(n) PP32_DEBUG_REG_ADDR(n, 0x0D00) +#define PP32_HALT_STAT(n) PP32_CPU_STATUS(n) +#define PP32_DBG_CUR_PC(n) PP32_CPU_STATUS(n) + #define PP32_CPU_USER_STOPPED(n) (*PP32_CPU_STATUS(n) & (1 << 0)) + #define PP32_CPU_USER_BREAKIN_RCV(n) (*PP32_CPU_STATUS(n) & (1 << 1)) + #define PP32_CPU_USER_BREAKPOINT_MET(n) (*PP32_CPU_STATUS(n) & (1 << 2)) + #define PP32_CPU_CUR_PC(n) (*PP32_CPU_STATUS(n) >> 16) + +#define PP32_BREAKPOINT_REASONS(n) PP32_DEBUG_REG_ADDR(n, 0x0A00) + #define PP32_BRK_PC_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << (i))) + #define PP32_BRK_DATA_ADDR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2))) + #define PP32_BRK_DATA_VALUE_RD_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4))) + #define PP32_BRK_DATA_VALUE_WR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6))) + #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8))) + #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9))) + #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12))) + #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13))) + #define PP32_BRK_CUR_CONTEXT(n) ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03) + +#define PP32_GP_REG_BASE(n) PP32_DEBUG_REG_ADDR(n, 0x0E00) +#define PP32_GP_CONTEXTi_REGn(n, i, j) PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j)) + +/* + * EMA Registers + */ +#define EMA_CMDCFG PPE_REG_ADDR(0x0A00) +#define EMA_DATACFG PPE_REG_ADDR(0x0A01) +#define EMA_CMDCNT PPE_REG_ADDR(0x0A02) +#define EMA_DATACNT PPE_REG_ADDR(0x0A03) +#define EMA_ISR PPE_REG_ADDR(0x0A04) +#define EMA_IER PPE_REG_ADDR(0x0A05) +#define EMA_CFG PPE_REG_ADDR(0x0A06) +#define EMA_SUBID PPE_REG_ADDR(0x0A07) + +#define EMA_ALIGNMENT 4 + +/* + * Mailbox IGU1 Interrupt + */ +#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL0 + 24 + + + +#endif // IFXMIPS_ATM_PPE_AR9_H diff --git a/package/ltq-dsl/src/ifxmips_atm_ppe_common.h b/package/ltq-dsl/src/ifxmips_atm_ppe_common.h index c922276dfb..30b12c80d6 100644 --- a/package/ltq-dsl/src/ifxmips_atm_ppe_common.h +++ b/package/ltq-dsl/src/ifxmips_atm_ppe_common.h @@ -1,10 +1,33 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_ppe_common.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PPE Registers) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + #ifndef IFXMIPS_ATM_PPE_COMMON_H #define IFXMIPS_ATM_PPE_COMMON_H - -#if defined(CONFIG_LANTIQ) - #include "ifxmips_atm_ppe_danube.h" - #define CONFIG_DANUBE -#elif defined(CONFIG_DANUBE) +#if defined(CONFIG_DANUBE) #include "ifxmips_atm_ppe_danube.h" #elif defined(CONFIG_AMAZON_SE) #include "ifxmips_atm_ppe_amazon_se.h" @@ -17,6 +40,7 @@ #endif + /* * Code/Data Memory (CDM) Interface Configuration Register */ @@ -207,24 +231,134 @@ /* * RTHA/TTHA Registers */ -#define SFSM_STATE0 PPE_REG_ADDR(0x0410) -#define SFSM_STATE1 PPE_REG_ADDR(0x0411) -#define SFSM_DBA0 PPE_REG_ADDR(0x0412) -#define SFSM_DBA1 PPE_REG_ADDR(0x0413) -#define SFSM_CBA0 PPE_REG_ADDR(0x0414) -#define SFSM_CBA1 PPE_REG_ADDR(0x0415) -#define SFSM_CFG0 PPE_REG_ADDR(0x0416) -#define SFSM_CFG1 PPE_REG_ADDR(0x0417) -#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C) -#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D) -#define FFSM_DBA0 PPE_REG_ADDR(0x0508) -#define FFSM_DBA1 PPE_REG_ADDR(0x0509) -#define FFSM_CFG0 PPE_REG_ADDR(0x050A) -#define FFSM_CFG1 PPE_REG_ADDR(0x050B) -#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E) -#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F) -#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514) -#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515) +#define RFBI_CFG PPE_REG_ADDR(0x0400) +#define RBA_CFG0 PPE_REG_ADDR(0x0404) +#define RBA_CFG1 PPE_REG_ADDR(0x0405) +#define RCA_CFG0 PPE_REG_ADDR(0x0408) +#define RCA_CFG1 PPE_REG_ADDR(0x0409) +#define RDES_CFG0 PPE_REG_ADDR(0x040C) +#define RDES_CFG1 PPE_REG_ADDR(0x040D) +#define SFSM_STATE0 PPE_REG_ADDR(0x0410) +#define SFSM_STATE1 PPE_REG_ADDR(0x0411) +#define SFSM_DBA0 PPE_REG_ADDR(0x0412) +#define SFSM_DBA1 PPE_REG_ADDR(0x0413) +#define SFSM_CBA0 PPE_REG_ADDR(0x0414) +#define SFSM_CBA1 PPE_REG_ADDR(0x0415) +#define SFSM_CFG0 PPE_REG_ADDR(0x0416) +#define SFSM_CFG1 PPE_REG_ADDR(0x0417) +#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C) +#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D) +#define FFSM_DBA0 PPE_REG_ADDR(0x0508) +#define FFSM_DBA1 PPE_REG_ADDR(0x0509) +#define FFSM_CFG0 PPE_REG_ADDR(0x050A) +#define FFSM_CFG1 PPE_REG_ADDR(0x050B) +#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E) +#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F) +#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514) +#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515) + +/* + * PPE TC Logic Registers (partial) + */ +#define DREG_A_VERSION PPE_REG_ADDR(0x0D00) +#define DREG_A_CFG PPE_REG_ADDR(0x0D01) +#define DREG_AT_CTRL PPE_REG_ADDR(0x0D02) +#define DREG_AT_CB_CFG0 PPE_REG_ADDR(0x0D03) +#define DREG_AT_CB_CFG1 PPE_REG_ADDR(0x0D04) +#define DREG_AR_CTRL PPE_REG_ADDR(0x0D08) +#define DREG_AR_CB_CFG0 PPE_REG_ADDR(0x0D09) +#define DREG_AR_CB_CFG1 PPE_REG_ADDR(0x0D0A) +#define DREG_A_UTPCFG PPE_REG_ADDR(0x0D0E) +#define DREG_A_STATUS PPE_REG_ADDR(0x0D0F) +#define DREG_AT_CFG0 PPE_REG_ADDR(0x0D20) +#define DREG_AT_CFG1 PPE_REG_ADDR(0x0D21) +#define DREG_AT_FB_SIZE0 PPE_REG_ADDR(0x0D22) +#define DREG_AT_FB_SIZE1 PPE_REG_ADDR(0x0D23) +#define DREG_AT_CELL0 PPE_REG_ADDR(0x0D24) +#define DREG_AT_CELL1 PPE_REG_ADDR(0x0D25) +#define DREG_AT_IDLE_CNT0 PPE_REG_ADDR(0x0D26) +#define DREG_AT_IDLE_CNT1 PPE_REG_ADDR(0x0D27) +#define DREG_AT_IDLE0 PPE_REG_ADDR(0x0D28) +#define DREG_AT_IDLE1 PPE_REG_ADDR(0x0D29) +#define DREG_AR_CFG0 PPE_REG_ADDR(0x0D60) +#define DREG_AR_CFG1 PPE_REG_ADDR(0x0D61) +#define DREG_AR_CELL0 PPE_REG_ADDR(0x0D68) +#define DREG_AR_CELL1 PPE_REG_ADDR(0x0D69) +#define DREG_AR_IDLE_CNT0 PPE_REG_ADDR(0x0D6A) +#define DREG_AR_IDLE_CNT1 PPE_REG_ADDR(0x0D6B) +#define DREG_AR_AIIDLE_CNT0 PPE_REG_ADDR(0x0D6C) +#define DREG_AR_AIIDLE_CNT1 PPE_REG_ADDR(0x0D6D) +#define DREG_AR_BE_CNT0 PPE_REG_ADDR(0x0D6E) +#define DREG_AR_BE_CNT1 PPE_REG_ADDR(0x0D6F) +#define DREG_AR_HEC_CNT0 PPE_REG_ADDR(0x0D70) +#define DREG_AR_HEC_CNT1 PPE_REG_ADDR(0x0D71) +#define DREG_AR_IDLE0 PPE_REG_ADDR(0x0D74) +#define DREG_AR_IDLE1 PPE_REG_ADDR(0x0D75) +#define DREG_AR_CVN_CNT0 PPE_REG_ADDR(0x0DA4) +#define DREG_AR_CVN_CNT1 PPE_REG_ADDR(0x0DA5) +#define DREG_AR_CVNP_CNT0 PPE_REG_ADDR(0x0DA6) +#define DREG_AR_CVNP_CNT1 PPE_REG_ADDR(0x0DA7) +#define DREG_B0_LADR PPE_REG_ADDR(0x0DA8) +#define DREG_B1_LADR PPE_REG_ADDR(0x0DA9) + +#define SFSM_DBA(i) ( (SFSM_dba * ) PPE_REG_ADDR(0x0412 + (i))) +#define SFSM_CBA(i) ( (SFSM_cba * ) PPE_REG_ADDR(0x0414 + (i))) +#define SFSM_CFG(i) ( (SFSM_cfg * ) PPE_REG_ADDR(0x0416 + (i))) +#define SFSM_PGCNT(i) ( (SFSM_pgcnt * ) PPE_REG_ADDR(0x041C + (i))) + +#define FFSM_DBA(i) ( (FFSM_dba * ) PPE_REG_ADDR(0x0508 + (i))) +#define FFSM_CFG(i) ( (FFSM_cfg * ) PPE_REG_ADDR(0x050A + (i))) +#define FFSM_PGCNT(i) ( (FFSM_pgcnt * ) PPE_REG_ADDR(0x0514 + (i))) + +typedef struct { + unsigned int res : 19; + unsigned int dbase : 13; +} SFSM_dba; + +typedef struct { + unsigned int res : 19; + unsigned int cbase : 13; +} SFSM_cba; + +typedef struct { + unsigned int res : 15; + unsigned int endian : 1; + unsigned int idlekeep: 1; + unsigned int sen : 1; + unsigned int res1 : 8; + unsigned int pnum : 6; +} SFSM_cfg; + +typedef struct { + unsigned int res : 17; + unsigned int pptr : 6; + unsigned int dcmd : 1; + unsigned int res1 : 2; + unsigned int upage : 6; +} SFSM_pgcnt; + +typedef struct { + unsigned int res : 19; + unsigned int dbase : 13; +} FFSM_dba; + +typedef struct { + unsigned int res : 12; + unsigned int rstptr : 1; + unsigned int clvpage : 1; + unsigned int fidle : 1; + unsigned int endian : 1; + unsigned int res1 : 10; + unsigned int pnum : 6; +} FFSM_cfg; + +typedef struct { + unsigned int res : 17; + unsigned int ival : 6; + unsigned int icmd : 1; + unsigned int res1 : 2; + unsigned int vpage : 6; +} FFSM_pgcnt; diff --git a/package/ltq-dsl/src/ifxmips_atm_ppe_danube.h b/package/ltq-dsl/src/ifxmips_atm_ppe_danube.h index 34cf877051..7e46cc1838 100644 --- a/package/ltq-dsl/src/ifxmips_atm_ppe_danube.h +++ b/package/ltq-dsl/src/ifxmips_atm_ppe_danube.h @@ -1,3 +1,30 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_ppe_danube.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PPE Registers) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + #ifndef IFXMIPS_ATM_PPE_DANUBE_H #define IFXMIPS_ATM_PPE_DANUBE_H @@ -76,6 +103,8 @@ #define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081) +#define PP32_DBG_REG_BASE(tsk, i) PP32_DEBUG_REG_ADDR(0, 0x0100 + (tsk) * 16 + (i)) + /* * EMA Registers */ diff --git a/package/ltq-dsl/src/ifxmips_atm_ppe_vr9.h b/package/ltq-dsl/src/ifxmips_atm_ppe_vr9.h new file mode 100644 index 0000000000..316a772858 --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_ppe_vr9.h @@ -0,0 +1,192 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_ppe_vr9.h +** PROJECT : UEIP +** MODULES : ATM (ADSL) +** +** DATE : 1 AUG 2005 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM Driver (PPE Registers) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 4 AUG 2005 Xu Liang Initiate Version +** 23 OCT 2006 Xu Liang Add GPL header. +** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) +*******************************************************************************/ + + + +#ifndef IFXMIPS_ATM_PPE_VR9_H +#define IFXMIPS_ATM_PPE_VR9_H + + + +/* + * FPI Configuration Bus Register and Memory Address Mapping + */ +#define IFX_PPE (KSEG1 | 0x1E200000) +#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x000000 + (i) * 0x00010000) << 2))) +#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x001000 + (i) * 0x00010000) << 2))) +#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x004000 + (i) * 0x00010000) << 2))) +#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x008000) << 2))) +#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x009000) << 2))) +#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00A000) << 2))) +#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00B000) << 2))) +#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00D000) << 2))) +#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00E000) << 2))) +#define SB_RAM6_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x018000) << 2))) + +/* + * DWORD-Length of Memory Blocks + */ +#define PP32_DEBUG_REG_DWLEN 0x0030 +#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800) +#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) +#define SB_RAM0_DWLEN 0x1000 +#define SB_RAM1_DWLEN 0x1000 +#define SB_RAM2_DWLEN 0x1000 +#define SB_RAM3_DWLEN 0x1000 +#define SB_RAM6_DWLEN 0x8000 +#define QSB_CONF_REG_DWLEN 0x0100 + +/* + * PP32 to FPI Address Mapping + */ +#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x1FFF)) ? PPE_REG_ADDR((__sb_addr)) : \ + (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \ + (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x3000) : \ + (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4FFF)) ? SB_RAM2_ADDR((__sb_addr) - 0x4000) : \ + (((__sb_addr) >= 0x5000) && ((__sb_addr) <= 0x5FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x5000) : \ + (((__sb_addr) >= 0x7000) && ((__sb_addr) <= 0x7FFF)) ? PPE_REG_ADDR((__sb_addr) - 0x7000) : \ + (((__sb_addr) >= 0x8000) && ((__sb_addr) <= 0xFFFF)) ? SB_RAM6_ADDR((__sb_addr) - 0x8000) : \ + 0)) + +/* + * PP32 Debug Control Register + */ +#define NUM_OF_PP32 2 + +#define PP32_FREEZE PPE_REG_ADDR(0x0000) +#define PP32_SRST PPE_REG_ADDR(0x0020) + +#define PP32_DBG_CTRL(n) PP32_DEBUG_REG_ADDR(n, 0x0000) + +#define DBG_CTRL_RESTART 0 +#define DBG_CTRL_STOP 1 + +#define PP32_CTRL_CMD(n) PP32_DEBUG_REG_ADDR(n, 0x0B00) + #define PP32_CTRL_CMD_RESTART (1 << 0) + #define PP32_CTRL_CMD_STOP (1 << 1) + #define PP32_CTRL_CMD_STEP (1 << 2) + #define PP32_CTRL_CMD_BREAKOUT (1 << 3) + +#define PP32_CTRL_OPT(n) PP32_DEBUG_REG_ADDR(n, 0x0C00) + #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON (3 << 0) + #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF (2 << 0) + #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON (3 << 2) + #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2) + #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON (3 << 4) + #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF (2 << 4) + #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON (3 << 6) + #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF (2 << 6) + #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n) (*PP32_CTRL_OPT(n) & (1 << 0)) + #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 2)) + #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n) (*PP32_CTRL_OPT(n) & (1 << 4)) + #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n) (*PP32_CTRL_OPT(n) & (1 << 6)) + +#define PP32_BRK_PC(n, i) PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2) +#define PP32_BRK_PC_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2) +#define PP32_BRK_DATA_ADDR(n, i) PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2) +#define PP32_BRK_DATA_ADDR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2) +#define PP32_BRK_DATA_VALUE_RD(n, i) PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2) +#define PP32_BRK_DATA_VALUE_RD_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2) +#define PP32_BRK_DATA_VALUE_WR(n, i) PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2) +#define PP32_BRK_DATA_VALUE_WR_MASK(n, i) PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2) + #define PP32_BRK_CONTEXT_MASK(i) (1 << (i)) + #define PP32_BRK_CONTEXT_MASK_EN (1 << 4) + #define PP32_BRK_COMPARE_GREATER_EQUAL (1 << 5) // valid for break data value rd/wr only + #define PP32_BRK_COMPARE_LOWER_EQUAL (1 << 6) + #define PP32_BRK_COMPARE_EN (1 << 7) + +#define PP32_BRK_TRIG(n) PP32_DEBUG_REG_ADDR(n, 0x0F00) + #define PP32_BRK_GRPi_PCn_ON(i, n) ((3 << ((n) * 2)) << ((i) * 16)) + #define PP32_BRK_GRPi_PCn_OFF(i, n) ((2 << ((n) * 2)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n) ((3 << ((n) * 2 + 4)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n) ((2 << ((n) * 2 + 4)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16)) + #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16)) + #define PP32_BRK_GRPi_PCn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8))) + #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8))) + #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8))) + #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8))) + +#define PP32_CPU_STATUS(n) PP32_DEBUG_REG_ADDR(n, 0x0D00) +#define PP32_HALT_STAT(n) PP32_CPU_STATUS(n) +#define PP32_DBG_CUR_PC(n) PP32_CPU_STATUS(n) + #define PP32_CPU_USER_STOPPED(n) (*PP32_CPU_STATUS(n) & (1 << 0)) + #define PP32_CPU_USER_BREAKIN_RCV(n) (*PP32_CPU_STATUS(n) & (1 << 1)) + #define PP32_CPU_USER_BREAKPOINT_MET(n) (*PP32_CPU_STATUS(n) & (1 << 2)) + #define PP32_CPU_CUR_PC(n) (*PP32_CPU_STATUS(n) >> 16) + +#define PP32_BREAKPOINT_REASONS(n) PP32_DEBUG_REG_ADDR(n, 0x0A00) + #define PP32_BRK_PC_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << (i))) + #define PP32_BRK_DATA_ADDR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2))) + #define PP32_BRK_DATA_VALUE_RD_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4))) + #define PP32_BRK_DATA_VALUE_WR_MET(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6))) + #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8))) + #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9))) + #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12))) + #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i) (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13))) + #define PP32_BRK_CUR_CONTEXT(n) ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03) + +#define PP32_GP_REG_BASE(n) PP32_DEBUG_REG_ADDR(n, 0x0E00) +#define PP32_GP_CONTEXTi_REGn(n, i, j) PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j)) + +/* + * PDMA/EMA Registers + */ +#define PDMA_CFG PPE_REG_ADDR(0x0A00) +#define PDMA_RX_CMDCNT PPE_REG_ADDR(0x0A01) +#define PDMA_TX_CMDCNT PPE_REG_ADDR(0x0A02) +#define PDMA_RX_FWDATACNT PPE_REG_ADDR(0x0A03) +#define PDMA_TX_FWDATACNT PPE_REG_ADDR(0x0A04) +#define PDMA_RX_CTX_CFG PPE_REG_ADDR(0x0A05) +#define PDMA_TX_CTX_CFG PPE_REG_ADDR(0x0A06) +#define PDMA_RX_MAX_LEN_REG PPE_REG_ADDR(0x0A07) +#define PDMA_RX_DELAY_CFG PPE_REG_ADDR(0x0A08) +#define PDMA_INT_FIFO_RD PPE_REG_ADDR(0x0A09) +#define PDMA_ISR PPE_REG_ADDR(0x0A0A) +#define PDMA_IER PPE_REG_ADDR(0x0A0B) +#define PDMA_SUBID PPE_REG_ADDR(0x0A0C) +#define PDMA_BAR0 PPE_REG_ADDR(0x0A0D) +#define PDMA_BAR1 PPE_REG_ADDR(0x0A0E) + +#define SAR_PDMA_RX_CMDBUF_CFG PPE_REG_ADDR(0x0F00) +#define SAR_PDMA_TX_CMDBUF_CFG PPE_REG_ADDR(0x0F01) +#define SAR_PDMA_RX_FW_CMDBUF_CFG PPE_REG_ADDR(0x0F02) +#define SAR_PDMA_TX_FW_CMDBUF_CFG PPE_REG_ADDR(0x0F03) +#define SAR_PDMA_RX_CMDBUF_STATUS PPE_REG_ADDR(0x0F04) +#define SAR_PDMA_TX_CMDBUF_STATUS PPE_REG_ADDR(0x0F05) + +#define PDMA_ALIGNMENT 4 +#define EMA_ALIGNMENT PDMA_ALIGNMENT + +/* + * Mailbox IGU1 Interrupt + */ +#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL0 + 24 + + + +#endif // IFXMIPS_ATM_PPE_VR9_H diff --git a/package/ltq-dsl/src/ifxmips_atm_vr9.c b/package/ltq-dsl/src/ifxmips_atm_vr9.c new file mode 100644 index 0000000000..ea84c4c83f --- /dev/null +++ b/package/ltq-dsl/src/ifxmips_atm_vr9.c @@ -0,0 +1,303 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_atm_vr9.c +** PROJECT : UEIP +** MODULES : ATM +** +** DATE : 7 Jul 2009 +** AUTHOR : Xu Liang +** DESCRIPTION : ATM driver common source file (core functions) +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 07 JUL 2009 Xu Liang Init Version +*******************************************************************************/ + + + +/* + * #################################### + * Head File + * #################################### + */ + +/* + * Common Head File + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/version.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/proc_fs.h> +#include <linux/init.h> +#include <linux/ioctl.h> +#include <asm/delay.h> + +/* + * Chip Specific Head File + */ +#include <ifx_types.h> +#include <ifx_regs.h> +#include <common_routines.h> +#include <ifx_pmu.h> +#include <ifx_rcu.h> +#include "ifxmips_atm_core.h" +#include "ifxmips_atm_fw_vr9.h" + + + +/* + * #################################### + * Definition + * #################################### + */ + + + +/* + * #################################### + * Declaration + * #################################### + */ + +/* + * Hardware Init/Uninit Functions + */ +static inline void init_pmu(void); +static inline void uninit_pmu(void); +static inline void reset_ppe(void); +static inline void init_pdma(void); +static inline void init_mailbox(void); +static inline void init_atm_tc(void); +static inline void clear_share_buffer(void); + + + +/* + * #################################### + * Local Variable + * #################################### + */ + + + +/* + * #################################### + * Local Function + * #################################### + */ + +static inline void init_pmu(void) +{ + //*PMU_PWDCR &= ~((1 << 29) | (1 << 22) | (1 << 21) | (1 << 19) | (1 << 18)); + //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); + PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); + PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); + PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); + PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); + PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); + DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE); +} + +static inline void uninit_pmu(void) +{ + PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE); + PPE_TC_PMU_SETUP(IFX_PMU_DISABLE); + PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE); + PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE); + PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE); + DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE); + //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); +} + +static inline void reset_ppe(void) +{ +#ifdef MODULE + // reset PPE + ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM); + udelay(1000); + ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM); + udelay(1000); + ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM); + udelay(1000); + *PP32_SRST &= ~0x000303CF; + udelay(1000); + *PP32_SRST |= 0x000303CF; + udelay(1000); +#endif +} + +static inline void init_pdma(void) +{ + IFX_REG_W32(0x08, PDMA_CFG); + IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG); + IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG); +} + +static inline void init_mailbox(void) +{ + IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); + IFX_REG_W32(0x00000000, MBOX_IGU1_IER); + IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); + IFX_REG_W32(0x00000000, MBOX_IGU3_IER); +} + +static inline void init_atm_tc(void) +{ + /* clear sync state */ + *SFSM_STATE0 = 0; + *SFSM_STATE1 = 0; + + /* enable keep IDLE */ +// *SFSM_CFG0 |= 1 << 15; +// *SFSM_CFG1 |= 1 << 15; +} + +static inline void clear_share_buffer(void) +{ + volatile u32 *p; + unsigned int i; + + p = SB_RAM0_ADDR(0); + for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ ) + IFX_REG_W32(0, p++); + + p = SB_RAM6_ADDR(0); + for ( i = 0; i < SB_RAM6_DWLEN; i++ ) + IFX_REG_W32(0, p++); +} + +/* + * Description: + * Download PPE firmware binary code. + * Input: + * pp32 --- int, which pp32 core + * src --- u32 *, binary code buffer + * dword_len --- unsigned int, binary code length in DWORD (32-bit) + * Output: + * int --- IFX_SUCCESS: Success + * else: Error Code + */ +static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +{ + unsigned int clr, set; + volatile u32 *dest; + + if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 + || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) + return IFX_ERROR; + + clr = pp32 ? 0xF0 : 0x0F; + if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) + set = pp32 ? (3 << 6): (2 << 2); + else + set = 0x00; + IFX_REG_W32_MASK(clr, set, CDM_CFG); + + /* copy code */ + dest = CDM_CODE_MEMORY(pp32, 0); + while ( code_dword_len-- > 0 ) + IFX_REG_W32(*code_src++, dest++); + + /* copy data */ + dest = CDM_DATA_MEMORY(pp32, 0); + while ( data_dword_len-- > 0 ) + IFX_REG_W32(*data_src++, dest++); + + return IFX_SUCCESS; +} + + + +/* + * #################################### + * Global Function + * #################################### + */ + +extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor) +{ + ASSERT(major != NULL, "pointer is NULL"); + ASSERT(minor != NULL, "pointer is NULL"); + +#ifdef VER_IN_FIRMWARE + *major = FW_VER_ID->major; + *minor = FW_VER_ID->minor; +#else + *major = ATM_FW_VER_MAJOR; + *minor = ATM_FW_VER_MINOR; +#endif +} + +void ifx_atm_init_chip(void) +{ + init_pmu(); + + reset_ppe(); + + init_pdma(); + + init_mailbox(); + + init_atm_tc(); + + clear_share_buffer(); +} + +void ifx_atm_uninit_chip(void) +{ + uninit_pmu(); +} + +/* + * Description: + * Initialize and start up PP32. + * Input: + * none + * Output: + * int --- IFX_SUCCESS: Success + * else: Error Code + */ +int ifx_pp32_start(int pp32) +{ + unsigned int mask = 1 << (pp32 << 4); + int ret; + + /* download firmware */ + ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data)); + if ( ret != IFX_SUCCESS ) + return ret; + + /* run PP32 */ + IFX_REG_W32_MASK(mask, 0, PP32_FREEZE); + + /* idle for a while to let PP32 init itself */ + udelay(10); + + return IFX_SUCCESS; +} + +/* + * Description: + * Halt PP32. + * Input: + * none + * Output: + * none + */ +void ifx_pp32_stop(int pp32) +{ + unsigned int mask = 1 << (pp32 << 4); + + /* halt PP32 */ + IFX_REG_W32_MASK(0, mask, PP32_FREEZE); +} diff --git a/package/ltq-dsl/src/ifxmips_compat.h b/package/ltq-dsl/src/ifxmips_compat.h index ae375b7e6f..bd357e98cf 100644 --- a/package/ltq-dsl/src/ifxmips_compat.h +++ b/package/ltq-dsl/src/ifxmips_compat.h @@ -15,6 +15,14 @@ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) +#define IFX_PP32_ETOP_CFG 0x16020 +#define IFX_PP32_ETOP_MDIO_CFG 0x11804 +#define IFX_PP32_ETOP_IG_PLEN_CTRL 0x16080 +#define IFX_PP32_ENET_MAC_CFG 0x1840 + +#define IFX_RCU_DOMAIN_PPE (1 << 8) +#define IFX_RCU_MODULE_ATM + #define IFX_PMU_ENABLE 1 #define IFX_PMU_DISABLE 0 @@ -40,4 +48,6 @@ #define CONFIG_IFXMIPS_DSL_CPE_MEI y +#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) + #endif diff --git a/package/ltq-dsl/src/ifxmips_mei_interface.h b/package/ltq-dsl/src/ifxmips_mei_interface.h index ffde6113c8..4ddc4c6aed 100644 --- a/package/ltq-dsl/src/ifxmips_mei_interface.h +++ b/package/ltq-dsl/src/ifxmips_mei_interface.h @@ -12,7 +12,9 @@ #ifndef IFXMIPS_MEI_H #define IFXMIPS_MEI_H -#define CONFIG_DANUBE 1 +//#define CONFIG_AMAZON_SE 1 +//#define CONFIG_DANUBE 1 +//#define CONFIG_AR9 1 #if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9) #error Platform undefined!!! diff --git a/package/ltq-dsl/src/lantiq_mei.c b/package/ltq-dsl/src/lantiq_mei.c index ac818929cc..aadb098c6d 100644 --- a/package/ltq-dsl/src/lantiq_mei.c +++ b/package/ltq-dsl/src/lantiq_mei.c @@ -1351,11 +1351,13 @@ IFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev) im2_register = (*LTQ_ICU_IM2_IER) & (1 << 20); /* Turn off irq */ #ifdef CONFIG_SOC_AMAZON_SE +#define IFXMIPS_USB_OC_INT0 (INT_NUM_IM4_IRL0 + 23) disable_irq (IFXMIPS_USB_OC_INT0); - disable_irq (IFXMIPS_USB_OC_INT2); - #elif defined(CONFIG_LANTIQ_AR9) +// disable_irq (IFXMIPS_USB_OC_INT2); + #elif defined(CONFIG_SOC_AR9) +#define IFXMIPS_USB_OC_INT0 (INT_NUM_IM4_IRL1 + 28) disable_irq (IFXMIPS_USB_OC_INT0); - disable_irq (IFXMIPS_USB_OC_INT2); +// disable_irq (IFXMIPS_USB_OC_INT2); #elif defined(CONFIG_SOC_XWAY) disable_irq (LTQ_USB_OC_INT); #else @@ -1369,10 +1371,10 @@ IFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev) #ifdef CONFIG_SOC_AMAZON_SE MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0); - MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2); - #elif defined(CONFIG_LANTIQ_AMAZON_S) +// MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2); + #elif defined(CONFIG_SOC_AR9) MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0); - MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2); +// MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2); #elif defined(CONFIG_SOC_XWAY) MEI_MASK_AND_ACK_IRQ (LTQ_USB_OC_INT); #else |