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| author | Felix Fietkau <nbd@openwrt.org> | 2010-03-28 22:40:32 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2010-03-28 22:40:32 +0000 |
| commit | e4490cccdd3145a019940213cc06d87e6468bdb4 (patch) | |
| tree | aa64a4eb197b91873d662ebd1b617b1a32bb3cc1 /package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S | |
| parent | b4197c908d09b9bd00e01d8ac6514709f5dc193e (diff) | |
| download | upstream-e4490cccdd3145a019940213cc06d87e6468bdb4.tar.gz upstream-e4490cccdd3145a019940213cc06d87e6468bdb4.tar.bz2 upstream-e4490cccdd3145a019940213cc06d87e6468bdb4.zip | |
add uboot-lantiq (based on a patch contributed by Lantiq)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20561 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S')
| -rw-r--r-- | package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S b/package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S new file mode 100644 index 0000000000..fc482dcd61 --- /dev/null +++ b/package/uboot-lantiq/files/cpu/mips/danube/ifx_cache.S @@ -0,0 +1,60 @@ + +#define IFX_CACHE_EXTRA_INVALID_TAG \ + mtc0 zero, CP0_TAGLO, 1; \ + mtc0 zero, CP0_TAGLO, 2; \ + mtc0 zero, CP0_TAGLO, 3; \ + mtc0 zero, CP0_TAGLO, 4; + +#define IFX_CACHE_EXTRA_OPERATION \ + /* set WST bit */ \ + mfc0 a0, CP0_ECC; \ + li a1, ECCF_WST; \ + or a0, a1; \ + mtc0 a0, CP0_ECC; \ + \ + li a0, K0BASE; \ + move a2, t2; /* icacheSize */ \ + move a3, t4; /* icacheLineSize */ \ + move a1, a2; \ + icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \ + \ + /* clear WST bit */ \ + mfc0 a0, CP0_ECC; \ + li a1, ~ECCF_WST; \ + and a0, a1; \ + mtc0 a0, CP0_ECC; \ + \ + /* 1: initialise dcache tags. */ \ + \ + /* cache line size */ \ + li a2, CFG_CACHELINE_SIZE; \ + /* kseg0 mem address */ \ + li a1, 0; \ + li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \ +1: \ + /* store tag (invalid, not locked) */ \ + cache 0x8, 0(a1); \ + cache 0x9, 0(a1); \ + \ + add a3, -1; \ + bne a3, zero, 1b; \ + add a1, a2; \ + \ + /* set WST bit */ \ + mfc0 a0, CP0_ECC; \ + li a1, ECCF_WST; \ + or a0, a1; \ + mtc0 a0, CP0_ECC; \ + \ + li a0, K0BASE; \ + move a2, t3; /* dcacheSize */ \ + move a3, t5; /* dcacheLineSize */ \ + move a1, a2; \ + icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \ + \ + /* clear WST bit */ \ + mfc0 a0, CP0_ECC; \ + li a1, ~ECCF_WST; \ + and a0, a1; \ + mtc0 a0, CP0_ECC; + |