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author | John Crispin <john@openwrt.org> | 2012-10-11 10:05:13 +0000 |
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committer | John Crispin <john@openwrt.org> | 2012-10-11 10:05:13 +0000 |
commit | a95775e4b2a9831decbc7f37a2e47985ea2ac222 (patch) | |
tree | 2a188f047a7da8e3868f734b26756551c9f7ec8e /package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h | |
parent | 06218a992e0ffa234d8c180f9a24415b2fb5fe62 (diff) | |
download | upstream-a95775e4b2a9831decbc7f37a2e47985ea2ac222.tar.gz upstream-a95775e4b2a9831decbc7f37a2e47985ea2ac222.tar.bz2 upstream-a95775e4b2a9831decbc7f37a2e47985ea2ac222.zip |
drop unmaintained packages
SVN-Revision: 33723
Diffstat (limited to 'package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h')
-rw-r--r-- | package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h deleted file mode 100644 index 7f87d43f76..0000000000 --- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr221_settings.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x306 -#define MC_DC7_VALUE 0x403 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x90c -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xf02 -#define MC_DC12_VALUE 0x2c8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x12f /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xc800 -#define MC_DC17_VALUE 0xf -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1500 -#define MC_DC22_VALUE 0x1515 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x57 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x6b8 -#define MC_DC29_VALUE 0x3c84 -#define MC_DC30_VALUE 0xace5 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x600 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 |