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author | Ralph Hempel <ralph.hempel@lantiq.com> | 2010-03-30 13:56:30 +0000 |
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committer | Ralph Hempel <ralph.hempel@lantiq.com> | 2010-03-30 13:56:30 +0000 |
commit | 046d73d3c2bc3a515024c2cc8339d1177e749b77 (patch) | |
tree | e6c0308590b8a125833f31549758973328c4f577 /package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h | |
parent | aa323e0134c4dd374869446738b701f82d014c89 (diff) | |
download | upstream-046d73d3c2bc3a515024c2cc8339d1177e749b77.tar.gz upstream-046d73d3c2bc3a515024c2cc8339d1177e749b77.tar.bz2 upstream-046d73d3c2bc3a515024c2cc8339d1177e749b77.zip |
add preliminary AR9 support attention: if caches enabled the network is broken attention: the network of the flash image doesn't work because of enabled caches
SVN-Revision: 20606
Diffstat (limited to 'package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h')
-rw-r--r-- | package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h new file mode 100644 index 0000000000..766f1e00da --- /dev/null +++ b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr111_settings.h @@ -0,0 +1,51 @@ +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ + +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x306 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0x139 /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0x2200 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x301 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1800 +#define MC_DC22_VALUE 0x1818 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x514 +#define MC_DC29_VALUE 0x2d93 +#define MC_DC30_VALUE 0x8235 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x600 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 |