Integrate new HAL release (by OpenWrt, DD-WRT, MakSat Technologies)

SVN-Revision: 12429

1 files changed, 135 insertions, 0 deletions

diff --git a/package/madwifi/patches/450-new_hal.patch b/package/madwifi/patches/450-new_hal.patch
new file mode 100644
index 0000000000..5171ce2784
--- /dev/null
+++ b/package/madwifi/patches/450-new_hal.patch
@@ -0,0 +1,135 @@
+--- a/ath_hal/ah_os.h
++++ b/ath_hal/ah_os.h
+@@ -156,80 +156,23 @@
+ #endif
+ #endif				/* AH_BYTE_ORDER */
+ 
+-/*
+- * Some big-endian architectures don't set CONFIG_GENERIC_IOMAP, but fail to
+- * implement iowrite32be and ioread32be.  Provide compatibility macros when
+- * it's needed.
+- *
+- * As of Linux 2.6.24, only MIPS, PARISC and PowerPC implement iowrite32be and
+- * ioread32be as functions.
+- *
+- * The downside or the replacement macros it that we may be byte-swapping data
+- * for the second time, so the native implementations should be preferred.
+- */
+-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) && \
+-	!defined(CONFIG_GENERIC_IOMAP) && (AH_BYTE_ORDER == AH_BIG_ENDIAN) && \
+-	!defined(__mips__) && !defined(__hppa__) && !defined(__powerpc__)
+-# ifndef iowrite32be
+-#  define iowrite32be(_val, _addr) iowrite32(swab32((_val)), (_addr))
+-# endif
+-# ifndef ioread32be
+-#  define ioread32be(_addr) swab32(ioread32((_addr)))
+-# endif
+-#endif
++#define IS_SWAPPED(_ah, _reg) \
++	((_ah)->ah_swapped && \
++		(((0x4000 <= (_reg)) && ((_reg) < 0x5000)) || \
++		 ((0x7000 <= (_reg)) && ((_reg) < 0x8000))))
++
++#define SWAPREG(_ah, _reg, _val) \
++	(IS_SWAPPED(_ah, _reg) ? cpu_to_le32(_val) : (_val))
+ 
+ /*
+  * The register accesses are done using target-specific functions when
+  * debugging is enabled (AH_DEBUG) or it's explicitly requested for the target.
+- *
+- * The hardware registers use little-endian byte order natively.  Big-endian
+- * systems are configured by HAL to enable hardware byte-swap of register reads
+- * and writes at reset.  This avoid the need to byte-swap the data in software.
+- * However, the registers in a certain area from 0x4000 to 0x4fff (PCI clock
+- * domain registers) are not byte swapped!
+- *
+- * Since Linux I/O primitives default to little-endian operations, we only
+- * need to suppress byte-swapping on big-endian systems outside the area used
+- * by the PCI clock domain registers.
+  */
+-#if (AH_BYTE_ORDER == AH_BIG_ENDIAN)
+-#define is_reg_le(__reg) ((0x4000 <= (__reg) && (__reg) < 0x5000))
+-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)
+-#define _OS_REG_WRITE(_ah, _reg, _val) do {			\
+-	 is_reg_le(_reg) ?					\
+-	 iowrite32((_val), (_ah)->ah_sh + (_reg)) :		\
+-	 iowrite32be((_val), (_ah)->ah_sh + (_reg));		\
+-	} while (0)
+-#define _OS_REG_READ(_ah, _reg)					\
+-	(is_reg_le(_reg) ?					\
+-	 ioread32((_ah)->ah_sh + (_reg)) :			\
+-	 ioread32be((_ah)->ah_sh + (_reg)))
+-#else
+-#define _OS_REG_WRITE(_ah, _reg, _val) do {			\
+-	 writel(is_reg_le(_reg) ? 				\
+-	 	(_val) : cpu_to_le32(_val), 			\
+-		(_ah)->ah_sh + (_reg));				\
+-	} while (0)
+-#define _OS_REG_READ(_ah, _reg)					\
+-	(is_reg_le(_reg) ?					\
+-	 readl((_ah)->ah_sh + (_reg)) :				\
+-	 cpu_to_le32(readl((_ah)->ah_sh + (_reg))))
+-#endif				/* KERNEL_VERSION(2,6,12) */
+-#else				/* AH_BYTE_ORDER != AH_BIG_ENDIAN */
+-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)
+-#define _OS_REG_WRITE(_ah, _reg, _val) do {			\
+-	 iowrite32((_val), (_ah)->ah_sh + (_reg));		\
+-	} while (0)
+-#define _OS_REG_READ(_ah, _reg)					\
+-	ioread32((_ah)->ah_sh + (_reg))
+-#else
+ #define _OS_REG_WRITE(_ah, _reg, _val) do {			\
+-	 writel((_val), (_ah)->ah_sh + (_reg));			\
+-	} while (0)
++	 __raw_writel(SWAPREG(_ah, _reg, _val), (_ah)->ah_sh + (_reg));		\
++} while (0)
+ #define _OS_REG_READ(_ah, _reg)					\
+-	readl((_ah)->ah_sh + (_reg))
+-#endif				/* KERNEL_VERSION(2,6,12) */
+-#endif				/* AH_BYTE_ORDER != AH_BIG_ENDIAN */
++	 SWAPREG(_ah, _reg, __raw_readl((_ah)->ah_sh + (_reg)))
+ 
+ /*
+  * The functions in this section are not intended to be invoked by MadWifi
+--- a/ath/if_ath.c
++++ b/ath/if_ath.c
+@@ -592,6 +592,14 @@
+ 	}
+ 	sc->sc_ah = ah;
+ 
++	/* WAR for AR7100 PCI bug */
++#ifdef CONFIG_ATHEROS_AR71XX
++	if ((ar_device(sc->devid) >= 5210) && (ar_device(sc->devid) < 5416)) {
++		ath_hal_setcapability(ah, HAL_CAP_DMABURST_RX, 0, HAL_DMABURST_4B, NULL);
++		ath_hal_setcapability(ah, HAL_CAP_DMABURST_TX, 0, HAL_DMABURST_4B, NULL);
++	}
++#endif
++
+ 	/*
+ 	 * Check if the MAC has multi-rate retry support.
+ 	 * We do this by trying to setup a fake extended
+@@ -7348,7 +7356,7 @@
+ 	if (qtype == HAL_TX_QUEUE_UAPSD)
+ 		qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
+ 	else
+-		qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 
++		qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXOKINT_ENABLE |
+ 			HAL_TXQ_TXDESCINT_ENABLE;
+ 	qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
+ 	if (qnum == -1) {
+--- a/ath_hal/ah_os.c
++++ b/ath_hal/ah_os.c
+@@ -126,6 +126,13 @@
+ }
+ EXPORT_SYMBOL(ath_hal_printf);
+ 
++void __ahdecl
++ath_hal_printstr(struct ath_hal *ah, const char *str)
++{
++	printk("%s", str);
++}
++EXPORT_SYMBOL(ath_hal_printstr);
++
+ /*
+  * Format an Ethernet MAC for printing.
+  */