diff options
author | Felix Fietkau <nbd@nbd.name> | 2016-10-08 13:53:14 +0200 |
---|---|---|
committer | Felix Fietkau <nbd@nbd.name> | 2016-10-13 17:06:03 +0200 |
commit | ad51e09fd1301484820a466a49447a34d7504882 (patch) | |
tree | 06d56b89cf8709b0e9ca63528f8efc411089ddf5 /package/kernel/mac80211/patches/653-0037-rtl8xxxu-Improve-register-description-for-REG_FPGA1_.patch | |
parent | 4379bcb1b4b73fb8487a14bec9554a17d4726e35 (diff) | |
download | upstream-ad51e09fd1301484820a466a49447a34d7504882.tar.gz upstream-ad51e09fd1301484820a466a49447a34d7504882.tar.bz2 upstream-ad51e09fd1301484820a466a49447a34d7504882.zip |
mac80211: update to wireless-testing 2016-10-08
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'package/kernel/mac80211/patches/653-0037-rtl8xxxu-Improve-register-description-for-REG_FPGA1_.patch')
-rw-r--r-- | package/kernel/mac80211/patches/653-0037-rtl8xxxu-Improve-register-description-for-REG_FPGA1_.patch | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/package/kernel/mac80211/patches/653-0037-rtl8xxxu-Improve-register-description-for-REG_FPGA1_.patch b/package/kernel/mac80211/patches/653-0037-rtl8xxxu-Improve-register-description-for-REG_FPGA1_.patch new file mode 100644 index 0000000000..bb940db3c8 --- /dev/null +++ b/package/kernel/mac80211/patches/653-0037-rtl8xxxu-Improve-register-description-for-REG_FPGA1_.patch @@ -0,0 +1,30 @@ +From 5731f8a7485120836c42e0dfae61644588ffd119 Mon Sep 17 00:00:00 2001 +From: Jes Sorensen <Jes.Sorensen@redhat.com> +Date: Fri, 29 Jul 2016 15:57:19 -0400 +Subject: [PATCH] rtl8xxxu: Improve register description for REG_FPGA1_TX_INFO + +This is based on Hal_SetAntenna() from the 8188eu driver + +Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> +--- + drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h +@@ -944,6 +944,15 @@ + #define REG_FPGA1_RF_MODE 0x0900 + + #define REG_FPGA1_TX_INFO 0x090c ++#define FPGA1_TX_ANT_MASK 0x0000000f ++#define FPGA1_TX_ANT_L_MASK 0x000000f0 ++#define FPGA1_TX_ANT_NON_HT_MASK 0x00000f00 ++#define FPGA1_TX_ANT_HT1_MASK 0x0000f000 ++#define FPGA1_TX_ANT_HT2_MASK 0x000f0000 ++#define FPGA1_TX_ANT_HT_S1_MASK 0x00f00000 ++#define FPGA1_TX_ANT_NON_HT_S1_MASK 0x0f000000 ++#define FPGA1_TX_OFDM_TXSC_MASK 0x30000000 ++ + #define REG_ANT_MAPPING1 0x0914 + #define REG_DPDT_CTRL 0x092c /* 8723BU */ + #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ |