diff options
| author | Felix Fietkau <nbd@nbd.name> | 2016-12-27 20:54:15 +0100 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2016-12-27 20:55:35 +0100 |
| commit | c9c68c717769a7560b46fd77d050b08ffb94f241 (patch) | |
| tree | d54fc861c2a807b50a466217edfecf8d1c6f27b3 /package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch | |
| parent | 6b524fe5b8c51fddbfe49d6bcde5f8f126992820 (diff) | |
| download | upstream-c9c68c717769a7560b46fd77d050b08ffb94f241.tar.gz upstream-c9c68c717769a7560b46fd77d050b08ffb94f241.tar.bz2 upstream-c9c68c717769a7560b46fd77d050b08ffb94f241.zip | |
ath9k: fix issues with external reset on AR913x
An external reset patch for AR955x accidentally led to external reset
being issued twice on AR913x, once before the RTC reset and once after.
This may be causing some stability issues.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch')
| -rw-r--r-- | package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch b/package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch index 6a958a4132..34d7d3b1cf 100644 --- a/package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch +++ b/package/kernel/mac80211/patches/315-ath9k_hw-issue-external-reset-for-QCA955x.patch @@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name> return true; } -@@ -1356,24 +1373,23 @@ static bool ath9k_hw_set_reset(struct at +@@ -1356,24 +1373,24 @@ static bool ath9k_hw_set_reset(struct at rst_flags |= AR_RTC_RC_MAC_COLD; } @@ -115,7 +115,8 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name> - REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); } -+ ath9k_hw_external_reset(ah, type); ++ if (!AR_SREV_9100(ah)) ++ ath9k_hw_external_reset(ah, type); + + if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) + REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); |