uboot-rockchip: add NanoPi R2C support

Add support for the FriendlyARM NanoPi R2C.
Manually generated of-platdata files to avoid swig dependency.

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>

6 files changed, 438 insertions, 2 deletions

diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile
index f27a3e0638..bdd1f5d5d8 100644
--- a/package/boot/uboot-rockchip/Makefile
+++ b/package/boot/uboot-rockchip/Makefile
@@ -31,6 +31,13 @@ define U-Boot/rk3328/Default
   OF_PLATDATA:=$(1)
 endef
 
+define U-Boot/nanopi-r2c-rk3328
+  $(U-Boot/rk3328/Default)
+  NAME:=NanoPi R2C
+  BUILD_DEVICES:= \
+    friendlyarm_nanopi-r2c
+endef
+
 define U-Boot/nanopi-r2s-rk3328
   $(U-Boot/rk3328/Default)
   NAME:=NanoPi R2S
@@ -78,6 +85,7 @@ UBOOT_TARGETS := \
   nanopi-r4s-rk3399 \
   rock-pi-4-rk3399 \
   rockpro64-rk3399 \
+  nanopi-r2c-rk3328 \
   nanopi-r2s-rk3328 \
   roc-cc-rk3328
 
diff --git a/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch b/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch
index f630818358..174c9ea29c 100644
--- a/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch
+++ b/package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch
@@ -17,9 +17,9 @@ Signed-off-by: Marty Jones <mj8263788@gmail.com>
 
 --- a/configs/rockpro64-rk3399_defconfig
 +++ b/configs/rockpro64-rk3399_defconfig
-@@ -12,7 +12,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
+@@ -12,7 +12,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
+ CONFIG_SPL_SPI_FLASH_SUPPORT=y
  CONFIG_SPL_SPI_SUPPORT=y
- CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
  CONFIG_DEBUG_UART=y
 -CONFIG_USE_PREBOOT=y
  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
diff --git a/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch b/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch
new file mode 100644
index 0000000000..bc450b0dd4
--- /dev/null
+++ b/package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch
@@ -0,0 +1,199 @@
+From 7000a609473ffe14d32c656cdd0ff3ca0d3ecbd7 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Tue, 11 Apr 2023 18:14:49 +0800
+Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
+
+The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
+chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
+
+The device tree is taken from the kernel linux-next branch:
+https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ arch/arm/dts/Makefile                      |   1 +
+ arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi |   3 +
+ arch/arm/dts/rk3328-nanopi-r2c.dts         |  40 ++++++++
+ board/rockchip/evb_rk3328/MAINTAINERS      |   6 ++
+ configs/nanopi-r2c-rk3328_defconfig        | 112 +++++++++++++++++++++
+ 5 files changed, 162 insertions(+)
+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts
+ create mode 100644 configs/nanopi-r2c-rk3328_defconfig
+
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+ 
+ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ 	rk3328-evb.dtb \
++	rk3328-nanopi-r2c.dtb \
+ 	rk3328-nanopi-r2s.dtb \
+ 	rk3328-roc-cc.dtb \
+ 	rk3328-rock64.dtb \
+--- /dev/null
++++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
+@@ -0,0 +1,3 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++
++#include "rk3328-nanopi-r2s-u-boot.dtsi"
+--- /dev/null
++++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
+@@ -0,0 +1,40 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3328-nanopi-r2s.dts"
++
++/ {
++	model = "FriendlyElec NanoPi R2C";
++	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
++};
++
++&gmac2io {
++	phy-handle = <&yt8521s>;
++	tx_delay = <0x22>;
++	rx_delay = <0x12>;
++
++	mdio {
++		/delete-node/ ethernet-phy@1;
++
++		yt8521s: ethernet-phy@3 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <3>;
++
++			motorcomm,clk-out-frequency-hz = <125000000>;
++			motorcomm,keep-pll-enabled;
++			motorcomm,auto-sleep-disabled;
++
++			pinctrl-0 = <&eth_phy_reset_pin>;
++			pinctrl-names = "default";
++			reset-assert-us = <10000>;
++			reset-deassert-us = <50000>;
++			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
+--- a/board/rockchip/evb_rk3328/MAINTAINERS
++++ b/board/rockchip/evb_rk3328/MAINTAINERS
+@@ -5,6 +5,12 @@ F:      board/rockchip/evb_rk3328
+ F:      include/configs/evb_rk3328.h
+ F:      configs/evb-rk3328_defconfig
+ 
++NANOPI-R2C-RK3328
++M:      Tianling Shen <cnsztl@gmail.com>
++S:      Maintained
++F:      configs/nanopi-r2c-rk3328_defconfig
++F:      arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
++
+ NANOPI-R2S-RK3328
+ M:      David Bauer <mail@david-bauer.net>
+ S:      Maintained
+--- /dev/null
++++ b/configs/nanopi-r2c-rk3328_defconfig
+@@ -0,0 +1,98 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO_SUPPORT=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
++CONFIG_ROCKCHIP_RK3328=y
++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
++CONFIG_TPL_LIBCOMMON_SUPPORT=y
++CONFIG_TPL_LIBGENERIC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
++CONFIG_SPL_STACK_R_ADDR=0x600000
++CONFIG_DEBUG_UART_BASE=0xFF130000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_DEBUG_UART=y
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_MISC_INIT_R=y
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_I2C_SUPPORT=y
++CONFIG_SPL_POWER_SUPPORT=y
++CONFIG_SPL_ATF=y
++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_TPL_OF_PLATDATA=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_TPL_DM=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_FASTBOOT_BUF_ADDR=0x800800
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_SF_DEFAULT_SPEED=20000000
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_DM_REGULATOR=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_SPL_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSINFO=y
++CONFIG_SYSRESET=y
++# CONFIG_TPL_SYSRESET is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_GENERIC=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_SPL_TINY_MEMSET=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y
diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h
new file mode 100644
index 0000000000..0919e4ed53
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h
@@ -0,0 +1,23 @@
+/*
+ * DO NOT MODIFY
+ *
+ * Declares externs for all device/uclass instances.
+ * This was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+/* driver declarations - these allow DM_DRIVER_GET() to be used */
+extern U_BOOT_DRIVER(rockchip_rk3328_cru);
+extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
+extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
+extern U_BOOT_DRIVER(ns16550_serial);
+extern U_BOOT_DRIVER(rockchip_rk3328_grf);
+
+/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
+extern UCLASS_DRIVER(clk);
+extern UCLASS_DRIVER(mmc);
+extern UCLASS_DRIVER(ram);
+extern UCLASS_DRIVER(serial);
+extern UCLASS_DRIVER(syscon);
diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c
new file mode 100644
index 0000000000..e5b330c9d9
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c
@@ -0,0 +1,155 @@
+/*
+ * DO NOT MODIFY
+ *
+ * Declares the U_BOOT_DRIVER() records and platform data.
+ * This was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+/* Allow use of U_BOOT_DRVINFO() in this file */
+#define DT_PLAT_C
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+/*
+ * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
+ *
+ * idx  driver_info          driver
+ * ---  -------------------- --------------------
+ *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
+ *   1: dmc                  rockchip_rk3328_dmc
+ *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
+ *   3: serial_at_ff130000   ns16550_serial
+ *   4: syscon_at_ff100000   rockchip_rk3328_grf
+ * ---  -------------------- --------------------
+ */
+
+/*
+ * Node /clock-controller@ff440000 index 0
+ * driver rockchip_rk3328_cru parent None
+ */
+static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
+	.reg			= {0xff440000, 0x1000},
+	.rockchip_grf		= 0x3a,
+};
+U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
+	.name		= "rockchip_rk3328_cru",
+	.plat		= &dtv_clock_controller_at_ff440000,
+	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
+	.parent_idx	= -1,
+};
+
+/*
+ * Node /dmc index 1
+ * driver rockchip_rk3328_dmc parent None
+ */
+static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
+	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
+		0xff720000, 0x1000, 0xff798000, 0x1000},
+	.rockchip_sdram_params	= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
+		0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
+		0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
+		0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
+		0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
+		0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
+		0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
+		0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
+		0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
+		0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
+		0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
+		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
+		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
+		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
+		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
+		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
+		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
+		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
+		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
+		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
+		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
+		0x77, 0x77, 0x79, 0x9},
+};
+U_BOOT_DRVINFO(dmc) = {
+	.name		= "rockchip_rk3328_dmc",
+	.plat		= &dtv_dmc,
+	.plat_size	= sizeof(dtv_dmc),
+	.parent_idx	= -1,
+};
+
+/*
+ * Node /mmc@ff500000 index 2
+ * driver rockchip_rk3288_dw_mshc parent None
+ */
+static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
+	.bus_width		= 0x4,
+	.cap_sd_highspeed	= true,
+	.clocks			= {
+			{0, {317}},
+			{0, {33}},
+			{0, {74}},
+			{0, {78}},},
+	.disable_wp		= true,
+	.fifo_depth		= 0x100,
+	.interrupts		= {0x0, 0xc, 0x4},
+	.max_frequency		= 0x8f0d180,
+	.pinctrl_0		= {0x47, 0x48, 0x49, 0x4a},
+	.pinctrl_names		= "default",
+	.reg			= {0xff500000, 0x4000},
+	.sd_uhs_sdr104		= true,
+	.sd_uhs_sdr12		= true,
+	.sd_uhs_sdr25		= true,
+	.sd_uhs_sdr50		= true,
+	.u_boot_spl_fifo_mode	= true,
+	.vmmc_supply		= 0x4b,
+	.vqmmc_supply		= 0x1e,
+};
+U_BOOT_DRVINFO(mmc_at_ff500000) = {
+	.name		= "rockchip_rk3288_dw_mshc",
+	.plat		= &dtv_mmc_at_ff500000,
+	.plat_size	= sizeof(dtv_mmc_at_ff500000),
+	.parent_idx	= -1,
+};
+
+/*
+ * Node /serial@ff130000 index 3
+ * driver ns16550_serial parent None
+ */
+static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
+	.clock_frequency	= 0x16e3600,
+	.clocks			= {
+			{0, {40}},
+			{0, {212}},},
+	.dma_names		= {"tx", "rx"},
+	.dmas			= {0x10, 0x6, 0x10, 0x7},
+	.interrupts		= {0x0, 0x39, 0x4},
+	.pinctrl_0		= 0x26,
+	.pinctrl_names		= "default",
+	.reg			= {0xff130000, 0x100},
+	.reg_io_width		= 0x4,
+	.reg_shift		= 0x2,
+};
+U_BOOT_DRVINFO(serial_at_ff130000) = {
+	.name		= "ns16550_serial",
+	.plat		= &dtv_serial_at_ff130000,
+	.plat_size	= sizeof(dtv_serial_at_ff130000),
+	.parent_idx	= -1,
+};
+
+/*
+ * Node /syscon@ff100000 index 4
+ * driver rockchip_rk3328_grf parent None
+ */
+static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
+	.reg			= {0xff100000, 0x1000},
+};
+U_BOOT_DRVINFO(syscon_at_ff100000) = {
+	.name		= "rockchip_rk3328_grf",
+	.plat		= &dtv_syscon_at_ff100000,
+	.plat_size	= sizeof(dtv_syscon_at_ff100000),
+	.parent_idx	= -1,
+};
+
diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h
new file mode 100644
index 0000000000..b1ff08a927
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h
@@ -0,0 +1,51 @@
+/*
+ * DO NOT MODIFY
+ *
+ * Defines the structs used to hold devicetree data.
+ * This was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <stdbool.h>
+#include <linux/libfdt.h>
+struct dtd_ns16550_serial {
+	fdt32_t		clock_frequency;
+	struct phandle_1_arg clocks[2];
+	const char *	dma_names[2];
+	fdt32_t		dmas[4];
+	fdt32_t		interrupts[3];
+	fdt32_t		pinctrl_0;
+	const char *	pinctrl_names;
+	fdt64_t		reg[2];
+	fdt32_t		reg_io_width;
+	fdt32_t		reg_shift;
+};
+struct dtd_rockchip_rk3288_dw_mshc {
+	fdt32_t		bus_width;
+	bool		cap_sd_highspeed;
+	struct phandle_1_arg clocks[4];
+	bool		disable_wp;
+	fdt32_t		fifo_depth;
+	fdt32_t		interrupts[3];
+	fdt32_t		max_frequency;
+	fdt32_t		pinctrl_0[4];
+	const char *	pinctrl_names;
+	fdt64_t		reg[2];
+	bool		sd_uhs_sdr104;
+	bool		sd_uhs_sdr12;
+	bool		sd_uhs_sdr25;
+	bool		sd_uhs_sdr50;
+	bool		u_boot_spl_fifo_mode;
+	fdt32_t		vmmc_supply;
+	fdt32_t		vqmmc_supply;
+};
+struct dtd_rockchip_rk3328_cru {
+	fdt64_t		reg[2];
+	fdt32_t		rockchip_grf;
+};
+struct dtd_rockchip_rk3328_dmc {
+	fdt64_t		reg[12];
+	fdt32_t		rockchip_sdram_params[196];
+};
+struct dtd_rockchip_rk3328_grf {
+	fdt64_t		reg[2];
+};