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| author | Jo-Philipp Wich <jo@mein.io> | 2016-10-31 20:19:27 +0100 |
|---|---|---|
| committer | Jo-Philipp Wich <jo@mein.io> | 2016-11-02 02:11:19 +0100 |
| commit | 7a5897268008a85c3843ae522b2b274911a9eec0 (patch) | |
| tree | 63fb9c4aecb720286599da6dbfe4816b6b319932 /package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch | |
| parent | 12d15fa8a5096913927d75958d0ed3af9d963e73 (diff) | |
| download | upstream-7a5897268008a85c3843ae522b2b274911a9eec0.tar.gz upstream-7a5897268008a85c3843ae522b2b274911a9eec0.tar.bz2 upstream-7a5897268008a85c3843ae522b2b274911a9eec0.zip | |
uboot-sunxi: fix default config for OLIMEX A13 SOM (FS#239)
The current uboot default config for the A13 SOM erroneously enables support
for the AXP209 power regulator IC which is not present on the board.
This superfluous support module sets an incorrect initial clock frequency and
confuses the kernel, ultimately leading to a boot failure later on.
Properly disable the PMIC support and enable the EHCI support by translating
the deprecated SYS_EXTRA_OPTIONS values into proper SUNXI_NO_PMIC and
USB_EHCI_HCD symbols respectively.
Also rename 002-add-olimex-a13-som.diff to 002-add-olimex-a13-som.patch and
refresh the remaining patches of the series while we're at it.
Reported-by: Mario Fischer <mario-fischer@web.de>
Signed-off-by: Jo-Philipp Wich <jo@mein.io>
Diffstat (limited to 'package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch')
| -rw-r--r-- | package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch b/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch index e6af765cae..d200633bc2 100644 --- a/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch +++ b/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch @@ -16,8 +16,6 @@ order of magnitude as Boot1. Furthermore, a bit of documentation is added to clarify that the required setting for the PLL LDO is 1.37v as per the A31 manual. -diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -index fa7ebd8..3a6e56e 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -24,14 +24,27 @@ void clock_init_safe(void) @@ -49,9 +47,7 @@ index fa7ebd8..3a6e56e 100644 + clock_set_pll1(408000000); - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); -diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h -index 82ed541..41a62a4 100644 + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -111,13 +111,13 @@ @@ -72,6 +68,3 @@ index 82ed541..41a62a4 100644 __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) --- -cgit v0.10.2 - |