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authorZoltan Herpai <wigyori@uid0.hu>2016-03-29 11:42:14 +0000
committerZoltan Herpai <wigyori@uid0.hu>2016-03-29 11:42:14 +0000
commit2d4ebff3ad9b298837782b790ac5aea941c2a255 (patch)
tree8febe14ffb923147afec2dfe978760bfbc9882a2 /package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
parentd1aa4bfe1ddd52c52eb6314155245121078399a1 (diff)
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package: uboot-sunxi: various changes - bump to 2016.03 - add bugfixes related to 2016.03 update - sync DTS files with mainline - add support for non-standard uEnv.txt - add initial support for Theobroma A31-yQ7 devboard
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 49089
Diffstat (limited to 'package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch')
-rw-r--r--package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch37
1 files changed, 37 insertions, 0 deletions
diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
new file mode 100644
index 0000000000..f782994c14
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
@@ -0,0 +1,37 @@
+From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001
+From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+Date: Tue, 6 Jan 2015 15:47:18 +0100
+Subject: sun6i: Sync PLL1 multipliers/dividers with Boot1
+
+This change syncs up the multipliers and dividers used to initialize
+PLL1 (i.e. the fast clock driving the ARM cores) with the values used
+in Allwinner's Boot1 on sun6i.
+
+More specifically, the following settings are now used:
+ * up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
+ * up to 1152MHz: mul=3, div=2 (unchanged)
+ * above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
+
+diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+index cfb32b4..2986539 100644
+--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
++++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+@@ -102,11 +102,12 @@ void clock_set_pll1(unsigned int clk)
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int p = 0;
+- int k = 1;
+- int m = 1;
++ int k = 2;
++ int m = 2;
+
+ if (clk > 1152000000) {
+- k = 2;
++ k = 4;
++ m = 2;
+ } else if (clk > 768000000) {
+ k = 3;
+ m = 2;
+--
+cgit v0.10.2
+