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authorZoltan HERPAI <wigyori@uid0.hu>2014-02-05 08:39:38 +0000
committerZoltan HERPAI <wigyori@uid0.hu>2014-02-05 08:39:38 +0000
commit1dd76f71e1aa7e8dae83aed641ac527ac4f8fadd (patch)
tree0c06b702d571236b493152e45dbef0cea16cdba3 /package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch
parent7e030364412f90713c37819ed75b85cace1e371f (diff)
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uboot-sunxi: various fixes
- update A10-Lime support - fix MMC on sun5i with initializing PLL6 correctly Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39470 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch')
-rw-r--r--package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch33
1 files changed, 33 insertions, 0 deletions
diff --git a/package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch b/package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch
new file mode 100644
index 0000000000..3300f42bf9
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/003-sun5i-tweak-pll6-init-value.patch
@@ -0,0 +1,33 @@
+From 8f70a049daa30be894158411439a36f920f0d11c Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Wed, 15 Jan 2014 20:13:04 +0100
+Subject: [PATCH] sun5i: Tweak pll6 init value
+
+There are multiple ways to get 600 MHz from PLL6, the sun5i ccmu is very
+similar to the sun4i and sun7i ccmu.
+
+This commit changes the PLL6 initialization we do for sun5i to make the PLL6
+reg value match that of sun4i and sun7i. This also makes it closer to the
+sun5i power on default, as we are now only changing the K-factor from 3 to 1.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ arch/arm/cpu/armv7/sunxi/clock.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
+index b9dd608..54b8753 100644
+--- a/arch/arm/cpu/armv7/sunxi/clock.c
++++ b/arch/arm/cpu/armv7/sunxi/clock.c
+@@ -46,7 +46,7 @@ static void clock_init_safe(void)
+ #ifdef CONFIG_SUN5I
+ /* Power on reset default for PLL6 is 2400 MHz, which is faster then
+ * it can reliable do :| Set it to a 600 MHz instead. */
+- writel(0x21009900, &ccm->pll6_cfg);
++ writel(0x21009911, &ccm->pll6_cfg);
+ #endif
+ #ifdef CONFIG_SUN7I
+ writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
+--
+1.8.5.1
+