add uboot-oxnas

This adds support for the oxnas target in U-Boot 2014.04
History can be found at https://github.com/kref/u-boot-oxnas up to 2013.10
changes from 2013.10 to 2014.04 can be followed at
https://gitorious.org/openwrt-oxnas

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

SVN-Revision: 43389

7 files changed, 1155 insertions, 0 deletions

diff --git a/package/boot/uboot-oxnas/files/board/ox820/Makefile b/package/boot/uboot-oxnas/files/board/ox820/Makefile
new file mode 100644
index 0000000000..445fc4c7da
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/board/ox820/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ox820.o
+obj-y += lowlevel_init.o
+
+obj-$(CONFIG_SPL_BUILD) += spl_start.o
+obj-$(CONFIG_SPL_BUILD) += ddr.o
+
diff --git a/package/boot/uboot-oxnas/files/board/ox820/ddr.c b/package/boot/uboot-oxnas/files/board/ox820/ddr.c
new file mode 100755
index 0000000000..a665722e3b
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/board/ox820/ddr.c
@@ -0,0 +1,477 @@
+/*******************************************************************
+ *
+ * File:            ddr_oxsemi.c
+ *
+ * Description:     Declarations for DDR routines and data objects
+ *
+ * Author:          Julien Margetts
+ *
+ * Copyright:       Oxford Semiconductor Ltd, 2009
+ */
+#include <common.h>
+#include <asm/arch/clock.h>
+
+#include "ddr.h"
+
+typedef unsigned int UINT;
+
+// DDR TIMING PARAMETERS
+typedef struct {
+	unsigned int holdoff_cmd_A;
+	unsigned int holdoff_cmd_ARW;
+	unsigned int holdoff_cmd_N;
+	unsigned int holdoff_cmd_LM;
+	unsigned int holdoff_cmd_R;
+	unsigned int holdoff_cmd_W;
+	unsigned int holdoff_cmd_PC;
+	unsigned int holdoff_cmd_RF;
+	unsigned int holdoff_bank_R;
+	unsigned int holdoff_bank_W;
+	unsigned int holdoff_dir_RW;
+	unsigned int holdoff_dir_WR;
+	unsigned int holdoff_FAW;
+	unsigned int latency_CAS;
+	unsigned int latency_WL;
+	unsigned int recovery_WR;
+	unsigned int width_update;
+	unsigned int odt_offset;
+	unsigned int odt_drive_all;
+	unsigned int use_fixed_re;
+	unsigned int delay_wr_to_re;
+	unsigned int wr_slave_ratio;
+	unsigned int rd_slave_ratio0;
+	unsigned int rd_slave_ratio1;
+} T_DDR_TIMING_PARAMETERS;
+
+// DDR CONFIG PARAMETERS
+
+typedef struct {
+	unsigned int ddr_mode;
+	unsigned int width;
+	unsigned int blocs;
+	unsigned int banks8;
+	unsigned int rams;
+	unsigned int asize;
+	unsigned int speed;
+	unsigned int cmd_mode_wr_cl_bl;
+} T_DDR_CONFIG_PARAMETERS;
+
+//cmd_mode_wr_cl_bl
+//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
+//else       cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
+
+//                                                            cmd_                    bank_ dir_     lat_  rec_ width_ odt_   odt_ fix delay     ratio
+//                                                                A                                F  C         update offset all  re  re_to_we  w  r0  r1
+//                                                                R     L        P  R        R  W  A  A  W  W
+//Timing Parameters                                            A  W  N  M  R  W  C  F  R  W  W  R  W  S  L  R
+static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,
+	5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.
+static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,
+	5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };
+static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,
+	4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)
+
+//                                                          D     B  B  R  A   S
+//                                                          D  W  L  K  A  S   P
+//Config Parameters                                         R  D  C  8  M  Z   D CMD_MODE
+//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5  = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte
+static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,
+	25, 0x80200A53 }; // 128 MByte
+static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,
+	25, 0x80200A63 }; // 256 MByte
+
+static void ddr_phy_poll_until_locked(void)
+{
+	volatile UINT reg_tmp = 0;
+	volatile UINT locked = 0;
+
+	//Extra read to put in delay before starting to poll...
+	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read
+
+	//POLL C_DDR_PHY2_REG register until clock and flock
+	//!!! Ideally have a timeout on this.
+	while (locked == 0) {
+		reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read
+
+		//locked when bits 30 and 31 are set
+		if (reg_tmp & 0xC0000000) {
+			locked = 1;
+		}
+	}
+}
+
+static void ddr_poll_until_not_busy(void)
+{
+	volatile UINT reg_tmp = 0;
+	volatile UINT busy = 1;
+
+	//Extra read to put in delay before starting to poll...
+	reg_tmp = *(volatile UINT *) C_DDR_STAT_REG;      // read
+
+	//POLL DDR_STAT register until no longer busy
+	//!!! Ideally have a timeout on this.
+	while (busy == 1) {
+		reg_tmp = *(volatile UINT *) C_DDR_STAT_REG;      // read
+
+		//when bit 31 is clear - core is no longer busy
+		if ((reg_tmp & 0x80000000) == 0x00000000) {
+			busy = 0;
+		}
+	}
+}
+
+static void ddr_issue_command(int commmand)
+{
+	*(volatile UINT *) C_DDR_CMD_REG = commmand;
+	ddr_poll_until_not_busy();
+}
+
+static void ddr_timing_initialisation(
+	const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)
+{
+	volatile UINT reg_tmp = 0;
+	/* update the DDR controller registers for timing parameters */
+	reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);
+	*(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;
+
+	reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);
+	*(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;
+
+	reg_tmp = (ddr_timing_parameters->latency_CAS << 0);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);
+	reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);
+
+	*(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;
+
+	/* Program the timing parameters in the PHY too */
+	reg_tmp = (ddr_timing_parameters->use_fixed_re << 16)
+			| (ddr_timing_parameters->delay_wr_to_re << 8)
+			| (ddr_timing_parameters->latency_WL << 4)
+			| (ddr_timing_parameters->latency_CAS << 0);
+
+	*(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;
+
+	reg_tmp = ddr_timing_parameters->wr_slave_ratio;
+
+	*(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;
+
+	reg_tmp = ddr_timing_parameters->rd_slave_ratio0;
+	reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;
+
+	*(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;
+
+}
+
+static void ddr_normal_initialisation(
+	const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)
+{
+	int i;
+	volatile UINT tmp = 0;
+	volatile UINT reg_tmp = 0;
+	volatile UINT emr_cmd = 0;
+	UINT refresh;
+
+	//Total size of memory in Mbits...
+	tmp = ddr_config_parameters->rams * ddr_config_parameters->asize
+		* ddr_config_parameters->width;
+	//Deduce value to program into DDR_CFG register...
+	switch (tmp) {
+	case 16:
+		reg_tmp = 0x00020000 * 1;
+		break;
+	case 32:
+		reg_tmp = 0x00020000 * 2;
+		break;
+	case 64:
+		reg_tmp = 0x00020000 * 3;
+		break;
+	case 128:
+		reg_tmp = 0x00020000 * 4;
+		break;
+	case 256:
+		reg_tmp = 0x00020000 * 5;
+		break;
+	case 512:
+		reg_tmp = 0x00020000 * 6;
+		break;
+	case 1024:
+		reg_tmp = 0x00020000 * 7;
+		break;
+	case 2048:
+		reg_tmp = 0x00020000 * 8;
+		break;
+	default:
+		reg_tmp = 0; //forces sims not to work if badly configured
+	}
+
+	//Memory width
+	tmp = ddr_config_parameters->rams * ddr_config_parameters->width;
+	switch (tmp) {
+	case 8:
+		reg_tmp = reg_tmp + 0x00400000;
+		break;
+	case 16:
+		reg_tmp = reg_tmp + 0x00200000;
+		break;
+	case 32:
+		reg_tmp = reg_tmp + 0x00000000;
+		break;
+	default:
+		reg_tmp = 0; //forces sims not to work if badly configured
+	}
+
+	//Setup DDR Mode
+	switch (ddr_config_parameters->ddr_mode) {
+	case 0:
+		reg_tmp = reg_tmp + 0x00000000;
+		break;   //SDR
+	case 1:
+		reg_tmp = reg_tmp + 0x40000000;
+		break;   //DDR
+	case 2:
+		reg_tmp = reg_tmp + 0x80000000;
+		break;   //DDR2
+	default:
+		reg_tmp = 0; //forces sims not to work if badly configured
+	}
+
+	//Setup Banks
+	if (ddr_config_parameters->banks8 == 1) {
+		reg_tmp = reg_tmp + 0x00800000;
+	}
+
+	//Program DDR_CFG register...
+	*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
+
+	//Configure PHY0 reg - se_mode is bit 1,
+	//needs to be 1 for DDR (single_ended drive)
+	switch (ddr_config_parameters->ddr_mode) {
+	case 0:
+		reg_tmp = 2 + (0 << 4);
+		break;   //SDR
+	case 1:
+		reg_tmp = 2 + (4 << 4);
+		break;   //DDR
+	case 2:
+		reg_tmp = 0 + (4 << 4);
+		break;   //DDR2
+	default:
+		reg_tmp = 0;
+	}
+
+	//Program DDR_PHY0 register...
+	*(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;
+
+	//Read DDR_PHY* registers to exercise paths for vcd
+	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;
+	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;
+	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;
+	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;
+
+	//Start up sequences - Different dependant on DDR mode
+	switch (ddr_config_parameters->ddr_mode) {
+	case 2:   //DDR2
+		//Start-up sequence: follows procedure described in Micron datasheet.
+		//start up DDR PHY DLL
+		reg_tmp = 0x00022828;       // dll on, start point and inc = h28
+		*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
+
+		reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28
+		*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
+
+		ddr_phy_poll_until_locked();
+
+		udelay(200);   //200us
+
+		//Startup SDRAM...
+		//!!! Software: CK should be running for 200us before wake-up
+		ddr_issue_command( C_CMD_WAKE_UP);
+		ddr_issue_command( C_CMD_NOP);
+		ddr_issue_command( C_CMD_PRECHARGE_ALL);
+		ddr_issue_command( C_CMD_DDR2_EMR2);
+		ddr_issue_command( C_CMD_DDR2_EMR3);
+
+		emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE
+			+ C_CMD_ENABLE_DLL;
+
+		ddr_issue_command(emr_cmd);
+		//Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...
+		udelay(1);   //1us
+		ddr_issue_command(
+			ddr_config_parameters->cmd_mode_wr_cl_bl
+			+ C_CMD_RESET_DLL);
+		udelay(1);   //1us
+
+		//!!! Software: Wait 200 CK cycles before...
+		//for(i=1; i<=2; i++) {
+		ddr_issue_command(C_CMD_PRECHARGE_ALL);
+		// !!! Software: Wait here at least 8 CK cycles
+		//}
+		//need a wait here to ensure PHY DLL lock before the refresh is issued
+		udelay(1);   //1us
+		for (i = 1; i <= 2; i++) {
+			ddr_issue_command( C_CMD_AUTO_REFRESH);
+			//!!! Software: Wait here at least 8 CK cycles to satify tRFC
+			udelay(1);   //1us
+		}
+		//As before but without 'RESET_DLL' bit set...
+		ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);
+		udelay(1);   //1us
+		// OCD commands
+		ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);
+		ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);
+		break;
+
+	default:
+		break;  //Do nothing
+	}
+
+	//Enable auto-refresh
+
+	// 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us
+	// We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles
+	// Our core now does 8 refreshes in a go, so we multiply this period by 8
+
+	refresh = (64000 * mhz) / 8192; // Refresh period in clocks
+
+	reg_tmp = *(volatile UINT *) C_DDR_CFG_REG;      // read
+#ifdef BURST_REFRESH_ENABLE
+	reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);
+	reg_tmp |= C_CFG_BURST_REFRESH_ENABLE;
+#else
+	reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);
+	reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;
+#endif
+	*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
+
+	//Verify register contents
+	reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read
+	//printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX");
+	//TBD   Check_data (read_data,  dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass);
+	reg_tmp = *(volatile UINT *) C_DDR_CFG_REG;      // read
+	//TBD   Check_data (read_data,  cfg_reg, "Error: bad DDR_CFG read", tb_pass);
+
+	//disable optimised wrapping
+	if (ddr_config_parameters->ddr_mode == 2) {
+		reg_tmp = 0xFFFF0000;
+		*(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;
+	}
+
+	//enable midbuffer followon
+	reg_tmp = *(volatile UINT *) C_DDR_ARB_REG;      // read
+	reg_tmp = 0xFFFF0000 | reg_tmp;
+	*(volatile UINT *) C_DDR_ARB_REG = reg_tmp;
+
+	// Enable write behind coherency checking for all clients
+
+	reg_tmp = 0xFFFF0000;
+	*(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;
+
+	//Wait for 200 clock cycles for SDRAM DLL to lock...
+	udelay(1);   //1us
+}
+
+// Function used to Setup DDR core
+
+void ddr_setup(int mhz)
+{
+	static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =
+		&C_TP_DDR2_25_CL6_1GB;
+	static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =
+		&C_CP_DDR2_25_CL6;
+
+	//Bring core out of Reset
+	*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;
+
+	//DDR TIMING INITIALISTION
+	ddr_timing_initialisation(ddr_timing_parameters);
+
+	//DDR NORMAL INITIALISATION
+	ddr_normal_initialisation(ddr_config_parameters, mhz);
+
+	// route all writes through one client
+	*(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0
+		<< DDR_ROUTE_CPU0_INSTR_SHIFT)
+		| (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)
+		| (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)
+		| (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)
+		| (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)
+		| (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);
+
+	//Bring all clients out of reset
+	*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;
+
+}
+
+void set_ddr_timing(unsigned int w, unsigned int i)
+{
+	unsigned int reg;
+	unsigned int wnow = 16;
+	unsigned int inow = 32;
+
+	/* reset all timing controls to known value (31) */
+	writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
+	writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,
+	       DDR_PHY_TIMING);
+	writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
+
+	/* step up or down read delay to the requested value */
+	while (wnow != w) {
+		if (wnow < w) {
+			reg = DDR_PHY_TIMING_INC;
+			wnow++;
+		} else {
+			reg = 0;
+			wnow--;
+		}
+		writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
+		writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,
+		       DDR_PHY_TIMING);
+		writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
+	}
+
+	/* now write delay */
+	while (inow != i) {
+		if (inow < i) {
+			reg = DDR_PHY_TIMING_INC;
+			inow++;
+		} else {
+			reg = 0;
+			inow--;
+		}
+		writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
+		writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,
+		       DDR_PHY_TIMING);
+		writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
+	}
+}
+
+//Function used to Setup SDRAM in DDR/SDR mode
+void init_ddr(int mhz)
+{
+	/* start clocks */
+	enable_clock(SYS_CTRL_CLK_DDRPHY);
+	enable_clock(SYS_CTRL_CLK_DDR);
+	enable_clock(SYS_CTRL_CLK_DDRCK);
+
+	/* bring phy and core out of reset */
+	reset_block(SYS_CTRL_RST_DDR_PHY, 0);
+	reset_block(SYS_CTRL_RST_DDR, 0);
+
+	/* DDR runs at half the speed of the CPU */
+	ddr_setup(mhz >> 1);
+	return;
+}
diff --git a/package/boot/uboot-oxnas/files/board/ox820/ddr.h b/package/boot/uboot-oxnas/files/board/ox820/ddr.h
new file mode 100644
index 0000000000..a3c199019c
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/board/ox820/ddr.h
@@ -0,0 +1,148 @@
+/*******************************************************************
+*
+* File:			ddr_oxsemi.h
+*
+* Description:		Declarations for DDR routines and data objects
+*
+* Author:		Julien Margetts
+*
+* Copyright:		Oxford Semiconductor Ltd, 2009
+*/
+
+void ddr_oxsemi_setup(int mhz);
+
+/* define to refresh in bursts of 8 */
+#define BURST_REFRESH_ENABLE
+
+#define DDR_BASE			0x44700000
+
+#define C_DDR_CFG_REG			(DDR_BASE + 0x00)
+#define C_CFG_DDR			0x80000000
+#define C_CFG_SDR			0x00000000
+#define C_CFG_WIDTH8			0x00200000
+#define C_CFG_WIDTH16			0x00100000
+#define C_CFG_WIDTH32			0x00000000
+#define C_CFG_SIZE_FACTOR		0x00020000
+#define C_CFG_REFRESH_ENABLE		0x00010000
+#define C_CFG_BURST_REFRESH_ENABLE	0x01000000
+#define C_CFG_SIZE(x)			(x << 17)
+#define CFG_SIZE_2MB			1
+#define CFG_SIZE_4MB			2
+#define CFG_SIZE_8MB			3
+#define CFG_SIZE_16MB			4
+#define CFG_SIZE_32MB			5
+#define CFG_SIZE_64MB			6
+#define CFG_SIZE_128MB			7
+
+#define C_DDR_BLKEN_REG			(DDR_BASE + 0x04)
+#define C_BLKEN_DDR_ON			0x80000000
+
+#define C_DDR_STAT_REG			(DDR_BASE + 0x08)
+
+#define C_DDR_CMD_REG			(DDR_BASE + 0x0C)
+#define C_CMD_SEND_COMMAND		(1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates
+#define C_CMD_WAKE_UP			0x80FC0000 // Asserts CKE
+#define C_CMD_MODE_SDR			0x80200022 // Sets CL=2 BL=4
+#define C_CMD_MODE_DDR			0x80200063 // Sets CL=2.5 BL=8
+#define C_CMD_RESET_DLL			0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR
+#define C_CMD_PRECHARGE_ALL		0x80280400
+#define C_CMD_AUTO_REFRESH		0x80240000
+#define C_CMD_SELF_REFRESH		0x80040000 // As AUTO-REFRESH but with CKE low
+#define C_CMD_NOP			0x803C0000 // NOP just to insert guaranteed delay
+#define C_CMD_DDR2_EMR1			0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set
+//#define C_CMD_DDR2_EMR1		0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set
+#define C_CMD_ENABLE_DLL		0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1
+#define C_CMD_DISABLE_DLL		0x00000001
+#define C_CMD_REDUCED_DRIVE		0x00000002
+#define C_CMD_ODT_DISABLED		0x00000000
+#define C_CMD_ODT_50			0x00000044
+#define C_CMD_ODT_75			0x00000004
+#define C_CMD_ODT_150			0x00000040
+#define C_CMD_MODE_DDR2_OCD_DFLT	0x00000380
+#define C_CMD_MODE_DDR2_OCD_EXIT	0x00000000
+
+#define C_CMD_DDR2_EMR2			0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set
+#define C_CMD_DDR2_EMR3			0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set
+
+#define C_DDR_AHB_REG			(DDR_BASE + 0x10)
+#define C_AHB_NO_RCACHES		0xFFFF0000
+#define C_AHB_FLUSH_ALL_RCACHES		0x0000FFFF
+#define C_AHB_FLUSH_AHB0_RCACHE		0x00000001
+#define C_AHB_FLUSH_AHB1_RCACHE		0x00000002
+
+#define C_DDR_DLL_REG			(DDR_BASE + 0x14)
+#define C_DLL_DISABLED			0x00000000
+#define C_DLL_MANUAL			0x80000000
+#define C_DLL_AUTO_OFFSET		0xA0000000
+#define C_DLL_AUTO_IN_REFRESH		0xC0000000
+#define C_DLL_AUTOMATIC			0xE0000000
+
+#define C_DDR_MON_REG			(DDR_BASE + 0x18)
+#define C_MON_ALL			0x00000010
+#define C_MON_CLIENT			0x00000000
+
+#define C_DDR_DIAG_REG			(DDR_BASE + 0x1C)
+#define C_DDR_DIAG2_REG			(DDR_BASE + 0x20)
+
+#define C_DDR_IOC_REG			(DDR_BASE + 0x24)
+#define C_DDR_IOC_PWR_DWN		(1 << 10)
+#define C_DDR_IOC_SEL_SSTL		(1 << 9)
+#define C_DDR_IOC_CK_DRIVE(x)		((x) << 6)
+#define C_DDR_IOC_DQ_DRIVE(x)		((x) << 3)
+#define C_DDR_IOC_XX_DRIVE(x)		((x) << 0)
+
+#define C_DDR_ARB_REG			(DDR_BASE + 0x28)
+#define C_DDR_ARB_MIDBUF		(1 << 4)
+#define C_DDR_ARB_LRUBANK		(1 << 3)
+#define C_DDR_ARB_REQAGE		(1 << 2)
+#define C_DDR_ARB_DATDIR		(1 << 1)
+#define C_DDR_ARB_DATDIR_NC		(1 << 0)
+
+#define C_TOP_ADDRESS_BIT_TEST		22
+#define C_MEM_BASE			C_SDRAM_BASE
+
+#define C_MEM_TEST_BASE			0
+#define C_MEM_TEST_LEN			1920
+#define C_MAX_RAND_ACCESS_LEN		16
+
+#define C_DDR_REG_IGNORE		(DDR_BASE + 0x2C)
+#define C_DDR_AHB4_REG			(DDR_BASE + 0x44)
+
+#define C_DDR_REG_TIMING0		(DDR_BASE + 0x34)
+#define C_DDR_REG_TIMING1		(DDR_BASE + 0x38)
+#define C_DDR_REG_TIMING2		(DDR_BASE + 0x3C)
+
+#define C_DDR_REG_PHY0			(DDR_BASE + 0x48)
+#define C_DDR_REG_PHY1			(DDR_BASE + 0x4C)
+#define C_DDR_REG_PHY2			(DDR_BASE + 0x50)
+#define C_DDR_REG_PHY3			(DDR_BASE + 0x54)
+
+#define C_DDR_REG_GENERIC		(DDR_BASE + 0x60)
+
+#define C_OXSEMI_DDRC_SIGNATURE		0x054415AA
+
+#define DDR_PHY_BASE			(DDR_BASE + 0x80000)
+#define DDR_PHY_TIMING			(DDR_PHY_BASE + 0x48)
+#define DDR_PHY_TIMING_CK		(1 << 12)
+#define DDR_PHY_TIMING_INC		(1 << 13)
+#define DDR_PHY_TIMING_W_CE		(1 << 14)
+#define DDR_PHY_TIMING_W_RST		(1 << 15)
+#define DDR_PHY_TIMING_I_CE		(1 << 16)
+#define DDR_PHY_TIMING_I_RST		(1 << 17)
+
+#define C_DDR_REG_PHY_TIMING		(DDR_PHY_BASE + 0x50)
+#define C_DDR_REG_PHY_WR_RATIO		(DDR_PHY_BASE + 0x74)
+#define C_DDR_REG_PHY_RD_RATIO		(DDR_PHY_BASE + 0x78)
+
+#define C_DDR_TRANSACTION_ROUTING	(DDR_PHY_BASE + 0xC8)
+#define DDR_ROUTE_CPU0_INSTR_SHIFT	0
+#define DDR_ROUTE_CPU0_RDDATA_SHIFT	4
+#define DDR_ROUTE_CPU0_WRDATA_SHIFT	6
+#define DDR_ROUTE_CPU1_INSTR_SHIFT	8
+#define DDR_ROUTE_CPU1_RDDATA_SHIFT	12
+#define DDR_ROUTE_CPU1_WRDATA_SHIFT	14
+
+unsigned int ddrc_signature(void);
+void set_ddr_timing(unsigned int w, unsigned int i);
+int pause(unsigned int us);
+void set_ddr_sel(int val);
diff --git a/package/boot/uboot-oxnas/files/board/ox820/lowlevel_init.S b/package/boot/uboot-oxnas/files/board/ox820/lowlevel_init.S
new file mode 100644
index 0000000000..3328b7aa86
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/board/ox820/lowlevel_init.S
@@ -0,0 +1,20 @@
+#include <config.h>
+#ifndef CONFIG_SPL_BUILD
+
+.globl lowlevel_init
+lowlevel_init:
+	/*
+	 * Copy exception table to relocated address in internal SRAM
+	 */
+	ldr	r0, src		/* Address of exception table in flash */
+	ldr	r1, dest	/* Relocated address of exception table */
+	ldmia	r0!, {r3-r10}	/* Copy exception table and jump values from */
+	stmia	r1!, {r3-r10}	/* FLASH to relocated address */
+	ldmia	r0!, {r3-r10}
+	stmia	r1!, {r3-r10}
+	mov	pc, lr
+
+src:	.word CONFIG_SYS_TEXT_BASE
+dest:	.word CONFIG_SRAM_BASE
+
+#endif
\ No newline at end of file
diff --git a/package/boot/uboot-oxnas/files/board/ox820/ox820.c b/package/boot/uboot-oxnas/files/board/ox820/ox820.c
new file mode 100644
index 0000000000..32c91f4759
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/board/ox820/ox820.c
@@ -0,0 +1,373 @@
+#include <common.h>
+#include <spl.h>
+#include <phy.h>
+#include <netdev.h>
+#include <ide.h>
+#include <nand.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+#ifdef DEBUG
+#define DILIGENCE (1048576/4)
+static int test_memory(u32 memory)
+{
+	volatile u32 *read;
+	volatile u32 *write;
+	const u32 INIT_PATTERN = 0xAA55AA55;
+	const u32 INC_PATTERN = 0x01030507;
+	u32 pattern;
+	int check;
+	int i;
+
+	check = 0;
+	read = write = (volatile u32 *) memory;
+	pattern = INIT_PATTERN;
+	for (i = 0; i < DILIGENCE; i++) {
+		*write++ = pattern;
+		pattern += INC_PATTERN;
+	}
+	puts("testing\n");
+	pattern = INIT_PATTERN;
+	for (i = 0; i < DILIGENCE; i++) {
+		check += (pattern == *read++) ? 1 : 0;
+		pattern += INC_PATTERN;
+	}
+	return (check == DILIGENCE) ? 0 : -1;
+}
+#endif
+
+void uart_init(void)
+{
+	/* Reset UART1 */
+	reset_block(SYS_CTRL_RST_UART1, 1);
+	udelay(100);
+	reset_block(SYS_CTRL_RST_UART1, 0);
+	udelay(100);
+
+	/* Setup pin mux'ing for UART1 */
+	pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);
+	pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);
+}
+
+extern void init_ddr(int mhz);
+
+void board_inithw(void)
+{
+	int plla_freq;
+#ifdef DEBUG
+	int i;
+#endif	/* DEBUG */
+
+	timer_init();
+	uart_init();
+	preloader_console_init();
+
+	plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);
+	init_ddr(plla_freq);
+
+#ifdef DEBUG
+	if(test_memory(CONFIG_SYS_SDRAM_BASE)) {
+		puts("memory test failed\n");
+	} else {
+		puts("memory test done\n");
+	}
+#endif /* DEBUG */
+#ifdef CONFIG_SPL_BSS_DRAM_START
+	extern char __bss_dram_start[];
+	extern char __bss_dram_end[];
+	memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);
+#endif
+}
+
+void board_init_f(ulong dummy)
+{
+	/* Set the stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	board_inithw();
+
+	board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+	return CONFIG_SPL_BOOT_DEVICE;
+}
+
+#ifdef CONFIG_SPL_BLOCK_SUPPORT
+void spl_block_device_init(void)
+{
+	ide_init();
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+        /* break into full u-boot on 'c' */
+        return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
+void spl_display_print(void)
+{
+	/* print a hint, so that we will not use the wrong SPL by mistake */
+	puts("  Boot device: " BOOT_DEVICE_TYPE "\n" );
+}
+
+void lowlevel_init(void)
+{
+}
+
+#ifdef USE_DL_PREFIX
+/* quick and dirty memory allocation */
+static ulong next_mem = CONFIG_SPL_MALLOC_START;
+
+void *memalign(size_t alignment, size_t bytes)
+{
+	ulong mem = ALIGN(next_mem, alignment);
+
+	next_mem = mem + bytes;
+
+	if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {
+		printf("spl: out of memory\n");
+		hang();
+	}
+
+	return (void *)mem;
+}
+
+void free(void* mem)
+{
+}
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+#define STATIC_CTL_BANK0		(STATIC_CONTROL_BASE + 4)
+#define STATIC_READ_CYCLE_SHIFT		0
+#define STATIC_DELAYED_OE		(1 << 7)
+#define STATIC_WRITE_CYCLE_SHIFT	8
+#define STATIC_WRITE_PULSE_SHIFT	16
+#define STATIC_WRITE_BURST_EN		(1 << 23)
+#define STATIC_TURN_AROUND_SHIFT	24
+#define STATIC_BUFFER_PRESENT		(1 << 28)
+#define STATIC_READ_BURST_EN		(1 << 29)
+#define STATIC_BUS_WIDTH8		(0 << 30)
+#define STATIC_BUS_WIDTH16		(1 << 30)
+#define STATIC_BUS_WIDTH32		(2 << 30)
+
+void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));
+		if (ctrl & NAND_CLE)
+			nandaddr |= BIT(NAND_CLE_ADDR_PIN);
+		else if (ctrl & NAND_ALE)
+			nandaddr |= BIT(NAND_ALE_ADDR_PIN);
+		this->IO_ADDR_W = (void __iomem *) nandaddr;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, (void __iomem *) nandaddr);
+}
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
+
+int nand_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	udelay(chip->chip_delay);
+
+	return 1;
+}
+
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+
+	for (i = 0; i < len; i++)
+		buf[i] = readb(chip->IO_ADDR_R);
+}
+
+void nand_dev_reset(struct nand_chip *chip)
+{
+	writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
+	udelay(chip->chip_delay);
+	writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
+	while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {
+		;
+	}
+}
+
+#else
+
+#define nand_dev_reset(chip)	/* framework will reset the chip anyway */
+#define nand_read_buf		NULL /* framework will provide a default one */
+#define nand_dev_ready		NULL /* dev_ready is optional */
+
+#endif
+
+int board_nand_init(struct nand_chip *chip)
+{
+	/* Block reset Static core */
+	reset_block(SYS_CTRL_RST_STATIC, 1);
+	reset_block(SYS_CTRL_RST_STATIC, 0);
+
+	/* Enable clock to Static core */
+	enable_clock(SYS_CTRL_CLK_STATIC);
+
+	/* enable flash support on static bus.
+	 * Enable static bus onto GPIOs, only CS0 */
+	pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);
+	pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);
+	pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);
+	pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);
+	pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);
+	pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);
+	pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);
+	pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);
+
+	pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);
+	pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);
+	pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);
+	pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);
+	pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);
+
+	/* Setup the static bus CS0 to access FLASH */
+
+	writel((0x3f << STATIC_READ_CYCLE_SHIFT)
+			| (0x3f << STATIC_WRITE_CYCLE_SHIFT)
+			| (0x1f << STATIC_WRITE_PULSE_SHIFT)
+			| (0x03 << STATIC_TURN_AROUND_SHIFT) |
+			STATIC_BUS_WIDTH16,
+		STATIC_CTL_BANK0);
+
+	chip->cmd_ctrl = nand_hwcontrol;
+	chip->ecc.mode = NAND_ECC_SOFT;
+	chip->chip_delay = 30;
+	chip->dev_ready = nand_dev_ready;
+	chip->read_buf = nand_read_buf;
+
+	nand_dev_reset(chip);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* assume uart is already initialized by SPL */
+
+#if defined(CONFIG_START_IDE)
+	puts("IDE:   ");
+	ide_init();
+#endif
+
+	return 0;
+}
+
+/* copied from board/evb64260/sdram_init.c */
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2)	/* start test at half size */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,
+					CONFIG_MAX_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	u32 value;
+
+	/* set the pin multiplexers to enable talking to Ethernent Phys */
+	pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);
+	pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);
+
+	// Ensure the MAC block is properly reset
+	reset_block(SYS_CTRL_RST_MAC, 1);
+	udelay(10);
+	reset_block(SYS_CTRL_RST_MAC, 0);
+
+	// Enable the clock to the MAC block
+	enable_clock(SYS_CTRL_CLK_MAC);
+
+	value = readl(SYS_CTRL_GMAC_CTRL);
+	/* Use simple mux for 25/125 Mhz clock switching */
+	value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
+	/* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
+	value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
+	/* set auto tx speed */
+	value |= BIT(SYS_CTRL_GMAC_AUTOSPEED);
+
+	writel(value, SYS_CTRL_GMAC_CTRL);
+
+	return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);
+}
+
diff --git a/package/boot/uboot-oxnas/files/board/ox820/spl_start.S b/package/boot/uboot-oxnas/files/board/ox820/spl_start.S
new file mode 100644
index 0000000000..2eab3f56d8
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/board/ox820/spl_start.S
@@ -0,0 +1,21 @@
+.section .init
+.globl _spl_start
+_spl_start:
+	b	_start
+	b	_start+0x4
+	b	_start+0x8
+	b	_start+0xc
+	b	_start+0x10
+	b	_start+0x14
+	b	_start+0x18
+	b	_start+0x1c
+	.space	0x30 - (. - _spl_start)
+	.ascii	"BOOT"		/* 0x30 signature*/
+	.word	0x50		/* 0x34 header size itself */
+	.word	0		/* 0x38 */
+	.word	0x5000f000	/* boot report location */
+	.word	_start		/* 0x40 */
+
+main_crc_size:	.word	code_size	/* 0x44 filled by linker */
+main_crc:	.word	0		/* 0x48 fill later */
+header_crc:	.word	0		/* 0x4C header crc*/
diff --git a/package/boot/uboot-oxnas/files/board/ox820/u-boot-spl.lds b/package/boot/uboot-oxnas/files/board/ox820/u-boot-spl.lds
new file mode 100644
index 0000000000..a8d90dfba7
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/board/ox820/u-boot-spl.lds
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY
+{
+	 sram (rwx) : ORIGIN = CONFIG_SPL_TEXT_BASE, LENGTH = CONFIG_SPL_MAX_SIZE
+	 dram : ORIGIN = CONFIG_SPL_BSS_DRAM_START, LENGTH = CONFIG_SPL_BSS_DRAM_SIZE
+}
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_spl_start)
+SECTIONS
+{
+	.text.0	:
+	{
+		*(.init*)
+	}
+
+
+	/* Start of the rest of the SPL */
+	code_start = . ;
+
+	.text.1	:
+	{
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	__image_copy_end = .;
+	code_size = . - code_start;
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	. = ALIGN(0x800);
+
+	_end = .;
+
+	.bss.sram __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss.stdio_devices)
+		*(.bss.serial_current)
+		 . = ALIGN(4);
+		__bss_end = .;
+	}
+
+	.bss : {
+		__bss_dram_start = .;
+		*(.bss*)
+		__bss_dram_end = .;
+	} > dram
+
+	/DISCARD/ : { *(.bss*) }
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynsym*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.hash*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}