aboutsummaryrefslogtreecommitdiffstats
path: root/package/boot/uboot-mvebu
diff options
context:
space:
mode:
authorJakov Petrina <jakov.petrina@sartura.hr>2020-04-24 14:38:58 +0200
committerLuka Perkov <luka.perkov@sartura.hr>2020-05-09 14:34:23 +0200
commitb1cfbff0a7d386a7b3d3aa19b9971e0ea6d1db65 (patch)
tree5b3d3f1b2ec84778e9651a129a04813f9b8e70a9 /package/boot/uboot-mvebu
parent02656caa7b3c6da24a1c253b8d28887ab5c1bed1 (diff)
downloadupstream-b1cfbff0a7d386a7b3d3aa19b9971e0ea6d1db65.tar.gz
upstream-b1cfbff0a7d386a7b3d3aa19b9971e0ea6d1db65.tar.bz2
upstream-b1cfbff0a7d386a7b3d3aa19b9971e0ea6d1db65.zip
mvebu: uDPU: switch default kernel and U-Boot PHY mode
Certain SFP modules (most notably Nokia GPON ones) first check connectivity on 1000base-x, and switch to 2500base-x afterwards. This is considered a quirk so the phylink switches the interface to 2500base-x as well. However, after power-cycling the uDPU device, network interface/SFP module will not work correctly until the module is re-seated. This patch resolves this issue by forcing the interface to be brought up in 2500base-x mode by default. Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr> Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'package/boot/uboot-mvebu')
-rw-r--r--package/boot/uboot-mvebu/patches/220-arm-dts-uDPU-switch-default-PHY-speed-to-3.125Gbit.patch43
1 files changed, 43 insertions, 0 deletions
diff --git a/package/boot/uboot-mvebu/patches/220-arm-dts-uDPU-switch-default-PHY-speed-to-3.125Gbit.patch b/package/boot/uboot-mvebu/patches/220-arm-dts-uDPU-switch-default-PHY-speed-to-3.125Gbit.patch
new file mode 100644
index 0000000000..0e10b2c767
--- /dev/null
+++ b/package/boot/uboot-mvebu/patches/220-arm-dts-uDPU-switch-default-PHY-speed-to-3.125Gbit.patch
@@ -0,0 +1,43 @@
+--- a/arch/arm/dts/armada-3720-uDPU.dts
++++ b/arch/arm/dts/armada-3720-uDPU.dts
+@@ -109,11 +109,11 @@
+ &comphy {
+ phy0 {
+ phy-type = <PHY_TYPE_SGMII1>;
+- phy-speed = <PHY_SPEED_1_25G>;
++ phy-speed = <PHY_SPEED_3_125G>;
+ };
+ phy1 {
+ phy-type = <PHY_TYPE_SGMII0>;
+- phy-speed = <PHY_SPEED_1_25G>;
++ phy-speed = <PHY_SPEED_3_125G>;
+ };
+
+ phy2 {
+@@ -125,22 +125,16 @@
+ &eth0 {
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+- phy-mode = "sgmii";
++ phy-mode = "sgmii-2500";
++ managed = "in-band-status";
+ phy = <&ethphy0>;
+- fixed-link {
+- speed = <1000>;
+- full-duplex;
+- };
+ };
+
+ &eth1 {
+ status = "okay";
+- phy-mode = "sgmii";
++ phy-mode = "sgmii-2500";
++ managed = "in-band-status";
+ phy = <&ethphy1>;
+- fixed-link {
+- speed = <1000>;
+- full-duplex;
+- };
+ };
+
+ &i2c0 {