diff options
| author | Daniel Golle <daniel@makrotopia.org> | 2022-07-11 21:15:32 +0100 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2022-07-11 21:27:24 +0100 |
| commit | 2f7fb57c12d7afe5be7747611bceec92a4c0c834 (patch) | |
| tree | 8766380a7feeb1350a6b78aa01014a8cb43c4e05 /package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch | |
| parent | fa75a3a935b26378630498ba7d3f6a0b5b11f86e (diff) | |
| download | upstream-2f7fb57c12d7afe5be7747611bceec92a4c0c834.tar.gz upstream-2f7fb57c12d7afe5be7747611bceec92a4c0c834.tar.bz2 upstream-2f7fb57c12d7afe5be7747611bceec92a4c0c834.zip | |
uboot-ramips: add support for MT7621, merge into uboot-mediatek
* Merge uboot-ramips into uboot-mediatek.
* Port support for the RAVPower RP WD009 to U-Boot 2022.07.
* Add support for MT7621 and add builds for the reference boards.
* Add builds for MT7620 and MT7628 reference boards.
This should help to make development of U-Boot-level board support for
all MediaTek targets much easier.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch')
| -rw-r--r-- | package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch b/package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch new file mode 100644 index 0000000000..0a3a0a18b6 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch @@ -0,0 +1,116 @@ +From be570e7b0ce004127a7cc97bfae30037fc42a340 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 20 May 2022 11:21:39 +0800 +Subject: [PATCH 02/25] mips: add more definitions for asm/cm.h + +This patch add more definitions needed for MT7621 initialization. +MT7621 needs to initialize GIC/CPC and other related parts. + +Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/mips/include/asm/cm.h | 67 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 67 insertions(+) + +diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h +index 99ddbccd80..5cc8c09621 100644 +--- a/arch/mips/include/asm/cm.h ++++ b/arch/mips/include/asm/cm.h +@@ -8,9 +8,23 @@ + #define __MIPS_ASM_CM_H__ + + /* Global Control Register (GCR) offsets */ ++#define GCR_CONFIG 0x0000 + #define GCR_BASE 0x0008 + #define GCR_BASE_UPPER 0x000c ++#define GCR_CONTROL 0x0010 ++#define GCR_ACCESS 0x0020 + #define GCR_REV 0x0030 ++#define GCR_GIC_BASE 0x0080 ++#define GCR_CPC_BASE 0x0088 ++#define GCR_REG0_BASE 0x0090 ++#define GCR_REG0_MASK 0x0098 ++#define GCR_REG1_BASE 0x00a0 ++#define GCR_REG1_MASK 0x00a8 ++#define GCR_REG2_BASE 0x00b0 ++#define GCR_REG2_MASK 0x00b8 ++#define GCR_REG3_BASE 0x00c0 ++#define GCR_REG3_MASK 0x00c8 ++#define GCR_CPC_STATUS 0x00f0 + #define GCR_L2_CONFIG 0x0130 + #define GCR_L2_TAG_ADDR 0x0600 + #define GCR_L2_TAG_ADDR_UPPER 0x0604 +@@ -19,10 +33,59 @@ + #define GCR_L2_DATA 0x0610 + #define GCR_L2_DATA_UPPER 0x0614 + #define GCR_Cx_COHERENCE 0x2008 ++#define GCR_Cx_OTHER 0x2018 ++#define GCR_Cx_ID 0x2028 ++#define GCR_CO_COHERENCE 0x4008 ++ ++/* GCR_CONFIG fields */ ++#define GCR_CONFIG_NUM_CLUSTERS_SHIFT 23 ++#define GCR_CONFIG_NUM_CLUSTERS (0x7f << 23) ++#define GCR_CONFIG_NUMIOCU_SHIFT 8 ++#define GCR_CONFIG_NUMIOCU (0xff << 8) ++#define GCR_CONFIG_PCORES_SHIFT 0 ++#define GCR_CONFIG_PCORES (0xff << 0) ++ ++/* GCR_BASE fields */ ++#define GCR_BASE_SHIFT 15 ++#define CCA_DEFAULT_OVR_SHIFT 5 ++#define CCA_DEFAULT_OVR_MASK (0x7 << 5) ++#define CCA_DEFAULT_OVREN (0x1 << 4) ++#define CM_DEFAULT_TARGET_SHIFT 0 ++#define CM_DEFAULT_TARGET_MASK (0x3 << 0) ++ ++/* GCR_CONTROL fields */ ++#define GCR_CONTROL_SYNCCTL (0x1 << 16) + + /* GCR_REV CM versions */ + #define GCR_REV_CM3 0x0800 + ++/* GCR_GIC_BASE fields */ ++#define GCR_GIC_BASE_ADDRMASK_SHIFT 7 ++#define GCR_GIC_BASE_ADDRMASK (0x1ffffff << 7) ++#define GCR_GIC_EN (0x1 << 0) ++ ++/* GCR_CPC_BASE fields */ ++#define GCR_CPC_BASE_ADDRMASK_SHIFT 15 ++#define GCR_CPC_BASE_ADDRMASK (0x1ffff << 15) ++#define GCR_CPC_EN (0x1 << 0) ++ ++/* GCR_REGn_MASK fields */ ++#define GCR_REGn_MASK_ADDRMASK_SHIFT 16 ++#define GCR_REGn_MASK_ADDRMASK (0xffff << 16) ++#define GCR_REGn_MASK_CCAOVR_SHIFT 5 ++#define GCR_REGn_MASK_CCAOVR (0x7 << 5) ++#define GCR_REGn_MASK_CCAOVREN (1 << 4) ++#define GCR_REGn_MASK_DROPL2 (1 << 2) ++#define GCR_REGn_MASK_CMTGT_SHIFT 0 ++#define GCR_REGn_MASK_CMTGT (0x3 << 0) ++#define GCR_REGn_MASK_CMTGT_DISABLED 0x0 ++#define GCR_REGn_MASK_CMTGT_MEM 0x1 ++#define GCR_REGn_MASK_CMTGT_IOCU0 0x2 ++#define GCR_REGn_MASK_CMTGT_IOCU1 0x3 ++ ++/* GCR_CPC_STATUS fields */ ++#define GCR_CPC_EX (0x1 << 0) ++ + /* GCR_L2_CONFIG fields */ + #define GCR_L2_CONFIG_ASSOC_SHIFT 0 + #define GCR_L2_CONFIG_ASSOC_BITS 8 +@@ -36,6 +99,10 @@ + #define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) + #define GCR_Cx_COHERENCE_EN (0x1 << 0) + ++/* GCR_Cx_OTHER fields */ ++#define GCR_Cx_OTHER_CORENUM_SHIFT 16 ++#define GCR_Cx_OTHER_CORENUM (0xffff << 16) ++ + #ifndef __ASSEMBLY__ + + #include <asm/io.h> +-- +2.36.1 + |