layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 58 insertions, 0 deletions

diff --git a/package/boot/uboot-layerscape/patches/0071-driver-fsl_qspi-disable-AHB-buffer-prefetch.patch b/package/boot/uboot-layerscape/patches/0071-driver-fsl_qspi-disable-AHB-buffer-prefetch.patch
new file mode 100644
index 0000000000..a7cb7b485e
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0071-driver-fsl_qspi-disable-AHB-buffer-prefetch.patch
@@ -0,0 +1,58 @@
+From e2a5bba97cd6e42b2b631bd17012aa26ffdb5f67 Mon Sep 17 00:00:00 2001
+From: Yunhui Cui <yunhui.cui@nxp.com>
+Date: Tue, 12 Jul 2016 10:30:08 +0800
+Subject: [PATCH 71/93] driver: fsl_qspi: disable AHB buffer prefetch
+
+Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
+When we enable the CONFIG_SYS_FSL_QSPI_AHB, we need this errata workaround.
+
+Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
+---
+ drivers/spi/fsl_qspi.c           |   12 +++++++++++-
+ include/configs/ls1012a_common.h |    1 +
+ 2 files changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
+index 09759fa..f1c87f5 100644
+--- a/drivers/spi/fsl_qspi.c
++++ b/drivers/spi/fsl_qspi.c
+@@ -441,13 +441,23 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
+ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
+ {
+ 	struct fsl_qspi_regs *regs = priv->regs;
++	int rx_size = 0x80;
+ 
+ 	/* AHB configuration for access buffer 0/1/2 .*/
+ 	qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
+ 	qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
+ 	qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
++
++#ifdef CONFIG_SYS_FSL_ERRATUM_A009282
++	/*A-009282: QuadSPI data pre-fetch can result in incorrect data
++	 *Workaround: Keep the read data size to 64 bits (8 Bytes), which
++	 *disables the prefetch on the AHB buffer,and prevents this issue
++	 *from occurring.
++	*/
++	rx_size = 0x1;
++#endif
+ 	qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
+-		     (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
++		     (rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
+ 
+ 	/* We only use the buffer3 */
+ 	qspi_write32(priv->flags, &regs->buf0ind, 0);
+diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
+index 47b8ec3..f0ae355 100644
+--- a/include/configs/ls1012a_common.h
++++ b/include/configs/ls1012a_common.h
+@@ -68,6 +68,7 @@
+ #define FSL_QSPI_FLASH_SIZE		(1 << 26)
+ #define FSL_QSPI_FLASH_NUM		2
+ #define CONFIG_SYS_FSL_QSPI_AHB
++#define CONFIG_SYS_FSL_ERRATUM_A009282
+ 
+ /*
+  * Environment
+-- 
+1.7.9.5
+