layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 64 insertions, 0 deletions

diff --git a/package/boot/uboot-layerscape/patches/0064-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch b/package/boot/uboot-layerscape/patches/0064-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch
new file mode 100644
index 0000000000..eaff510997
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0064-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch
@@ -0,0 +1,64 @@
+From 31f17073ffb1501574ad4cb8dffd507dee40e69a Mon Sep 17 00:00:00 2001
+From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+Date: Thu, 16 Jun 2016 13:49:17 +0530
+Subject: [PATCH 64/93] board: freescale: ls1012a: Intergrate and enable PPA
+ on LS1012ARDB
+
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
+---
+ board/freescale/ls1012ardb/ls1012ardb.c |   10 ++++++++++
+ include/configs/ls1012ardb.h            |    9 +++++++++
+ 2 files changed, 19 insertions(+)
+
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index 8340f14..7f7503c 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -198,6 +198,9 @@ int mmc_check_sdhc2_card(void)
+ int board_init(void)
+ {
+ 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
++#ifdef CONFIG_FSL_LS_PPA
++	u64 ppa_entry;
++#endif
+ 	/*
+ 	 * Set CCI-400 control override register to enable barrier
+ 	 * transaction
+@@ -216,6 +219,13 @@ int board_init(void)
+ 	sec_init();
+ #endif
+ 
++#ifdef CONFIG_FSL_LS_PPA
++	ppa_init_pre(&ppa_entry);
++
++	if (ppa_entry)
++		ppa_init_entry((void *)ppa_entry);
++#endif
++
+ 	return 0;
+ }
+ 
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index f6b3f28..fdaea3e 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -9,6 +9,15 @@
+ 
+ #include "ls1012a_common.h"
+ 
++#define CONFIG_FSL_LS_PPA
++#if defined(CONFIG_FSL_LS_PPA)
++#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE		(1UL * 1024 * 1024)
++
++#define CONFIG_SYS_LS_PPA_FW_IN_XIP
++#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
++#define	CONFIG_SYS_LS_PPA_FW_ADDR	0x40500000
++#endif
++#endif
+ 
+ #define CONFIG_DIMM_SLOTS_PER_CTLR	1
+ #define CONFIG_CHIP_SELECTS_PER_CTRL	1
+-- 
+1.7.9.5
+