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| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
| tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch | |
| parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
| download | upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip | |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch b/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch new file mode 100644 index 0000000000..33ea668526 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch @@ -0,0 +1,32 @@ +From 367c16da9255dacf6440f3c72c01c197cfb1bbe8 Mon Sep 17 00:00:00 2001 +From: Sumit Garg <sumit.garg@nxp.com> +Date: Wed, 11 May 2016 12:44:35 -0400 +Subject: [PATCH 30/93] ARMv8: Enable CPUECTLR.SMPEN for data coherency + +Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. +The SMPEN bit should be set before enabling the data cache. If not +enabled, the cache is not coherent with other cores and data +corruption could occur. It also enables core level cache snooping. + +Signed-off-by: Sumit Garg <sumit.garg@nxp.com> +--- + arch/arm/cpu/armv8/start.S | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S +index 235213f..9703f6b 100644 +--- a/arch/arm/cpu/armv8/start.S ++++ b/arch/arm/cpu/armv8/start.S +@@ -70,6 +70,9 @@ reset: + mov x0, #3 << 20 + msr cpacr_el1, x0 /* Enable FP/SIMD */ + 0: ++ /* Enalbe SMPEN bit */ ++ mov x0, #0x40 ++ msr s3_1_c15_c2_1, x0 + + /* Apply ARM core specific erratas */ + bl apply_core_errata +-- +1.7.9.5 + |