layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 115 insertions, 0 deletions

diff --git a/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch b/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch
new file mode 100644
index 0000000000..e42e51ea36
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch
@@ -0,0 +1,115 @@
+From 93a1095c7da7291ffb12116de9122d431b9f6113 Mon Sep 17 00:00:00 2001
+From: Sumit Garg <sumit.garg@nxp.com>
+Date: Fri, 6 May 2016 11:11:58 -0400
+Subject: [PATCH 25/93] armv8: ls1012ardb: Add qspi SECURE BOOT target
+
+Add qspi SECURE BOOT target to enable chain of trust. Also enable
+sec_init in boot sequence.
+
+Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
+Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
+---
+ arch/arm/include/asm/arch-fsl-layerscape/config.h |    7 +++++++
+ arch/arm/include/asm/fsl_secure_boot.h            |    7 ++++++-
+ board/freescale/ls1012ardb/ls1012ardb.c           |    5 +++++
+ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig     |   10 ++++++++++
+ include/configs/ls1012ardb.h                      |    2 ++
+ 5 files changed, 30 insertions(+), 1 deletion(-)
+ create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+index 6ea4e8e..679be6c 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
+@@ -237,6 +237,13 @@
+ 
+ #define CONFIG_SYS_FSL_ERRATUM_A009798
+ 
++#define CONFIG_SYS_FSL_SFP_VER_3_2
++#define CONFIG_SYS_FSL_SEC_MON_BE
++#define CONFIG_SYS_FSL_SEC_BE
++#define CONFIG_SYS_FSL_SFP_BE
++#define CONFIG_SYS_FSL_SRK_LE
++#define CONFIG_KEY_REVOCATION
++
+ #else
+ #error SoC not defined
+ #endif
+diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
+index c7f8b3e..c973255 100644
+--- a/arch/arm/include/asm/fsl_secure_boot.h
++++ b/arch/arm/include/asm/fsl_secure_boot.h
+@@ -50,7 +50,7 @@
+ #endif
+ 
+ #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
+-	defined(CONFIG_LS2085A)
++	defined(CONFIG_LS2085A) || defined(CONFIG_LS1012A)
+ /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
+  * Similiarly for LS2080 and LS2085
+  */
+@@ -81,6 +81,11 @@
+ #define CONFIG_BS_ADDR_FLASH		0x583900000
+ #define CONFIG_BS_HDR_ADDR_RAM		0xa3920000
+ #define CONFIG_BS_ADDR_RAM		0xa3900000
++#elif defined(CONFIG_LS1012A)
++#define CONFIG_BS_HDR_ADDR_FLASH	0x400c0000
++#define CONFIG_BS_ADDR_FLASH		0x40060000
++#define CONFIG_BS_HDR_ADDR_RAM		0xa0060000
++#define CONFIG_BS_ADDR_RAM		0xa0060000
+ #else
+ #define CONFIG_BS_HDR_ADDR_FLASH	0x600a0000
+ #define CONFIG_BS_ADDR_FLASH		0x60060000
+diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
+index f7b9bce..347b8c8 100644
+--- a/board/freescale/ls1012ardb/ls1012ardb.c
++++ b/board/freescale/ls1012ardb/ls1012ardb.c
+@@ -20,6 +20,7 @@
+ #include <environment.h>
+ #include <fsl_mmdc.h>
+ #include <netdev.h>
++#include <fsl_sec.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+ 
+@@ -191,6 +192,10 @@ int board_init(void)
+ 	enable_layerscape_ns_access();
+ #endif
+ 
++#ifdef CONFIG_FSL_CAAM
++	sec_init();
++#endif
++
+ 	return 0;
+ }
+ 
+diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+new file mode 100644
+index 0000000..92a95a8
+--- /dev/null
++++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LS1012ARDB=y
++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
++# CONFIG_CMD_IMLS is not set
++CONFIG_SYS_NS16550=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
++CONFIG_OF_CONTROL=y
++CONFIG_DM=y
++CONFIG_SPI_FLASH=y
++CONFIG_DM_SPI=y
+diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
+index af3d33f..b40e02b 100644
+--- a/include/configs/ls1012ardb.h
++++ b/include/configs/ls1012ardb.h
+@@ -73,4 +73,6 @@
+ #define CONFIG_SYS_MEMTEST_START	0x80000000
+ #define CONFIG_SYS_MEMTEST_END		0x9fffffff
+ 
++#define CONFIG_FSL_CAAM			/* Enable CAAM */
++
+ #endif /* __LS1012ARDB_H__ */
+-- 
+1.7.9.5
+