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author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
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committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch | |
parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
download | upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch')
-rw-r--r-- | package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch b/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch new file mode 100644 index 0000000000..61b445de3d --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch @@ -0,0 +1,65 @@ +From 271adb5c0546b080fb350a41520c600a16739f1a Mon Sep 17 00:00:00 2001 +From: Rajesh Bhagat <rajesh.bhagat@nxp.com> +Date: Fri, 6 May 2016 09:05:29 +0530 +Subject: [PATCH 23/93] drivers: usb: fsl: add USB ULPI init code + +This adds the required code to set up a ULPI USB port, for +new NXP USB PHY used in QorIQ platforms. + +To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT +have to be set in the board configuration file. + +Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> +--- + drivers/usb/host/ehci-fsl.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c +index 97b7f14..3f06345 100644 +--- a/drivers/usb/host/ehci-fsl.c ++++ b/drivers/usb/host/ehci-fsl.c +@@ -16,6 +16,9 @@ + #include <hwconfig.h> + #include <fsl_usb.h> + #include <fdt_support.h> ++#ifdef CONFIG_USB_ULPI ++#include <usb/ulpi.h> ++#endif + + #include "ehci.h" + +@@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init, + const char *phy_type = NULL; + size_t len; + char current_usb_controller[5]; ++#ifdef CONFIG_USB_ULPI ++ int ret; ++ struct ulpi_viewport ulpi_vp; ++#endif + #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY + char usb_phy[5]; + +@@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init, + udelay(1000); /* delay required for PHY Clk to appear */ + if (!usb_phy_clk_valid(ehci)) + return -EINVAL; ++ ++#ifdef CONFIG_USB_ULPI ++ ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; ++ ulpi_vp.port_num = 0; ++ ++ ret = ulpi_init(&ulpi_vp); ++ if (ret) { ++ puts("NXP ULPI viewport init failed\n"); ++ return -1; ++ } ++ ++ ulpi_set_vbus(&ulpi_vp, 1, 1); ++ ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 1); ++#endif + out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); + } + +-- +1.7.9.5 + |