diff options
| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
| tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch | |
| parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
| download | upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip | |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch b/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch new file mode 100644 index 0000000000..f46b1b282f --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch @@ -0,0 +1,62 @@ +From 035a4db85bbf28ba1452c49c9f8d05a085f2544b Mon Sep 17 00:00:00 2001 +From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +Date: Tue, 26 Apr 2016 17:40:05 +0530 +Subject: [PATCH 18/93] boards: ls1012aqds: Enable SDHC_CD in brdcfg10 of FPGA + +Default configuration of brdcfg10 in FPGA does not enable SDHC_CD +signal. + +Enable SDHC_CD by default during boot sequence. + +Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> +Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +--- + board/freescale/ls1012aqds/ls1012aqds.c | 12 ++++++++++++ + include/configs/ls1012aqds.h | 3 +++ + 2 files changed, 15 insertions(+) + +diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c +index ffcd0d8..6d5fef8 100644 +--- a/board/freescale/ls1012aqds/ls1012aqds.c ++++ b/board/freescale/ls1012aqds/ls1012aqds.c +@@ -154,6 +154,18 @@ int board_early_init_f(void) + return 0; + } + ++#ifdef CONFIG_MISC_INIT_R ++int misc_init_r(void) ++{ ++ u8 mux_sdhc_cd = 0x80; ++ ++ i2c_set_bus_num(0); ++ ++ i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); ++ return 0; ++} ++#endif ++ + int board_init(void) + { + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) +diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h +index fdada18..bb433de 100644 +--- a/include/configs/ls1012aqds.h ++++ b/include/configs/ls1012aqds.h +@@ -27,6 +27,7 @@ + #endif + + #define CONFIG_QIXIS_I2C_ACCESS ++#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + + /* + * I2C bus multiplexer +@@ -145,4 +146,6 @@ + #define CONFIG_SYS_MEMTEST_START 0x80000000 + #define CONFIG_SYS_MEMTEST_END 0x9fffffff + ++#define CONFIG_MISC_INIT_R ++ + #endif /* __LS1012AQDS_H__ */ +-- +1.7.9.5 + |