layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 44 insertions, 0 deletions

diff --git a/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch b/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch
new file mode 100644
index 0000000000..6cb1847ca6
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch
@@ -0,0 +1,44 @@
+From 825d623c913c63b1f00c42f27ef0916b11d9f09f Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 15 Mar 2016 13:40:22 +0530
+Subject: [PATCH 07/93] armv8: fsl-layerscape: Avoid LS1043A specifc defines
+
+Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
+
+So Avoid LS1043A specific defines in arch/arm
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/soc.c            |    2 +-
+ .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |    2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+index 92dcb72..23f0c88 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+@@ -314,7 +314,7 @@ int sata_init(void)
+ }
+ #endif
+ 
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_FSL_LSCH2)
+ #ifdef CONFIG_SCSI_AHCI_PLAT
+ int sata_init(void)
+ {
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+index d1fbde7..7096dac 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+@@ -55,7 +55,7 @@ enum srds {
+ 	FSL_SRDS_1  = 0,
+ 	FSL_SRDS_2  = 1,
+ };
+-#elif defined(CONFIG_LS1043A)
++#elif defined(CONFIG_FSL_LSCH2)
+ enum srds_prtcl {
+ 	NONE = 0,
+ 	PCIE1,
+-- 
+1.7.9.5
+