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| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
| tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch | |
| parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
| download | upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 upstream-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip | |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch b/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch new file mode 100644 index 0000000000..a8a9aa360e --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch @@ -0,0 +1,37 @@ +From be06181f45695ce71536ecb461615ebf6f18011e Mon Sep 17 00:00:00 2001 +From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +Date: Tue, 15 Mar 2016 13:40:07 +0530 +Subject: [PATCH 06/93] armv8: fsl-layerscape: Put SMMU config code in + SMMU_BASE + +It is not mandatory for Layerscape SoCs to have SMMU. SoCs like +LS1012A are layerscape SoC without SMMU IP. + +So put SMMU configuration code under SMMU_BASE. + +Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +--- + arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +index 93f4a65..5f5bfb9 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S ++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +@@ -95,11 +95,13 @@ ENTRY(lowlevel_init) + bl ccn504_set_qos + #endif + ++#ifdef SMMU_BASE + /* Set the SMMU page size in the sACR register */ + ldr x1, =SMMU_BASE + ldr w0, [x1, #0x10] + orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ + str w0, [x1, #0x10] ++#endif + + /* Initialize GIC Secure Bank Status */ + #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +-- +1.7.9.5 + |