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| author | Mathias Kresin <dev@kresin.me> | 2016-05-21 12:13:39 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-05-23 11:03:24 +0200 |
| commit | a22feb4c78f51716772738af84180d58bd877c45 (patch) | |
| tree | 41b423036e8ec8a98f9bbfa5c312f4e420fc18d3 /package/boot/uboot-lantiq/patches | |
| parent | 382282eca922e106f5b01597e4676bab8c7176db (diff) | |
| download | upstream-a22feb4c78f51716772738af84180d58bd877c45.tar.gz upstream-a22feb4c78f51716772738af84180d58bd877c45.tar.bz2 upstream-a22feb4c78f51716772738af84180d58bd877c45.zip | |
uboot-lantiq: VGV7510KW22 - use ddr ram params from brnboot
Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'package/boot/uboot-lantiq/patches')
| -rw-r--r-- | package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch b/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch index e46d374dc0..ccc3505a96 100644 --- a/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch +++ b/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch @@ -166,9 +166,9 @@ @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com> -+ * Based on code by: -+ * Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ * and Lantiq Deutschland GmbH ++ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me> ++ * ++ * The values have been extracted from original brnboot. + * + * SPDX-License-Identifier: GPL-2.0+ + */ @@ -204,7 +204,7 @@ +#define MC_CCR28_VALUE 0x0 +#define MC_CCR29_VALUE 0x0 +#define MC_CCR30_VALUE 0x798 -+#define MC_CCR31_VALUE 0x0 ++#define MC_CCR31_VALUE 0x2040F +#define MC_CCR32_VALUE 0x0 +#define MC_CCR33_VALUE 0x650000 +#define MC_CCR34_VALUE 0x200C8 @@ -220,7 +220,7 @@ +#define MC_CCR44_VALUE 0x566504 +#define MC_CCR45_VALUE 0x565F17 +#define MC_CCR46_VALUE 0x565F17 -+#define MC_CCR47_VALUE 0x0 ++#define MC_CCR47_VALUE 0x2040F +#define MC_CCR48_VALUE 0x0 +#define MC_CCR49_VALUE 0x0 +#define MC_CCR50_VALUE 0x0 |