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| author | Felix Fietkau <nbd@openwrt.org> | 2016-01-17 19:55:10 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2016-01-17 19:55:10 +0000 |
| commit | 3f8a4260564d70bd2df9b417b4d03ec39422b8f5 (patch) | |
| tree | 202a2d6321ba1f4015d309469de97a00103e3a83 /feeds.conf.default | |
| parent | 1204a1b1e55a3d1e0ff7b0309c414fb0a1f38eda (diff) | |
| download | upstream-3f8a4260564d70bd2df9b417b4d03ec39422b8f5.tar.gz upstream-3f8a4260564d70bd2df9b417b4d03ec39422b8f5.tar.bz2 upstream-3f8a4260564d70bd2df9b417b4d03ec39422b8f5.zip | |
lantiq: Configure the PCIe reset GPIO using OF
After the latest pinctrl backports there are only 50 (instead of 56 as
before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now
462, before it was 456). This means that any hardcoded GPIOs have to be
adjusted.
This broke the PCIe driver (which seems to be the only driver which uses
hardcoded GPIO numbers), it only reports:
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
pcie_rc_initialize link up failed!!!!!
To prevent more of these issues in the future we remove the hardcoded
PCIe reset GPIO definition and simply pass it via device-tree (like the
PCI driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48285
Diffstat (limited to 'feeds.conf.default')
0 files changed, 0 insertions, 0 deletions