diff options
| author | Piotr Dymacz <pepe2k@gmail.com> | 2017-10-23 13:30:20 +0200 |
|---|---|---|
| committer | Piotr Dymacz <pepe2k@gmail.com> | 2017-11-14 22:36:46 +0100 |
| commit | c83bdd094ec4722b35811bd64781d8aacddb2344 (patch) | |
| tree | 8972d0453a1e780ecb5df2e5d22964edff95c065 /config/Config-devel.in | |
| parent | fa36bea470b3f1f26da4af80ac1e0f0b667a3466 (diff) | |
| download | upstream-c83bdd094ec4722b35811bd64781d8aacddb2344.tar.gz upstream-c83bdd094ec4722b35811bd64781d8aacddb2344.tar.bz2 upstream-c83bdd094ec4722b35811bd64781d8aacddb2344.zip | |
ar71xx: add support for Wallys DR342
Wallys DR342 is a 5 GHz, 2T2R AP/CPE board based on Atheros AR9342.
Short specification:
- 560/450/225 MHz (CPU/DDR/AHB)
- 1x Gbps Ethernet (AR8035) with passive PoE support (24-56 V)
- 64 MB of RAM (DDR2)
- 16 MB of FLASH
- 2T2R 5 GHz with external FEM (SKY85728-11), up to 30 dBm
- 2x MMCX connectors
- miniPCIe connector with PCIe and USB 2.0 buses
- optional miniSIM slot
- 7x LED, 1x button
- UART, (E)JTAG and LED headers
- 1x DC jack for main power (12-56 V)
Flash instruction (do it under U-Boot, using UART):
1. tftp 0x82000000 lede-ar71xx-generic-dr342-squashfs-sysupgrade.bin
2. erase 0x9f050000 +$filesize
3. cp.b $fileaddr 0x9f050000 $filesize
4. setenv bootcmd "bootm 0x9f050000"
5. saveenv && reset
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Diffstat (limited to 'config/Config-devel.in')
0 files changed, 0 insertions, 0 deletions