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| author | Robert Marko <robert.marko@sartura.hr> | 2021-11-08 23:06:02 +0100 |
|---|---|---|
| committer | David Bauer <mail@david-bauer.net> | 2022-10-02 23:04:38 +0200 |
| commit | 45ad5beb809ea9421c0b150c8f03e5b24952b4ae (patch) | |
| tree | 44ae5bd8f7db3c252a089156bbdfef5fa5a89538 | |
| parent | acc4add9a762dc2d29f9e2d6026b1f63e2f0bfa7 (diff) | |
| download | upstream-45ad5beb809ea9421c0b150c8f03e5b24952b4ae.tar.gz upstream-45ad5beb809ea9421c0b150c8f03e5b24952b4ae.tar.bz2 upstream-45ad5beb809ea9421c0b150c8f03e5b24952b4ae.zip | |
ipq40xx: qca807x: always set PSGMII AZ WAR
There is no point in using a DT property to trigger setting the PSGMII
PHY AZ transmitting ability.
Especially since EEE can be disabled using ethtool anyway.
Fixup the mask for setting the workaround as only BIT(0) is actually being
changed and use the phy_clear_bits_mmd helper instead of reading, then
clearing the bit and writing back as it does everything for us.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
3 files changed, 7 insertions, 12 deletions
diff --git a/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c b/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c index d56e9f9cda..2a2d19d6db 100644 --- a/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c +++ b/target/linux/ipq40xx/files/drivers/net/phy/qca807x.c @@ -121,7 +121,7 @@ #define PSGMII_QSGMII_DRIVE_CONTROL_1 0xb #define PSGMII_QSGMII_TX_DRIVER_MASK GENMASK(7, 4) #define PSGMII_MODE_CTRL 0x6d -#define PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK GENMASK(3, 0) +#define PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK BIT(0) #define PSGMII_MMD3_SERDES_CONTROL 0x805a struct qca807x_gpio_priv { @@ -780,17 +780,14 @@ static int qca807x_probe(struct phy_device *phydev) static int qca807x_psgmii_config(struct phy_device *phydev) { struct device_node *node = phydev->mdio.dev.of_node; - int psgmii_az, tx_amp, ret = 0; + int tx_amp, ret = 0; u32 tx_driver_strength; /* Workaround to enable AZ transmitting ability */ - if (of_property_read_bool(node, "qcom,psgmii-az")) { - psgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL); - psgmii_az &= ~PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK; - psgmii_az |= FIELD_PREP(PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK, 0xc); - ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL, psgmii_az); - psgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL); - } + ret = phy_clear_bits_mmd(phydev, + MDIO_MMD_PMAPMD, + PSGMII_MODE_CTRL, + PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK); /* PSGMII/QSGMII TX amp set to DT defined value instead of default 600mV */ if (!of_property_read_u32(node, "qcom,tx-driver-strength", &tx_driver_strength)) { diff --git a/target/linux/ipq40xx/patches-5.10/708-arm-dts-ipq4019-QCA807x-properties.patch b/target/linux/ipq40xx/patches-5.10/708-arm-dts-ipq4019-QCA807x-properties.patch index c08f3a83e6..235f4419a8 100644 --- a/target/linux/ipq40xx/patches-5.10/708-arm-dts-ipq4019-QCA807x-properties.patch +++ b/target/linux/ipq40xx/patches-5.10/708-arm-dts-ipq4019-QCA807x-properties.patch @@ -56,7 +56,6 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr> + reg = <5>; + + qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>; -+ qcom,psgmii-az; }; }; diff --git a/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch b/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch index c08f3a83e6..d978693b4f 100644 --- a/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch +++ b/target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch @@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr> / { #address-cells = <1>; -@@ -598,22 +599,39 @@ +@@ -598,22 +599,38 @@ ethphy0: ethernet-phy@0 { reg = <0>; @@ -56,7 +56,6 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr> + reg = <5>; + + qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>; -+ qcom,psgmii-az; }; }; |