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| author | Birger Koblitz <git@birger-koblitz.de> | 2022-04-24 22:01:31 +0200 |
|---|---|---|
| committer | Sander Vanheule <sander@svanheule.net> | 2022-05-11 22:23:50 +0200 |
| commit | d1b824650f1ee694ec2dbdd2f4f9ec64e650cf86 (patch) | |
| tree | af9bbb14eecb79c7b15fa2a3d814e177a89f04f1 | |
| parent | d9a063c3967c72773616cf5eadd4f978b9724c50 (diff) | |
| download | upstream-d1b824650f1ee694ec2dbdd2f4f9ec64e650cf86.tar.gz upstream-d1b824650f1ee694ec2dbdd2f4f9ec64e650cf86.tar.bz2 upstream-d1b824650f1ee694ec2dbdd2f4f9ec64e650cf86.zip | |
realtek: do not reset SerDes on link change
Do not reset the RTL930x SerDes on link changes, instead set up
the SDS with internal PHYs for the SFP+ ports only.
This fixes the 8 1GBit ports on the Zyxel XGS1250 which
do not work without this patch.
A complete SerDes reset was performed on all SerDes links. For copper
1Gbit ports, this is commonly a single XGMII link to an RTL8218D. There
is however no support for setting up the XGMII link on RTL9300/RTL9310,
thereby wiping the (RX/TX) setup done by u-boot and breaking the 1GBit
ports. No SerDes reset should be done for these links.
The handling of SGMII/HiSGMII, 1000BX or 10GR links is actually entirely
different. All these modes need to be suitably RX calibrated and the
pre- main and post- amplifiers set up properly for TX.
The 10GBit SFP+ fiber links are recalibrated instead of reset, which
e.g. is necessary when someone pulls a module out and puts another in.
This makes swapping out 10GBit fiber modules possible. 1GBit modules are
not yet supported, nor any modules with an internal phy.
Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[rewrite commit message based on discussion]
Link: http://lists.infradead.org/pipermail/openwrt-devel/2022-May/038623.html
Signed-off-by: Sander Vanheule <sander@svanheule.net>
| -rw-r--r-- | target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c | 3 | ||||
| -rw-r--r-- | target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index 2e3ab4a805..f54fdd298a 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -817,7 +817,8 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port, __func__, phy_modes(state->interface)); return; } - rtl9300_sds_rst(sds_num, sds_mode); + if (state->interface == PHY_INTERFACE_MODE_10GBASER) + rtl9300_serdes_setup(sds_num, state->interface); } reg = sw_r32(priv->r->mac_force_mode_ctrl(port)); diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h index 0bb11f9b8b..107016469c 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -121,6 +121,7 @@ irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); void rtl930x_vlan_profile_dump(int index); int rtl9300_sds_power(int mac, int val); void rtl9300_sds_rst(int sds_num, u32 mode); +int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode); void rtl930x_print_matrix(void); /* RTL931x-specific */ |