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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2021-05-05 14:17:36 +0200 |
|---|---|---|
| committer | Christian Lamparter <chunkeey@gmail.com> | 2021-11-06 23:36:32 +0100 |
| commit | 8bc6654244bf90fbdb09b12541380246dbc9556e (patch) | |
| tree | 7bb15d97fab5d4ca5090997d4133512ce603ffb7 | |
| parent | 2bc659ee07fa06b82a6272185865cac29819c254 (diff) | |
| download | upstream-8bc6654244bf90fbdb09b12541380246dbc9556e.tar.gz upstream-8bc6654244bf90fbdb09b12541380246dbc9556e.tar.bz2 upstream-8bc6654244bf90fbdb09b12541380246dbc9556e.zip | |
ramips: mt7621-dts: properly organize pcie node
Device tree pcie node for this SoC is using different
styles in its different properties. Hence properly
unify them to be able to write a a proper yaml schema
documentation.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210505121736.6459-11-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | target/linux/ramips/dts/mt7621.dtsi | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index d1c4756cec..4a3327a364 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -541,10 +541,10 @@ pcie: pcie@1e140000 { compatible = "mediatek,mt7621-pci"; - reg = <0x1e140000 0x100 /* host-pci bridge registers */ - 0x1e142000 0x100 /* pcie port 0 RC control registers */ - 0x1e143000 0x100 /* pcie port 1 RC control registers */ - 0x1e144000 0x100>; /* pcie port 2 RC control registers */ + reg = <0x1e140000 0x100>, /* host-pci bridge registers */ + <0x1e142000 0x100>, /* pcie port 0 RC control registers */ + <0x1e143000 0x100>, /* pcie port 1 RC control registers */ + <0x1e144000 0x100>; /* pcie port 2 RC control registers */ #address-cells = <3>; #size-cells = <2>; @@ -553,10 +553,8 @@ device_type = "pci"; - ranges = < - 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ - >; + ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ interrupt-parent = <&gic>; interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH @@ -565,9 +563,9 @@ status = "disabled"; - resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; + resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>; reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>; clock-names = "pcie0", "pcie1", "pcie2"; phys = <&pcie0_phy 1>, <&pcie2_phy 0>; phy-names = "pcie-phy0", "pcie-phy2"; |