mpc85xx: add support for Freescale (NXP) P2020RDB

This commit add initial support for Freescale (NXP) P2020RDB

Hardware:
SoC: P2020 2x1GHz
DRAM: 512-1GB DDR3
2 + 4 GBE (2 separate ports and four in VSC7385)
Flash: 16MB NOR, 32MB NAND, 16MB SPI-NOR
PCIE x1 and mPCIE x1
SD Reader

Interfaces:
GBE RJ45 x6
USB2.0 x1
UART x2
I2C x2
JTAG x1
SD x1
PCIE x2 (PCIE and mPCIE)

Flash instructions:
Place sysupgrade image to 0x80000 address in NOR.
Eg. (no brakelines in setenv command):

setenv 'firmware_flash tftpboot $loadaddr $firmwarefile;
 protect off $norfdtaddr +$filesize; erase $norfdtaddr +$filesize;
 cp.b $loadaddr $norfdtaddr $filesize; protect on $norfdtaddr +$filesize;
 cmp.b $loadaddr $norfdtaddr $filesize'
setenv firmwarefile firmware.bin
run firmware_flash

Boot (no brakeline in setenv command):
setenv bootcmd 'setenv bootargs root=/dev/mtdblock3 rw console=$consoledev,
$baudrate rootfstype=squashfs $othbootargs;
bootm $norfdtaddr'
saveenv
boot

Known issues:
-Switch is unmanaged (VSC 7385 is connected via eLBC, driver uses SPI)
-No SD reader support

Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [refreshed patches]

7 files changed, 411 insertions, 1 deletions

diff --git a/target/linux/mpc85xx/Makefile b/target/linux/mpc85xx/Makefile
index 552f16e82f..799f0f54dd 100644
--- a/target/linux/mpc85xx/Makefile
+++ b/target/linux/mpc85xx/Makefile
@@ -12,7 +12,7 @@ BOARDNAME:=Freescale MPC85xx
 CPU_TYPE:=8540
 FEATURES:=squashfs
 MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
-SUBTARGETS:=generic p1020
+SUBTARGETS:=generic p1020 p2020
 
 KERNEL_PATCHVER:=4.14
 
diff --git a/target/linux/mpc85xx/image/Makefile b/target/linux/mpc85xx/image/Makefile
index 00eed88874..dd15d4c610 100644
--- a/target/linux/mpc85xx/image/Makefile
+++ b/target/linux/mpc85xx/image/Makefile
@@ -79,4 +79,23 @@ TARGET_DEVICES += hiveap-330
 
 endif
 
+ifeq ($(SUBTARGET),p2020)
+
+define Device/p2020rdb
+  DEVICE_TITLE := Freescale P2020RDB
+  DEVICE_DTS_DIR := $(DTS_DIR)/fsl
+  DEVICE_PACKAGES := kmod-hwmon-core kmod-hwmon-lm90 kmod-rtc-ds1307 \
+	kmod-gpio-pca953x kmod-eeprom-at24
+  BLOCKSIZE := 128k
+  KERNEL := kernel-bin | gzip | \
+	fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+  SUPPORTED_DEVICES := fsl,P2020RDB
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
+	pad-rootfs $$(BLOCKSIZE) | append-metadata
+endef
+TARGET_DEVICES += p2020rdb
+
+endif
+
 $(eval $(call BuildImage))
diff --git a/target/linux/mpc85xx/p2020/config-default b/target/linux/mpc85xx/p2020/config-default
new file mode 100644
index 0000000000..e6526446b4
--- /dev/null
+++ b/target/linux/mpc85xx/p2020/config-default
@@ -0,0 +1,31 @@
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_CPU_RMAP=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_HAVE_RCU_TABLE_FREE=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MPC85xx_RDB=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BCH=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_BCH=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI_MSI=y
+CONFIG_PPC_MSI_BITMAP=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_XPS=y
diff --git a/target/linux/mpc85xx/p2020/profiles/00-default.mk b/target/linux/mpc85xx/p2020/profiles/00-default.mk
new file mode 100644
index 0000000000..c9ea67df08
--- /dev/null
+++ b/target/linux/mpc85xx/p2020/profiles/00-default.mk
@@ -0,0 +1,15 @@
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/Default
+  NAME:=Default Profile
+  PRIORITY:=1
+endef
+
+define Profile/Default/Description
+	Default package set compatible with most P2020 boards.
+endef
+
+$(eval $(call Profile,Default))
diff --git a/target/linux/mpc85xx/p2020/target.mk b/target/linux/mpc85xx/p2020/target.mk
new file mode 100644
index 0000000000..23aca656b2
--- /dev/null
+++ b/target/linux/mpc85xx/p2020/target.mk
@@ -0,0 +1,5 @@
+BOARDNAME:=P2020
+
+define Target/Description
+	Build firmware images for Freescale P2020 based boards.
+endef
diff --git a/target/linux/mpc85xx/patches-4.14/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch b/target/linux/mpc85xx/patches-4.14/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch
new file mode 100644
index 0000000000..39c72314b8
--- /dev/null
+++ b/target/linux/mpc85xx/patches-4.14/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch
@@ -0,0 +1,170 @@
+From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Sun, 30 Dec 2018 23:24:41 +0100
+Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT
+
+This patch apply chages for OpenWRT in P2020RDB
+dts file.
+
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++---------
+ 1 file changed, 63 insertions(+), 35 deletions(-)
+
+--- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts
++++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts
+@@ -2,6 +2,7 @@
+  * P2020 RDB Device Tree Source
+  *
+  * Copyright 2009-2012 Freescale Semiconductor Inc.
++ * Copyright 2018      Pawel Dembicki <paweldembicki@gmail.com>
+  *
+  * This program is free software; you can redistribute  it and/or modify it
+  * under  the terms of  the GNU General  Public License as published by the
+@@ -9,10 +10,15 @@
+  * option) any later version.
+  */
+ 
++/dts-v1/;
++
+ /include/ "p2020si-pre.dtsi"
+ 
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
+ / {
+-	model = "fsl,P2020RDB";
++	model = "Freescale P2020RDB";
+ 	compatible = "fsl,P2020RDB";
+ 
+ 	aliases {
+@@ -38,48 +44,38 @@
+ 			  0x2 0x0 0x0 0xffb00000 0x00020000>;
+ 
+ 		nor@0,0 {
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+ 			compatible = "cfi-flash";
+ 			reg = <0x0 0x0 0x1000000>;
+ 			bank-width = <2>;
+ 			device-width = <1>;
+ 
+-			partition@0 {
+-				/* This location must not be altered  */
+-				/* 256KB for Vitesse 7385 Switch firmware */
+-				reg = <0x0 0x00040000>;
+-				label = "NOR (RO) Vitesse-7385 Firmware";
+-				read-only;
+-			};
+-
+-			partition@40000 {
+-				/* 256KB for DTB Image */
+-				reg = <0x00040000 0x00040000>;
+-				label = "NOR (RO) DTB Image";
+-				read-only;
+-			};
++			partitions {
++				compatible = "fixed-partitions";
++				#address-cells = <1>;
++				#size-cells = <1>;
+ 
+-			partition@80000 {
+-				/* 3.5 MB for Linux Kernel Image */
+-				reg = <0x00080000 0x00380000>;
+-				label = "NOR (RO) Linux Kernel Image";
+-				read-only;
+-			};
++				partition@0 {
++					/* This location must not be altered  */
++					/* 256KB for Vitesse 7385 Switch firmware */
++					reg = <0x0 0x00040000>;
++					label = "NOR (RO) Vitesse-7385 Firmware";
++					read-only;
++				};
+ 
+-			partition@400000 {
+-				/* 11MB for JFFS2 based Root file System */
+-				reg = <0x00400000 0x00b00000>;
+-				label = "NOR (RW) JFFS2 Root File System";
+-			};
++				partition@40000 {
++					compatible = "denx,fit";
++					reg = <0x00040000 0x00ec0000>;
++					label = "firmware";
++				};
+ 
+-			partition@f00000 {
+-				/* This location must not be altered  */
+-				/* 512KB for u-boot Bootloader Image */
+-				/* 512KB for u-boot Environment Variables */
+-				reg = <0x00f00000 0x00100000>;
+-				label = "NOR (RO) U-Boot Image";
+-				read-only;
++				partition@f00000 {
++					/* This location must not be altered  */
++					/* 512KB for u-boot Bootloader Image */
++					/* 512KB for u-boot Environment Variables */
++					reg = <0x00f00000 0x00100000>;
++					label = "u-boot";
++					read-only;
++				};
+ 			};
+ 		};
+ 
+@@ -144,13 +140,43 @@
+ 	soc: soc@ffe00000 {
+ 		ranges = <0x0 0x0 0xffe00000 0x100000>;
+ 
++		gpio0: gpio-controller@fc00 {
++		};
++
+ 		i2c@3000 {
++			temperature-sensor@4c {
++				compatible = "adi,adt7461";
++				reg = <0x4c>;
++			};
++
++			eeprom@50 {
++				compatible = "atmel,24c256";
++				reg = <0x50>;
++			};
++
+ 			rtc@68 {
+ 				compatible = "dallas,ds1339";
+ 				reg = <0x68>;
+ 			};
+ 		};
+ 
++		i2c@3100 {
++			pmic@11 {
++				compatible = "zl2006";
++				reg = <0x11>;
++			};
++
++			gpio@18 {
++				compatible = "nxp,pca9557";
++				reg = <0x18>;
++			};
++
++			eeprom@52 {
++				compatible = "atmel,24c01";
++				reg = <0x52>;
++			};
++		};
++
+ 		spi@7000 {
+ 			flash@0 {
+ 				#address-cells = <1>;
+@@ -204,10 +230,12 @@
+ 			phy0: ethernet-phy@0 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x0>;
++				reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ 			};
+ 			phy1: ethernet-phy@1 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x1>;
++				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ 			};
+ 			tbi-phy@2 {
+ 				device_type = "tbi-phy";
diff --git a/target/linux/mpc85xx/patches-4.19/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch b/target/linux/mpc85xx/patches-4.19/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch
new file mode 100644
index 0000000000..39c72314b8
--- /dev/null
+++ b/target/linux/mpc85xx/patches-4.19/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch
@@ -0,0 +1,170 @@
+From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Sun, 30 Dec 2018 23:24:41 +0100
+Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT
+
+This patch apply chages for OpenWRT in P2020RDB
+dts file.
+
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++---------
+ 1 file changed, 63 insertions(+), 35 deletions(-)
+
+--- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts
++++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts
+@@ -2,6 +2,7 @@
+  * P2020 RDB Device Tree Source
+  *
+  * Copyright 2009-2012 Freescale Semiconductor Inc.
++ * Copyright 2018      Pawel Dembicki <paweldembicki@gmail.com>
+  *
+  * This program is free software; you can redistribute  it and/or modify it
+  * under  the terms of  the GNU General  Public License as published by the
+@@ -9,10 +10,15 @@
+  * option) any later version.
+  */
+ 
++/dts-v1/;
++
+ /include/ "p2020si-pre.dtsi"
+ 
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
+ / {
+-	model = "fsl,P2020RDB";
++	model = "Freescale P2020RDB";
+ 	compatible = "fsl,P2020RDB";
+ 
+ 	aliases {
+@@ -38,48 +44,38 @@
+ 			  0x2 0x0 0x0 0xffb00000 0x00020000>;
+ 
+ 		nor@0,0 {
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+ 			compatible = "cfi-flash";
+ 			reg = <0x0 0x0 0x1000000>;
+ 			bank-width = <2>;
+ 			device-width = <1>;
+ 
+-			partition@0 {
+-				/* This location must not be altered  */
+-				/* 256KB for Vitesse 7385 Switch firmware */
+-				reg = <0x0 0x00040000>;
+-				label = "NOR (RO) Vitesse-7385 Firmware";
+-				read-only;
+-			};
+-
+-			partition@40000 {
+-				/* 256KB for DTB Image */
+-				reg = <0x00040000 0x00040000>;
+-				label = "NOR (RO) DTB Image";
+-				read-only;
+-			};
++			partitions {
++				compatible = "fixed-partitions";
++				#address-cells = <1>;
++				#size-cells = <1>;
+ 
+-			partition@80000 {
+-				/* 3.5 MB for Linux Kernel Image */
+-				reg = <0x00080000 0x00380000>;
+-				label = "NOR (RO) Linux Kernel Image";
+-				read-only;
+-			};
++				partition@0 {
++					/* This location must not be altered  */
++					/* 256KB for Vitesse 7385 Switch firmware */
++					reg = <0x0 0x00040000>;
++					label = "NOR (RO) Vitesse-7385 Firmware";
++					read-only;
++				};
+ 
+-			partition@400000 {
+-				/* 11MB for JFFS2 based Root file System */
+-				reg = <0x00400000 0x00b00000>;
+-				label = "NOR (RW) JFFS2 Root File System";
+-			};
++				partition@40000 {
++					compatible = "denx,fit";
++					reg = <0x00040000 0x00ec0000>;
++					label = "firmware";
++				};
+ 
+-			partition@f00000 {
+-				/* This location must not be altered  */
+-				/* 512KB for u-boot Bootloader Image */
+-				/* 512KB for u-boot Environment Variables */
+-				reg = <0x00f00000 0x00100000>;
+-				label = "NOR (RO) U-Boot Image";
+-				read-only;
++				partition@f00000 {
++					/* This location must not be altered  */
++					/* 512KB for u-boot Bootloader Image */
++					/* 512KB for u-boot Environment Variables */
++					reg = <0x00f00000 0x00100000>;
++					label = "u-boot";
++					read-only;
++				};
+ 			};
+ 		};
+ 
+@@ -144,13 +140,43 @@
+ 	soc: soc@ffe00000 {
+ 		ranges = <0x0 0x0 0xffe00000 0x100000>;
+ 
++		gpio0: gpio-controller@fc00 {
++		};
++
+ 		i2c@3000 {
++			temperature-sensor@4c {
++				compatible = "adi,adt7461";
++				reg = <0x4c>;
++			};
++
++			eeprom@50 {
++				compatible = "atmel,24c256";
++				reg = <0x50>;
++			};
++
+ 			rtc@68 {
+ 				compatible = "dallas,ds1339";
+ 				reg = <0x68>;
+ 			};
+ 		};
+ 
++		i2c@3100 {
++			pmic@11 {
++				compatible = "zl2006";
++				reg = <0x11>;
++			};
++
++			gpio@18 {
++				compatible = "nxp,pca9557";
++				reg = <0x18>;
++			};
++
++			eeprom@52 {
++				compatible = "atmel,24c01";
++				reg = <0x52>;
++			};
++		};
++
+ 		spi@7000 {
+ 			flash@0 {
+ 				#address-cells = <1>;
+@@ -204,10 +230,12 @@
+ 			phy0: ethernet-phy@0 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x0>;
++				reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ 			};
+ 			phy1: ethernet-phy@1 {
+ 				interrupts = <3 1 0 0>;
+ 				reg = <0x1>;
++				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ 			};
+ 			tbi-phy@2 {
+ 				device_type = "tbi-phy";