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authorMathias Kresin <dev@kresin.me>2021-11-02 23:35:32 +0100
committerMathias Kresin <dev@kresin.me>2021-11-14 20:15:42 +0100
commite6f8cf622318e65a00a5322509707f3f25cef68e (patch)
tree69a94a805032d18f3b270ebbbbbbc05059210e2d
parent87b8f095af9f7e6ff5edae6778d967f91e779cf2 (diff)
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uboot-lantiq: danube: fix SPL boot
On danube we only have 0x6800 bytes of usable SRAM. Everything behind can't be written to and a SPL u-boot locks up during boot. Since it's a hard to debug issue and took me more than two years to fix it, I consider it worth to include fix albeit SPL u-boots are not build in OpenWrt. I faced the issue while trying to shrink the u-boot to 64K since some boards only have an u-boot partition of that size from the days ifx-uboot was used. Signed-off-by: Mathias Kresin <dev@kresin.me> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-rw-r--r--package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch34
1 files changed, 34 insertions, 0 deletions
diff --git a/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch b/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch
new file mode 100644
index 0000000000..6cb309b8f2
--- /dev/null
+++ b/package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch
@@ -0,0 +1,34 @@
+From 65f1f160139c2bac83650c9c7c4aee4e5fd74c7c Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Sun, 2 May 2021 02:03:05 +0200
+Subject: [PATCH] MIPS: lantiq: danube: fix SPL boot
+
+On danube we only have 0x6800 bytes of usable SRAM. Everything behind
+can't be written to and a SPL u-boot locks up during boot.
+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+---
+ arch/mips/include/asm/arch-danube/config.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/include/asm/arch-danube/config.h
++++ b/arch/mips/include/asm/arch-danube/config.h
+@@ -61,7 +61,7 @@
+
+ /* SRAM */
+ #define CONFIG_SYS_SRAM_BASE 0xBE1A0000
+-#define CONFIG_SYS_SRAM_SIZE 0x10000
++#define CONFIG_SYS_SRAM_SIZE 0x6800
+
+ /* ASC/UART driver and console */
+ #define CONFIG_LANTIQ_SERIAL
+@@ -117,7 +117,7 @@
+ #define CONFIG_CMD_NET
+ #endif
+
+-#define CONFIG_SPL_MAX_SIZE (32 * 1024)
++#define CONFIG_SPL_MAX_SIZE (18 * 1024)
+ #define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024)
+ #define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024)
+ #define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024)