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authorDaniel Kestrel <kestrel1974@t-online.de>2021-05-31 14:13:42 +0200
committerHauke Mehrtens <hauke@hauke-m.de>2022-01-06 00:22:18 +0100
commitc8967d6d12b25cf50b7e060485004c1332a40367 (patch)
tree08c79afdbe6d1fcb8e6b538ad81873c1e33eb5b2
parent8dafa98bfb545cb6c014f6e85bc3fd6a78834c6c (diff)
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ltq-deu: set correct control register for AES
Some devices initialize AES during boot and AES works out of the box and the correct endianess is set. NDC means (No Danube Compatibility Mode) and the endianess setting has no effect if its set to 0. NDC 0: OFF ENDI bit cannot be written as in Danube To make it work for other devices, the NDC control register needs to be set to 1. Signed-off-by: Daniel Kestrel <kestrel1974@t-online.de>
-rw-r--r--package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
index aaa7bce237..8063672613 100644
--- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
+++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
@@ -107,7 +107,7 @@ void aes_chip_init (void)
// start crypto engine with write to ILR
aes->controlr.SM = 1;
- aes->controlr.NDC = 0;
+ aes->controlr.NDC = 1;
asm("sync");
aes->controlr.ENDI = 1;
asm("sync");