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authorGabor Juhos <juhosg@openwrt.org>2011-12-05 18:21:15 +0000
committerGabor Juhos <juhosg@openwrt.org>2011-12-05 18:21:15 +0000
commitada92aee62143b12ffa408edcf52797e8cb8074f (patch)
treeb4f1c4026dc6da19dcb448c568e9d2db38ab5f19
parentc6bcf8d1d844cb5375b4115d63e83c537908a6c1 (diff)
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ar71xx: don't register PCI controller on AR934x if PCIE_RC bit is not set
SVN-Revision: 29456
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/pci.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/pci.c b/target/linux/ar71xx/files/arch/mips/ar71xx/pci.c
index 8850c0b6b0..f3c6452418 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/pci.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/pci.c
@@ -68,6 +68,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
{
+ u32 t;
int ret = 0;
switch (ar71xx_soc) {
@@ -86,9 +87,13 @@ int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344:
- ret = ar724x_pcibios_init(AR934X_IP2_IRQ_PCIE);
- break;
+ t = ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+ if (t & AR934X_BOOTSTRAP_PCIE_RC) {
+ ret = ar724x_pcibios_init(AR934X_IP2_IRQ_PCIE);
+ break;
+ }
+ /* fall through */
default:
return 0;
}