kernel: backport a MIPS SMP icache flush fix

Signed-off-by: Felix Fietkau <nbd@nbd.name>

1 files changed, 38 insertions, 0 deletions

diff --git a/target/linux/generic/patches-4.4/094-MIPS-c-r4k-Fix-size-calc-when-avoiding-IPIs-for-smal.patch b/target/linux/generic/patches-4.4/094-MIPS-c-r4k-Fix-size-calc-when-avoiding-IPIs-for-smal.patch
new file mode 100644
index 0000000000..733d9c77b3
--- /dev/null
+++ b/target/linux/generic/patches-4.4/094-MIPS-c-r4k-Fix-size-calc-when-avoiding-IPIs-for-smal.patch
@@ -0,0 +1,38 @@
+From: Paul Burton <paul.burton@imgtec.com>
+Date: Mon, 5 Sep 2016 15:24:54 +0100
+Subject: [PATCH] MIPS: c-r4k: Fix size calc when avoiding IPIs for small
+ icache flushes
+
+Commit f70ddc07b637 ("MIPS: c-r4k: Avoid small flush_icache_range SMP
+calls") adds checks to force use of hit-type cache ops for small icache
+flushes where they are globalised & index-type cache ops aren't, in
+order to avoid the overhead of IPIs in those cases. However it
+calculated the size of the region being flushed incorrectly, subtracting
+the end address from the start address rather than the reverse. This
+would have led to an overflow with size wrapping round to some large
+value, and likely to the special case for avoiding IPIs not actually
+being hit.
+
+Signed-off-by: Paul Burton <paul.burton@imgtec.com>
+Cc: James Hogan <james.hogan@imgtec.com>
+Fixes: f70ddc07b637 ("MIPS: c-r4k: Avoid small flush_icache_range SMP calls")
+Reviewed-by: James Hogan <james.hogan@imgtec.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Cc: Huacai Chen <chenhc@lemote.com>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/14211/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -781,7 +781,7 @@ static void r4k_flush_icache_range(unsig
+ 		 * If address-based cache ops are globalized, then we may be
+ 		 * able to avoid the IPI for small flushes.
+ 		 */
+-		size = start - end;
++		size = end - start;
+ 		cache_size = icache_size;
+ 		if (!cpu_has_ic_fills_f_dc) {
+ 			size *= 2;