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| author | Christian Lamparter <chunkeey@gmail.com> | 2020-08-12 18:26:43 +0200 |
|---|---|---|
| committer | Christian Lamparter <chunkeey@gmail.com> | 2020-08-29 17:14:44 +0200 |
| commit | 9153955095f01a7ac5f2659a671f0229cbad3507 (patch) | |
| tree | d9a9e6fe62326b9728d7f50e2183ff2ffab9bbff | |
| parent | b15420fc6c55bccb4c773e5c095a07eb30459bcb (diff) | |
| download | upstream-9153955095f01a7ac5f2659a671f0229cbad3507.tar.gz upstream-9153955095f01a7ac5f2659a671f0229cbad3507.tar.bz2 upstream-9153955095f01a7ac5f2659a671f0229cbad3507.zip | |
apm821xx: MR24: enumerate PCIe in device-tree
This patch adds the pcie-switch and bridge configuration for
the Meraki MR24.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
| -rw-r--r-- | target/linux/apm821xx/dts/meraki-mr24.dts | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/target/linux/apm821xx/dts/meraki-mr24.dts b/target/linux/apm821xx/dts/meraki-mr24.dts index 8fdef7c171..97a69e71d1 100644 --- a/target/linux/apm821xx/dts/meraki-mr24.dts +++ b/target/linux/apm821xx/dts/meraki-mr24.dts @@ -182,6 +182,57 @@ &PCIE0 { status = "okay"; + /* + * relevant lspci topology: + * + * -+-[0000:40]---00.0-[41-7f]----00.0-[42-45]--+-02.0-[43]----00.0 + * +-03.0-[44]----00.0 + * + */ + + bridge@64,0 { + reg = <0x00400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + bridge@65,0 { + /* IDT PES3T3 PCI Express Switch */ + compatible = "pci111d,8039"; + reg = <0x00410000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + bridge@66,2 { + compatible = "pci111d,8039"; + reg = <0x00421000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@67,0 { + /* Atheros AR9380 2.4GHz */ + compatible = "pci168c,0030"; + reg = <0x00430000 0 0 0 0>; + }; + }; + + bridge@66,3 { + compatible = "pci111d,8039"; + reg = <0x00421800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@68,0 { + /* Atheros AR9380 5GHz */ + compatible = "pci168c,0030"; + reg = <0x00440000 0 0 0 0>; + }; + }; + }; + }; }; &MSI { |