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| author | John Crispin <john@openwrt.org> | 2015-09-16 08:29:40 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-09-16 08:29:40 +0000 |
| commit | 710520d5c73bc5b047184ca0a00bf7f0ea80d510 (patch) | |
| tree | d641d579c9ef526494f3bb80773c7efffb84b52b | |
| parent | 6f07b8a6594f14a5d8d659b4b34fec0484759ae0 (diff) | |
| download | upstream-710520d5c73bc5b047184ca0a00bf7f0ea80d510.tar.gz upstream-710520d5c73bc5b047184ca0a00bf7f0ea80d510.tar.bz2 upstream-710520d5c73bc5b047184ca0a00bf7f0ea80d510.zip | |
ramips: make the mt7628 spi driver work for both cs lines
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 46951
| -rw-r--r-- | target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch index 9ee8893550..762462f95d 100644 --- a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch @@ -1,6 +1,6 @@ --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -439,6 +439,12 @@ config SPI_RT2880 +@@ -439,6 +439,12 @@ help This selects a driver for the Ralink RT288x/RT305x SPI Controller. @@ -15,7 +15,7 @@ depends on ARCH_S3C24XX --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70l +@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o @@ -25,7 +25,7 @@ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o --- /dev/null +++ b/drivers/spi/spi-mt7621.c -@@ -0,0 +1,315 @@ +@@ -0,0 +1,314 @@ +/* + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver + * @@ -111,12 +111,11 @@ +static void mt7621_spi_set_cs(struct spi_device *spi, int enable) +{ + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi); -+ u32 polar = mt7621_spi_read(rs, MT7621_SPI_POLAR); ++ int cs = spi->chip_select; ++ u32 polar = 0; + + if (enable) -+ polar |= 1; -+ else -+ polar &= ~1; ++ polar = BIT(cs); + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar); +} + @@ -290,7 +289,7 @@ + master->transfer_one_message = mt7621_spi_transfer_one_message; + master->bits_per_word_mask = SPI_BPW_MASK(8); + master->dev.of_node = pdev->dev.of_node; -+ master->num_chipselect = 1; ++ master->num_chipselect = 2; + + dev_set_drvdata(&pdev->dev, master); + |